1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 55 unchanged lines hidden (view full) --- 64ISA::params() const 65{ 66 return dynamic_cast<const Params *>(_params); 67} 68 69void 70ISA::clear() 71{ |
72 const Params *p(params()); 73 |
74 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; |
75 memset(miscRegs, 0, sizeof(miscRegs)); 76 CPSR cpsr = 0; 77 cpsr.mode = MODE_USER; 78 miscRegs[MISCREG_CPSR] = cpsr; 79 updateRegMap(cpsr); 80 81 SCTLR sctlr = 0; 82 sctlr.te = (bool)sctlr_rst.te; 83 sctlr.nmfi = (bool)sctlr_rst.nmfi; 84 sctlr.v = (bool)sctlr_rst.v; 85 sctlr.u = 1; 86 sctlr.xp = 1; 87 sctlr.rao2 = 1; 88 sctlr.rao3 = 1; 89 sctlr.rao4 = 1; 90 miscRegs[MISCREG_SCTLR] = sctlr; 91 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 92 |
93 /* Start with an event in the mailbox */ 94 miscRegs[MISCREG_SEV_MAILBOX] = 1; 95 96 // Separate Instruction and Data TLBs. 97 miscRegs[MISCREG_TLBTR] = 1; 98 99 MVFR0 mvfr0 = 0; 100 mvfr0.advSimdRegisters = 2; --- 44 unchanged lines hidden (view full) --- 145 (2 << 10) | // 11:10 146 (0 << 8) | // 9:8 147 (3 << 6) | // 7:6 148 (2 << 4) | // 5:4 149 (0 << 2) | // 3:2 150 0; // 1:0 151 152 miscRegs[MISCREG_CPACR] = 0; |
153 |
154 // Initialize configurable default values 155 miscRegs[MISCREG_MIDR] = p->midr; |
156 |
157 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 158 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 159 160 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 161 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 162 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 163 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 164 165 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 166 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 167 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 168 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 169 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 170 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 171 172 173 miscRegs[MISCREG_FPSID] = p->fpsid; 174 175 |
176 //XXX We need to initialize the rest of the state. 177} 178 179MiscReg 180ISA::readMiscRegNoEffect(int misc_reg) 181{ 182 assert(misc_reg < NumMiscRegs); 183 --- 35 unchanged lines hidden (view full) --- 219 return 0x80000000 | // multiprocessor extensions available 220 tc->cpuId(); 221 } else { 222 return 0x80000000 | // multiprocessor extensions available 223 0x40000000 | // in up system 224 tc->cpuId(); 225 } 226 break; |
227 case MISCREG_CLIDR: 228 warn_once("The clidr register always reports 0 caches.\n"); 229 warn_once("clidr LoUIS field of 0b001 to match current " 230 "ARM implementations.\n"); 231 return 0x00200000; 232 case MISCREG_CCSIDR: 233 warn_once("The ccsidr register isn't implemented and " 234 "always reads as 0.\n"); 235 break; |
236 case MISCREG_CTR: 237 { 238 //all caches have the same line size in gem5 239 //4 byte words in ARM 240 unsigned lineSizeWords = 241 tc->getCpuPtr()->getInstPort().peerBlockSize() / 4; 242 unsigned log2LineSizeWords = 0; 243 --- 210 unchanged lines hidden (view full) --- 454 CheckerCPU *checker = oc->getCheckerCpuPtr(); 455 if (checker) { 456 checker->getDTBPtr()->allCpusCaching(); 457 checker->getITBPtr()->allCpusCaching(); 458 } 459 } 460 return; 461 } |
462 463 case MISCREG_MIDR: 464 case MISCREG_ID_PFR0: 465 case MISCREG_ID_PFR1: 466 case MISCREG_ID_MMFR0: 467 case MISCREG_ID_MMFR1: 468 case MISCREG_ID_MMFR2: 469 case MISCREG_ID_MMFR3: 470 case MISCREG_ID_ISAR0: 471 case MISCREG_ID_ISAR1: 472 case MISCREG_ID_ISAR2: 473 case MISCREG_ID_ISAR3: 474 case MISCREG_ID_ISAR4: 475 case MISCREG_ID_ISAR5: 476 477 case MISCREG_MPIDR: 478 case MISCREG_FPSID: |
479 case MISCREG_TLBTR: 480 case MISCREG_MVFR0: 481 case MISCREG_MVFR1: |
482 // ID registers are constants. |
483 return; |
484 |
485 case MISCREG_TLBIALLIS: 486 case MISCREG_TLBIALL: 487 sys = tc->getSystemPtr(); 488 for (x = 0; x < sys->numContexts(); x++) { 489 oc = sys->getThreadContext(x); 490 assert(oc->getITBPtr() && oc->getDTBPtr()); 491 oc->getITBPtr()->flushAll(); 492 oc->getDTBPtr()->flushAll(); --- 186 unchanged lines hidden --- |