1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 213 unchanged lines hidden (view full) --- 222 miscRegName[misc_reg]); 223 break; 224 case MISCREG_CPSR_Q: 225 panic("shouldn't be reading this register seperately\n"); 226 case MISCREG_FPSCR_QC: 227 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 228 case MISCREG_FPSCR_EXC: 229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; |
230 case MISCREG_L2CTLR: 231 // mostly unimplemented, just set NumCPUs field from sim and return 232 L2CTLR l2ctlr = 0; 233 // b00:1CPU to b11:4CPUs 234 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 235 return l2ctlr; |
236 } 237 return readMiscRegNoEffect(misc_reg); 238} 239 240void 241ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 242{ 243 assert(misc_reg < NumMiscRegs); --- 294 unchanged lines hidden (view full) --- 538 break; 539 case MISCREG_CPSR_MODE: 540 // This miscreg is used by copy*Regs to set the CPSR mode 541 // without updating other CPSR variables. It's used to 542 // make sure the register map is in such a state that we can 543 // see all of the registers for the copy. 544 updateRegMap(val); 545 return; |
546 case MISCREG_L2CTLR: 547 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 548 miscRegName[misc_reg], uint32_t(val)); |
549 } 550 } 551 setMiscRegNoEffect(misc_reg, newVal); 552} 553 554} |