1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 346 unchanged lines hidden (view full) --- 355 { 356 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 357 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 358 SCTLR new_sctlr = newVal; 359 new_sctlr.nmfi = (bool)sctlr.nmfi; 360 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 361 tc->getITBPtr()->invalidateMiscReg(); 362 tc->getDTBPtr()->invalidateMiscReg(); |
363 364 // Check if all CPUs are booted with caches enabled 365 // so we can stop enforcing coherency of some kernel 366 // structures manually. 367 sys = tc->getSystemPtr(); 368 for (x = 0; x < sys->numContexts(); x++) { 369 oc = sys->getThreadContext(x); 370 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 371 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 372 return; 373 } 374 375 for (x = 0; x < sys->numContexts(); x++) { 376 oc = sys->getThreadContext(x); 377 oc->getDTBPtr()->allCpusCaching(); 378 oc->getITBPtr()->allCpusCaching(); 379 } |
380 return; 381 } 382 case MISCREG_TLBTR: 383 case MISCREG_MVFR0: 384 case MISCREG_MVFR1: 385 case MISCREG_MPIDR: 386 case MISCREG_FPSID: 387 return; --- 158 unchanged lines hidden --- |