1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 777 unchanged lines hidden (view full) --- 786 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 787 int old_mode = old_cpsr.mode; 788 CPSR cpsr = val; 789 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 790 getITBPtr(tc)->invalidateMiscReg(); 791 getDTBPtr(tc)->invalidateMiscReg(); 792 } 793 |
794 if (cpsr.pan != old_cpsr.pan) { 795 getDTBPtr(tc)->invalidateMiscReg(); 796 } 797 |
798 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 799 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 800 PCState pc = tc->pcState(); 801 pc.nextThumb(cpsr.t); 802 pc.nextJazelle(cpsr.j); 803 pc.illegalExec(cpsr.il == 1); 804 805 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); --- 1375 unchanged lines hidden --- |