1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1581 unchanged lines hidden (view full) --- 1590 } 1591 // If we're in timing mode then doing the translation in 1592 // functional mode then we're slightly distorting performance 1593 // results obtained from simulations. The translation should be 1594 // done in the same mode the core is running in. NOTE: This 1595 // can't be an atomic translation because that causes problems 1596 // with unexpected atomic snoop requests. 1597 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); |
1598 1599 auto req = std::make_shared<Request>( 1600 0, val, 0, flags, Request::funcMasterId, 1601 tc->pcState().pc(), tc->contextId()); 1602 |
1603 fault = getDTBPtr(tc)->translateFunctional( |
1604 req, tc, mode, tranType); 1605 |
1606 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1607 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1608 1609 MiscReg newVal; 1610 if (fault == NoFault) { |
1611 Addr paddr = req->getPaddr(); |
1612 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1613 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1614 newVal = (paddr & mask(39, 12)) | 1615 (getDTBPtr(tc)->getAttr()); 1616 } else { 1617 newVal = (paddr & 0xfffff000) | 1618 (getDTBPtr(tc)->getAttr()); 1619 } --- 153 unchanged lines hidden (view full) --- 1773 case MISCREG_AT_S1E2W_Xt: 1774 case MISCREG_AT_S12E1R_Xt: 1775 case MISCREG_AT_S12E1W_Xt: 1776 case MISCREG_AT_S12E0R_Xt: 1777 case MISCREG_AT_S12E0W_Xt: 1778 case MISCREG_AT_S1E3R_Xt: 1779 case MISCREG_AT_S1E3W_Xt: 1780 { |
1781 RequestPtr req = std::make_shared<Request>(); |
1782 Request::Flags flags = 0; 1783 BaseTLB::Mode mode = BaseTLB::Read; 1784 TLB::ArmTranslationType tranType = TLB::NormalTran; 1785 Fault fault; 1786 switch(misc_reg) { 1787 case MISCREG_AT_S1E1R_Xt: 1788 flags = TLB::MustBeOne; 1789 tranType = TLB::S1E1Tran; --- 102 unchanged lines hidden (view full) --- 1892 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1893 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1894 newVal |= 1 << 11; // RES1 1895 } 1896 DPRINTF(MiscRegs, 1897 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1898 val, fsr, newVal); 1899 } |
1900 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1901 return; 1902 } 1903 case MISCREG_SPSR_EL3: 1904 case MISCREG_SPSR_EL2: 1905 case MISCREG_SPSR_EL1: 1906 // Force bits 23:21 to 0 1907 newVal = val & ~(0x7 << 21); --- 44 unchanged lines hidden --- |