1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 696 unchanged lines hidden (view full) --- 705 706} // anonymous namespace 707 708void 709ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 710{ 711 712 MiscReg newVal = val; |
713 bool secure_lookup; 714 bool hyp; |
715 uint8_t target_el; 716 uint16_t asid; 717 SCR scr; 718 719 if (misc_reg == MISCREG_CPSR) { 720 updateRegMap(val); 721 722 --- 298 unchanged lines hidden (view full) --- 1021 1022 // TLBI all entries, EL0&1 inner sharable (ignored) 1023 case MISCREG_TLBIALLIS: 1024 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1025 assert32(tc); 1026 target_el = 1; // el 0 and 1 are handled together 1027 scr = readMiscReg(MISCREG_SCR, tc); 1028 secure_lookup = haveSecurity && !scr.ns; |
1029 tlbiALL(tc, secure_lookup, target_el); |
1030 return; 1031 // TLBI all entries, EL0&1, instruction side 1032 case MISCREG_ITLBIALL: 1033 assert32(tc); 1034 target_el = 1; // el 0 and 1 are handled together 1035 scr = readMiscReg(MISCREG_SCR, tc); 1036 secure_lookup = haveSecurity && !scr.ns; 1037 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el); --- 13 unchanged lines hidden (view full) --- 1051 // regardless of the level of lookup, since in gem5 we cache 1052 // in the tlb the last level of lookup only. 1053 case MISCREG_TLBIMVA: 1054 case MISCREG_TLBIMVAIS: 1055 assert32(tc); 1056 target_el = 1; // el 0 and 1 are handled together 1057 scr = readMiscReg(MISCREG_SCR, tc); 1058 secure_lookup = haveSecurity && !scr.ns; |
1059 tlbiVA(tc, mbits(newVal, 31, 12), bits(newVal, 7,0), 1060 secure_lookup, target_el); |
1061 return; 1062 // TLBI by ASID, EL0&1, inner sharable 1063 case MISCREG_TLBIASIDIS: 1064 case MISCREG_TLBIASID: 1065 assert32(tc); 1066 target_el = 1; // el 0 and 1 are handled together 1067 scr = readMiscReg(MISCREG_SCR, tc); 1068 secure_lookup = haveSecurity && !scr.ns; |
1069 asid = bits(newVal, 7,0); 1070 tlbiASID(tc, asid, secure_lookup, target_el); |
1071 return; 1072 // TLBI by address, EL0&1, inner sharable (ignored) 1073 case MISCREG_TLBIMVAAL: 1074 case MISCREG_TLBIMVAALIS: 1075 // mcr tlbimvaal(is) is invalidating all matching entries 1076 // regardless of the level of lookup, since in gem5 we cache 1077 // in the tlb the last level of lookup only. 1078 case MISCREG_TLBIMVAA: 1079 case MISCREG_TLBIMVAAIS: 1080 assert32(tc); 1081 target_el = 1; // el 0 and 1 are handled together 1082 scr = readMiscReg(MISCREG_SCR, tc); 1083 secure_lookup = haveSecurity && !scr.ns; 1084 hyp = 0; |
1085 tlbiMVA(tc, mbits(newVal, 31,12), secure_lookup, hyp, target_el); |
1086 return; 1087 // TLBI by address, EL2, hypervisor mode 1088 case MISCREG_TLBIMVALH: 1089 case MISCREG_TLBIMVALHIS: 1090 // mcr tlbimvalh(is) is invalidating all matching entries 1091 // regardless of the level of lookup, since in gem5 we cache 1092 // in the tlb the last level of lookup only. 1093 case MISCREG_TLBIMVAH: 1094 case MISCREG_TLBIMVAHIS: 1095 assert32(tc); 1096 target_el = 1; // aarch32, use hyp bit 1097 scr = readMiscReg(MISCREG_SCR, tc); 1098 secure_lookup = haveSecurity && !scr.ns; 1099 hyp = 1; |
1100 tlbiMVA(tc, mbits(newVal, 31,12), secure_lookup, hyp, target_el); |
1101 return; 1102 case MISCREG_TLBIIPAS2L: 1103 case MISCREG_TLBIIPAS2LIS: 1104 // mcr tlbiipas2l(is) is invalidating all matching entries 1105 // regardless of the level of lookup, since in gem5 we cache 1106 // in the tlb the last level of lookup only. 1107 case MISCREG_TLBIIPAS2: 1108 case MISCREG_TLBIIPAS2IS: --- 91 unchanged lines hidden (view full) --- 1200 case MISCREG_TLBI_VAE3_Xt: 1201 // TLBI by VA, EL3 regime stage 1, last level walk 1202 case MISCREG_TLBI_VALE3IS_Xt: 1203 case MISCREG_TLBI_VALE3_Xt: 1204 assert64(tc); 1205 target_el = 3; 1206 asid = 0xbeef; // does not matter, tlbi is global 1207 secure_lookup = true; |
1208 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12, 1209 asid, secure_lookup, target_el); |
1210 return; 1211 // TLBI by VA, EL2 1212 case MISCREG_TLBI_VAE2IS_Xt: 1213 case MISCREG_TLBI_VAE2_Xt: 1214 // TLBI by VA, EL2, stage1 last level walk 1215 case MISCREG_TLBI_VALE2IS_Xt: 1216 case MISCREG_TLBI_VALE2_Xt: 1217 assert64(tc); 1218 target_el = 2; 1219 asid = 0xbeef; // does not matter, tlbi is global 1220 scr = readMiscReg(MISCREG_SCR, tc); 1221 secure_lookup = haveSecurity && !scr.ns; |
1222 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12, 1223 asid, secure_lookup, target_el); |
1224 return; 1225 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1226 case MISCREG_TLBI_VAE1IS_Xt: 1227 case MISCREG_TLBI_VAE1_Xt: 1228 case MISCREG_TLBI_VALE1IS_Xt: 1229 case MISCREG_TLBI_VALE1_Xt: 1230 assert64(tc); 1231 asid = bits(newVal, 63, 48); 1232 target_el = 1; // el 0 and 1 are handled together 1233 scr = readMiscReg(MISCREG_SCR, tc); 1234 secure_lookup = haveSecurity && !scr.ns; |
1235 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12, 1236 asid, secure_lookup, target_el); |
1237 return; 1238 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1239 // @todo: handle VMID to enable Virtualization 1240 case MISCREG_TLBI_ASIDE1IS_Xt: 1241 case MISCREG_TLBI_ASIDE1_Xt: 1242 assert64(tc); 1243 target_el = 1; // el 0 and 1 are handled together 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 secure_lookup = haveSecurity && !scr.ns; |
1246 asid = bits(newVal, 63, 48); 1247 tlbiASID(tc, asid, secure_lookup, target_el); |
1248 return; 1249 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1250 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1251 // entries from the last level of translation table walks 1252 // @todo: handle VMID to enable Virtualization 1253 case MISCREG_TLBI_VAAE1IS_Xt: 1254 case MISCREG_TLBI_VAAE1_Xt: 1255 case MISCREG_TLBI_VAALE1IS_Xt: 1256 case MISCREG_TLBI_VAALE1_Xt: 1257 assert64(tc); 1258 target_el = 1; // el 0 and 1 are handled together 1259 scr = readMiscReg(MISCREG_SCR, tc); 1260 secure_lookup = haveSecurity && !scr.ns; |
1261 tlbiMVA(tc, 1262 ((Addr)bits(newVal, 43, 0)) << 12, |
1263 secure_lookup, false, target_el); |
1264 return; 1265 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1266 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1267 case MISCREG_TLBI_IPAS2LE1_Xt: 1268 case MISCREG_TLBI_IPAS2E1IS_Xt: 1269 case MISCREG_TLBI_IPAS2E1_Xt: 1270 assert64(tc); 1271 target_el = 1; // EL 0 and 1 are handled together --- 442 unchanged lines hidden (view full) --- 1714 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1715 break; 1716 } 1717 } 1718 setMiscRegNoEffect(misc_reg, newVal); 1719} 1720 1721void |
1722ISA::tlbiVA(ThreadContext *tc, Addr va, uint16_t asid, |
1723 bool secure_lookup, uint8_t target_el) 1724{ 1725 if (!haveLargeAsid64) 1726 asid &= mask(8); |
1727 System *sys = tc->getSystemPtr(); 1728 for (int x = 0; x < sys->numContexts(); x++) { 1729 ThreadContext *oc = sys->getThreadContext(x); 1730 getITBPtr(oc)->flushMvaAsid(va, asid, 1731 secure_lookup, target_el); 1732 getDTBPtr(oc)->flushMvaAsid(va, asid, 1733 secure_lookup, target_el); 1734 --- 40 unchanged lines hidden (view full) --- 1775 if (checker) { 1776 getITBPtr(checker)->flushAllNs(hyp, target_el); 1777 getDTBPtr(checker)->flushAllNs(hyp, target_el); 1778 } 1779 } 1780} 1781 1782void |
1783ISA::tlbiMVA(ThreadContext *tc, Addr va, bool secure_lookup, bool hyp, |
1784 uint8_t target_el) 1785{ 1786 System *sys = tc->getSystemPtr(); 1787 for (int x = 0; x < sys->numContexts(); x++) { 1788 ThreadContext *oc = sys->getThreadContext(x); |
1789 getITBPtr(oc)->flushMva(va, secure_lookup, hyp, target_el); 1790 getDTBPtr(oc)->flushMva(va, secure_lookup, hyp, target_el); |
1791 1792 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1793 if (checker) { |
1794 getITBPtr(checker)->flushMva(va, secure_lookup, hyp, target_el); 1795 getDTBPtr(checker)->flushMva(va, secure_lookup, hyp, target_el); |
1796 } 1797 } 1798} 1799 1800void 1801ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, 1802 uint8_t target_el) 1803{ --- 11 unchanged lines hidden (view full) --- 1815 getITBPtr(checker)->flushIpaVmid(ipa, 1816 secure_lookup, false, target_el); 1817 getDTBPtr(checker)->flushIpaVmid(ipa, 1818 secure_lookup, false, target_el); 1819 } 1820 } 1821} 1822 |
1823void 1824ISA::tlbiASID(ThreadContext *tc, uint16_t asid, bool secure_lookup, 1825 uint8_t target_el) 1826{ 1827 if (!haveLargeAsid64) 1828 asid &= mask(8); 1829 1830 System *sys = tc->getSystemPtr(); 1831 for (auto x = 0; x < sys->numContexts(); x++) { 1832 tc = sys->getThreadContext(x); 1833 getITBPtr(tc)->flushAsid(asid, secure_lookup, target_el); 1834 getDTBPtr(tc)->flushAsid(asid, secure_lookup, target_el); 1835 CheckerCPU *checker = tc->getCheckerCpuPtr(); 1836 if (checker) { 1837 getITBPtr(checker)->flushAsid(asid, secure_lookup, target_el); 1838 getDTBPtr(checker)->flushAsid(asid, secure_lookup, target_el); 1839 } 1840 } 1841} 1842 |
1843BaseISADevice & 1844ISA::getGenericTimer(ThreadContext *tc) 1845{ 1846 // We only need to create an ISA interface the first time we try 1847 // to access the timer. 1848 if (timer) 1849 return *timer.get(); 1850 --- 18 unchanged lines hidden --- |