1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1462 unchanged lines hidden (view full) --- 1471 } else { 1472 newVal = (paddr & 0xfffff000) | 1473 (getDTBPtr(tc)->getAttr()); 1474 } 1475 DPRINTF(MiscRegs, 1476 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1477 val, newVal); 1478 } else { |
1479 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); |
1480 // Set fault bit and FSR 1481 FSR fsr = armFault->getFsr(tc); 1482 1483 newVal = ((fsr >> 9) & 1) << 11; 1484 if (newVal) { 1485 // LPAE - rearange fault status 1486 newVal |= ((fsr >> 0) & 0x3f) << 1; 1487 } else { --- 232 unchanged lines hidden (view full) --- 1720 attr |= 0x100; 1721 attr &= ~ uint64_t(0x80); 1722 } 1723 newVal = (paddr & mask(47, 12)) | attr; 1724 DPRINTF(MiscRegs, 1725 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1726 val, newVal); 1727 } else { |
1728 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); |
1729 // Set fault bit and FSR 1730 FSR fsr = armFault->getFsr(tc); 1731 1732 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1733 if (cpsr.width) { // AArch32 1734 newVal = ((fsr >> 9) & 1) << 11; 1735 // rearrange fault status 1736 newVal |= ((fsr >> 0) & 0x3f) << 1; --- 152 unchanged lines hidden --- |