1701c1701
< tranType = TLB::S1CTran;
---
> tranType = TLB::S1E1Tran;
1706c1706
< tranType = TLB::S1CTran;
---
> tranType = TLB::S1E1Tran;
1711c1711
< tranType = TLB::S1CTran;
---
> tranType = TLB::S1E0Tran;
1716c1716
< tranType = TLB::S1CTran;
---
> tranType = TLB::S1E0Tran;
1721c1721
< tranType = TLB::HypMode;
---
> tranType = TLB::S1E2Tran;
1726c1726
< tranType = TLB::HypMode;
---
> tranType = TLB::S1E2Tran;
1731c1731
< tranType = TLB::S1S2NsTran;
---
> tranType = TLB::S12E0Tran;
1736c1736
< tranType = TLB::S1S2NsTran;
---
> tranType = TLB::S12E0Tran;
1741c1741
< tranType = TLB::S1S2NsTran;
---
> tranType = TLB::S12E1Tran;
1746c1746
< tranType = TLB::S1S2NsTran;
---
> tranType = TLB::S12E1Tran;
1751c1751
< tranType = TLB::HypMode; // There is no TZ mode defined.
---
> tranType = TLB::S1E3Tran;
1756c1756
< tranType = TLB::HypMode; // There is no TZ mode defined.
---
> tranType = TLB::S1E3Tran;
1791,1796c1791,1806
< newVal = ((fsr >> 9) & 1) << 11;
< // rearange fault status
< newVal |= ((fsr >> 0) & 0x3f) << 1;
< newVal |= 0x1; // F bit
< newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
< newVal |= armFault->isStage2() ? 0x200 : 0;
---
> CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
> if (cpsr.width) { // AArch32
> newVal = ((fsr >> 9) & 1) << 11;
> // rearrange fault status
> newVal |= ((fsr >> 0) & 0x3f) << 1;
> newVal |= 0x1; // F bit
> newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
> newVal |= armFault->isStage2() ? 0x200 : 0;
> } else { // AArch64
> newVal = 1; // F bit
> newVal |= fsr << 1; // FST
> // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
> newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
> newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
> newVal |= 1 << 11; // RES1
> }