55c55
<
---
> uint32_t midr = miscRegs[MISCREG_MIDR];
73a74,76
> // Preserve MIDR accross reset
> miscRegs[MISCREG_MIDR] = midr;
>
77,88d79
< /*
< * Implemented = '5' from "M5",
< * Variant = 0,
< */
< miscRegs[MISCREG_MIDR] =
< (0x35 << 24) | // Implementor is '5' from "M5"
< (0 << 20) | // Variant
< (0xf << 16) | // Architecture from CPUID scheme
< (0xf00 << 4) | // Primary part number
< (0 << 0) | // Revision
< 0;
<
211a203,205
> case MISCREG_ID_PFR1:
> warn("reading unimplmented register ID_PFR1");
> return 0;
222c216
< warn("Not doing anyhting for read to miscreg %s\n",
---
> warn("Not doing anything for read to miscreg %s\n",