50a51,52
> #include "dev/arm/gic_v3.hh"
> #include "dev/arm/gic_v3_cpu_interface.hh"
96a99,105
> // GICv3 CPU interface system registers are supported
> haveGICv3CPUInterface = false;
>
> if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
> haveGICv3CPUInterface = true;
> }
>
374a384,390
> if (system) {
> Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
> if (gicv3) {
> gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
> gicv3CpuInterface->setISA(this);
> }
> }
675,678c691,695
< return 0x0000000000000002 // AArch{64,32} supported at EL0
< | 0x0000000000000020 // EL1
< | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
< | (haveSecurity ? 0x0000000000002000 : 0); // EL3
---
> return 0x0000000000000002 | // AArch{64,32} supported at EL0
> 0x0000000000000020 | // EL1
> (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
> (haveSecurity ? 0x0000000000002000 : 0) | // EL3
> (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
691a709,712
> case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
> case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
> return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
>
1967a1989,1993
>
> case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
> case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
> getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
> return;
1993a2020,2024
> BaseISADevice &
> ISA::getGICv3CPUInterface(ThreadContext *tc)
> {
> panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
> return *gicv3CpuInterface.get();
1995a2027,2028
> }
>