1147a1148,1160
> case MISCREG_TLBIIPAS2L:
> case MISCREG_TLBIIPAS2LIS:
> // mcr tlbiipas2l(is) is invalidating all matching entries
> // regardless of the level of lookup, since in gem5 we cache
> // in the tlb the last level of lookup only.
> case MISCREG_TLBIIPAS2:
> case MISCREG_TLBIIPAS2IS:
> assert32(tc);
> target_el = 1; // EL 0 and 1 are handled together
> scr = readMiscReg(MISCREG_SCR, tc);
> secure_lookup = haveSecurity && !scr.ns;
> tlbiIPA(tc, newVal, secure_lookup, target_el);
> return;
1333,1349c1346
< sys = tc->getSystemPtr();
< for (x = 0; x < sys->numContexts(); x++) {
< oc = sys->getThreadContext(x);
< Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
< getITBPtr(oc)->flushIpaVmid(ipa,
< secure_lookup, false, target_el);
< getDTBPtr(oc)->flushIpaVmid(ipa,
< secure_lookup, false, target_el);
<
< CheckerCPU *checker = oc->getCheckerCpuPtr();
< if (checker) {
< getITBPtr(checker)->flushIpaVmid(ipa,
< secure_lookup, false, target_el);
< getDTBPtr(checker)->flushIpaVmid(ipa,
< secure_lookup, false, target_el);
< }
< }
---
> tlbiIPA(tc, newVal, secure_lookup, target_el);
1879a1877,1899
> void
> ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
> uint8_t target_el)
> {
> System *sys = tc->getSystemPtr();
> for (auto x = 0; x < sys->numContexts(); x++) {
> tc = sys->getThreadContext(x);
> Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
> getITBPtr(tc)->flushIpaVmid(ipa,
> secure_lookup, false, target_el);
> getDTBPtr(tc)->flushIpaVmid(ipa,
> secure_lookup, false, target_el);
>
> CheckerCPU *checker = tc->getCheckerCpuPtr();
> if (checker) {
> getITBPtr(checker)->flushIpaVmid(ipa,
> secure_lookup, false, target_el);
> getDTBPtr(checker)->flushIpaVmid(ipa,
> secure_lookup, false, target_el);
> }
> }
> }
>