1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
|
42#include "config/use_checker.hh"
| 42#include "cpu/checker/cpu.hh"
|
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
| 43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
|
49#if USE_CHECKER
50#include "cpu/checker/cpu.hh"
51#endif
52
| |
53namespace ArmISA
54{
55
56void
57ISA::clear()
58{
59 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
60 uint32_t midr = miscRegs[MISCREG_MIDR];
61 memset(miscRegs, 0, sizeof(miscRegs));
62 CPSR cpsr = 0;
63 cpsr.mode = MODE_USER;
64 miscRegs[MISCREG_CPSR] = cpsr;
65 updateRegMap(cpsr);
66
67 SCTLR sctlr = 0;
68 sctlr.te = (bool)sctlr_rst.te;
69 sctlr.nmfi = (bool)sctlr_rst.nmfi;
70 sctlr.v = (bool)sctlr_rst.v;
71 sctlr.u = 1;
72 sctlr.xp = 1;
73 sctlr.rao2 = 1;
74 sctlr.rao3 = 1;
75 sctlr.rao4 = 1;
76 miscRegs[MISCREG_SCTLR] = sctlr;
77 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
78
79 // Preserve MIDR accross reset
80 miscRegs[MISCREG_MIDR] = midr;
81
82 /* Start with an event in the mailbox */
83 miscRegs[MISCREG_SEV_MAILBOX] = 1;
84
85 // Separate Instruction and Data TLBs.
86 miscRegs[MISCREG_TLBTR] = 1;
87
88 MVFR0 mvfr0 = 0;
89 mvfr0.advSimdRegisters = 2;
90 mvfr0.singlePrecision = 2;
91 mvfr0.doublePrecision = 2;
92 mvfr0.vfpExceptionTrapping = 0;
93 mvfr0.divide = 1;
94 mvfr0.squareRoot = 1;
95 mvfr0.shortVectors = 1;
96 mvfr0.roundingModes = 1;
97 miscRegs[MISCREG_MVFR0] = mvfr0;
98
99 MVFR1 mvfr1 = 0;
100 mvfr1.flushToZero = 1;
101 mvfr1.defaultNaN = 1;
102 mvfr1.advSimdLoadStore = 1;
103 mvfr1.advSimdInteger = 1;
104 mvfr1.advSimdSinglePrecision = 1;
105 mvfr1.advSimdHalfPrecision = 1;
106 mvfr1.vfpHalfPrecision = 1;
107 miscRegs[MISCREG_MVFR1] = mvfr1;
108
109 miscRegs[MISCREG_MPIDR] = 0;
110
111 // Reset values of PRRR and NMRR are implementation dependent
112
113 miscRegs[MISCREG_PRRR] =
114 (1 << 19) | // 19
115 (0 << 18) | // 18
116 (0 << 17) | // 17
117 (1 << 16) | // 16
118 (2 << 14) | // 15:14
119 (0 << 12) | // 13:12
120 (2 << 10) | // 11:10
121 (2 << 8) | // 9:8
122 (2 << 6) | // 7:6
123 (2 << 4) | // 5:4
124 (1 << 2) | // 3:2
125 0; // 1:0
126 miscRegs[MISCREG_NMRR] =
127 (1 << 30) | // 31:30
128 (0 << 26) | // 27:26
129 (0 << 24) | // 25:24
130 (3 << 22) | // 23:22
131 (2 << 20) | // 21:20
132 (0 << 18) | // 19:18
133 (0 << 16) | // 17:16
134 (1 << 14) | // 15:14
135 (0 << 12) | // 13:12
136 (2 << 10) | // 11:10
137 (0 << 8) | // 9:8
138 (3 << 6) | // 7:6
139 (2 << 4) | // 5:4
140 (0 << 2) | // 3:2
141 0; // 1:0
142
143 miscRegs[MISCREG_CPACR] = 0;
144 miscRegs[MISCREG_FPSID] = 0x410430A0;
145
146 // See section B4.1.84 of ARM ARM
147 // All values are latest for ARMv7-A profile
148 miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
149 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
150 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
151 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
152 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
153 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
154
155 //XXX We need to initialize the rest of the state.
156}
157
158MiscReg
159ISA::readMiscRegNoEffect(int misc_reg)
160{
161 assert(misc_reg < NumMiscRegs);
162
163 int flat_idx;
164 if (misc_reg == MISCREG_SPSR)
165 flat_idx = flattenMiscIndex(misc_reg);
166 else
167 flat_idx = misc_reg;
168 MiscReg val = miscRegs[flat_idx];
169
170 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
171 misc_reg, flat_idx, val);
172 return val;
173}
174
175
176MiscReg
177ISA::readMiscReg(int misc_reg, ThreadContext *tc)
178{
179 if (misc_reg == MISCREG_CPSR) {
180 CPSR cpsr = miscRegs[misc_reg];
181 PCState pc = tc->pcState();
182 cpsr.j = pc.jazelle() ? 1 : 0;
183 cpsr.t = pc.thumb() ? 1 : 0;
184 return cpsr;
185 }
186 if (misc_reg >= MISCREG_CP15_UNIMP_START)
187 panic("Unimplemented CP15 register %s read.\n",
188 miscRegName[misc_reg]);
189
190 switch (misc_reg) {
191 case MISCREG_MPIDR:
192
193 return 0x80000000 | // multiprocessor extensions available
194 tc->cpuId();
195 break;
196 case MISCREG_ID_MMFR0:
197 return 0x03; // VMSAv7 support
198 case MISCREG_ID_MMFR2:
199 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
200 // | all TLB maintenance | no Harvard
201 case MISCREG_ID_MMFR3:
202 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
203 // BP Maint | Cache Maint Set/way | Cache Maint MVA
204 case MISCREG_CLIDR:
205 warn_once("The clidr register always reports 0 caches.\n");
206 warn_once("clidr LoUIS field of 0b001 to match current "
207 "ARM implementations.\n");
208 return 0x00200000;
209 case MISCREG_CCSIDR:
210 warn_once("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
214 warn("Returning thumbEE disabled for now since we don't support CP14"
215 "config registers and jumping to ThumbEE vectors\n");
216 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
217 case MISCREG_ID_PFR1:
218 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
219 case MISCREG_CTR:
220 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
221 case MISCREG_ACTLR:
222 warn("Not doing anything for miscreg ACTLR\n");
223 break;
224 case MISCREG_PMCR:
225 case MISCREG_PMCCNTR:
226 case MISCREG_PMSELR:
227 warn("Not doing anything for read to miscreg %s\n",
228 miscRegName[misc_reg]);
229 break;
230 case MISCREG_CPSR_Q:
231 panic("shouldn't be reading this register seperately\n");
232 case MISCREG_FPSCR_QC:
233 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
234 case MISCREG_FPSCR_EXC:
235 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
236 case MISCREG_L2CTLR:
237 {
238 // mostly unimplemented, just set NumCPUs field from sim and return
239 L2CTLR l2ctlr = 0;
240 // b00:1CPU to b11:4CPUs
241 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
242 return l2ctlr;
243 }
244 case MISCREG_DBGDIDR:
245 /* For now just implement the version number.
246 * Return 0 as we don't support debug architecture yet.
247 */
248 return 0;
249 case MISCREG_DBGDSCR_INT:
250 return 0;
251 }
252 return readMiscRegNoEffect(misc_reg);
253}
254
255void
256ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
257{
258 assert(misc_reg < NumMiscRegs);
259
260 int flat_idx;
261 if (misc_reg == MISCREG_SPSR)
262 flat_idx = flattenMiscIndex(misc_reg);
263 else
264 flat_idx = misc_reg;
265 miscRegs[flat_idx] = val;
266
267 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
268 flat_idx, val);
269}
270
271void
272ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
273{
274
275 MiscReg newVal = val;
276 int x;
277 System *sys;
278 ThreadContext *oc;
279
280 if (misc_reg == MISCREG_CPSR) {
281 updateRegMap(val);
282
283
284 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
285 int old_mode = old_cpsr.mode;
286 CPSR cpsr = val;
287 if (old_mode != cpsr.mode) {
288 tc->getITBPtr()->invalidateMiscReg();
289 tc->getDTBPtr()->invalidateMiscReg();
290 }
291
292 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
293 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
294 PCState pc = tc->pcState();
295 pc.nextThumb(cpsr.t);
296 pc.nextJazelle(cpsr.j);
| 49namespace ArmISA
50{
51
52void
53ISA::clear()
54{
55 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
56 uint32_t midr = miscRegs[MISCREG_MIDR];
57 memset(miscRegs, 0, sizeof(miscRegs));
58 CPSR cpsr = 0;
59 cpsr.mode = MODE_USER;
60 miscRegs[MISCREG_CPSR] = cpsr;
61 updateRegMap(cpsr);
62
63 SCTLR sctlr = 0;
64 sctlr.te = (bool)sctlr_rst.te;
65 sctlr.nmfi = (bool)sctlr_rst.nmfi;
66 sctlr.v = (bool)sctlr_rst.v;
67 sctlr.u = 1;
68 sctlr.xp = 1;
69 sctlr.rao2 = 1;
70 sctlr.rao3 = 1;
71 sctlr.rao4 = 1;
72 miscRegs[MISCREG_SCTLR] = sctlr;
73 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
74
75 // Preserve MIDR accross reset
76 miscRegs[MISCREG_MIDR] = midr;
77
78 /* Start with an event in the mailbox */
79 miscRegs[MISCREG_SEV_MAILBOX] = 1;
80
81 // Separate Instruction and Data TLBs.
82 miscRegs[MISCREG_TLBTR] = 1;
83
84 MVFR0 mvfr0 = 0;
85 mvfr0.advSimdRegisters = 2;
86 mvfr0.singlePrecision = 2;
87 mvfr0.doublePrecision = 2;
88 mvfr0.vfpExceptionTrapping = 0;
89 mvfr0.divide = 1;
90 mvfr0.squareRoot = 1;
91 mvfr0.shortVectors = 1;
92 mvfr0.roundingModes = 1;
93 miscRegs[MISCREG_MVFR0] = mvfr0;
94
95 MVFR1 mvfr1 = 0;
96 mvfr1.flushToZero = 1;
97 mvfr1.defaultNaN = 1;
98 mvfr1.advSimdLoadStore = 1;
99 mvfr1.advSimdInteger = 1;
100 mvfr1.advSimdSinglePrecision = 1;
101 mvfr1.advSimdHalfPrecision = 1;
102 mvfr1.vfpHalfPrecision = 1;
103 miscRegs[MISCREG_MVFR1] = mvfr1;
104
105 miscRegs[MISCREG_MPIDR] = 0;
106
107 // Reset values of PRRR and NMRR are implementation dependent
108
109 miscRegs[MISCREG_PRRR] =
110 (1 << 19) | // 19
111 (0 << 18) | // 18
112 (0 << 17) | // 17
113 (1 << 16) | // 16
114 (2 << 14) | // 15:14
115 (0 << 12) | // 13:12
116 (2 << 10) | // 11:10
117 (2 << 8) | // 9:8
118 (2 << 6) | // 7:6
119 (2 << 4) | // 5:4
120 (1 << 2) | // 3:2
121 0; // 1:0
122 miscRegs[MISCREG_NMRR] =
123 (1 << 30) | // 31:30
124 (0 << 26) | // 27:26
125 (0 << 24) | // 25:24
126 (3 << 22) | // 23:22
127 (2 << 20) | // 21:20
128 (0 << 18) | // 19:18
129 (0 << 16) | // 17:16
130 (1 << 14) | // 15:14
131 (0 << 12) | // 13:12
132 (2 << 10) | // 11:10
133 (0 << 8) | // 9:8
134 (3 << 6) | // 7:6
135 (2 << 4) | // 5:4
136 (0 << 2) | // 3:2
137 0; // 1:0
138
139 miscRegs[MISCREG_CPACR] = 0;
140 miscRegs[MISCREG_FPSID] = 0x410430A0;
141
142 // See section B4.1.84 of ARM ARM
143 // All values are latest for ARMv7-A profile
144 miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
145 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
146 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
147 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
148 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
149 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
150
151 //XXX We need to initialize the rest of the state.
152}
153
154MiscReg
155ISA::readMiscRegNoEffect(int misc_reg)
156{
157 assert(misc_reg < NumMiscRegs);
158
159 int flat_idx;
160 if (misc_reg == MISCREG_SPSR)
161 flat_idx = flattenMiscIndex(misc_reg);
162 else
163 flat_idx = misc_reg;
164 MiscReg val = miscRegs[flat_idx];
165
166 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
167 misc_reg, flat_idx, val);
168 return val;
169}
170
171
172MiscReg
173ISA::readMiscReg(int misc_reg, ThreadContext *tc)
174{
175 if (misc_reg == MISCREG_CPSR) {
176 CPSR cpsr = miscRegs[misc_reg];
177 PCState pc = tc->pcState();
178 cpsr.j = pc.jazelle() ? 1 : 0;
179 cpsr.t = pc.thumb() ? 1 : 0;
180 return cpsr;
181 }
182 if (misc_reg >= MISCREG_CP15_UNIMP_START)
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
185
186 switch (misc_reg) {
187 case MISCREG_MPIDR:
188
189 return 0x80000000 | // multiprocessor extensions available
190 tc->cpuId();
191 break;
192 case MISCREG_ID_MMFR0:
193 return 0x03; // VMSAv7 support
194 case MISCREG_ID_MMFR2:
195 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
196 // | all TLB maintenance | no Harvard
197 case MISCREG_ID_MMFR3:
198 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
199 // BP Maint | Cache Maint Set/way | Cache Maint MVA
200 case MISCREG_CLIDR:
201 warn_once("The clidr register always reports 0 caches.\n");
202 warn_once("clidr LoUIS field of 0b001 to match current "
203 "ARM implementations.\n");
204 return 0x00200000;
205 case MISCREG_CCSIDR:
206 warn_once("The ccsidr register isn't implemented and "
207 "always reads as 0.\n");
208 break;
209 case MISCREG_ID_PFR0:
210 warn("Returning thumbEE disabled for now since we don't support CP14"
211 "config registers and jumping to ThumbEE vectors\n");
212 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
213 case MISCREG_ID_PFR1:
214 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
215 case MISCREG_CTR:
216 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
217 case MISCREG_ACTLR:
218 warn("Not doing anything for miscreg ACTLR\n");
219 break;
220 case MISCREG_PMCR:
221 case MISCREG_PMCCNTR:
222 case MISCREG_PMSELR:
223 warn("Not doing anything for read to miscreg %s\n",
224 miscRegName[misc_reg]);
225 break;
226 case MISCREG_CPSR_Q:
227 panic("shouldn't be reading this register seperately\n");
228 case MISCREG_FPSCR_QC:
229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
230 case MISCREG_FPSCR_EXC:
231 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
232 case MISCREG_L2CTLR:
233 {
234 // mostly unimplemented, just set NumCPUs field from sim and return
235 L2CTLR l2ctlr = 0;
236 // b00:1CPU to b11:4CPUs
237 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
238 return l2ctlr;
239 }
240 case MISCREG_DBGDIDR:
241 /* For now just implement the version number.
242 * Return 0 as we don't support debug architecture yet.
243 */
244 return 0;
245 case MISCREG_DBGDSCR_INT:
246 return 0;
247 }
248 return readMiscRegNoEffect(misc_reg);
249}
250
251void
252ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
253{
254 assert(misc_reg < NumMiscRegs);
255
256 int flat_idx;
257 if (misc_reg == MISCREG_SPSR)
258 flat_idx = flattenMiscIndex(misc_reg);
259 else
260 flat_idx = misc_reg;
261 miscRegs[flat_idx] = val;
262
263 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
264 flat_idx, val);
265}
266
267void
268ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
269{
270
271 MiscReg newVal = val;
272 int x;
273 System *sys;
274 ThreadContext *oc;
275
276 if (misc_reg == MISCREG_CPSR) {
277 updateRegMap(val);
278
279
280 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
281 int old_mode = old_cpsr.mode;
282 CPSR cpsr = val;
283 if (old_mode != cpsr.mode) {
284 tc->getITBPtr()->invalidateMiscReg();
285 tc->getDTBPtr()->invalidateMiscReg();
286 }
287
288 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
289 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
290 PCState pc = tc->pcState();
291 pc.nextThumb(cpsr.t);
292 pc.nextJazelle(cpsr.j);
|
297#if USE_CHECKER
298 tc->pcStateNoRecord(pc);
299#else
300 tc->pcState(pc);
301#endif //USE_CHECKER
| 293
294 // Follow slightly different semantics if a CheckerCPU object
295 // is connected
296 CheckerCPU *checker = tc->getCheckerCpuPtr();
297 if (checker) {
298 tc->pcStateNoRecord(pc);
299 } else {
300 tc->pcState(pc);
301 }
|
302 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
303 misc_reg < MISCREG_CP15_END) {
304 panic("Unimplemented CP15 register %s wrote with %#x.\n",
305 miscRegName[misc_reg], val);
306 } else {
307 switch (misc_reg) {
308 case MISCREG_CPACR:
309 {
310
311 const uint32_t ones = (uint32_t)(-1);
312 CPACR cpacrMask = 0;
313 // Only cp10, cp11, and ase are implemented, nothing else should
314 // be writable
315 cpacrMask.cp10 = ones;
316 cpacrMask.cp11 = ones;
317 cpacrMask.asedis = ones;
318 newVal &= cpacrMask;
319 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
320 miscRegName[misc_reg], newVal);
321 }
322 break;
323 case MISCREG_CSSELR:
324 warn_once("The csselr register isn't implemented.\n");
325 return;
326 case MISCREG_FPSCR:
327 {
328 const uint32_t ones = (uint32_t)(-1);
329 FPSCR fpscrMask = 0;
330 fpscrMask.ioc = ones;
331 fpscrMask.dzc = ones;
332 fpscrMask.ofc = ones;
333 fpscrMask.ufc = ones;
334 fpscrMask.ixc = ones;
335 fpscrMask.idc = ones;
336 fpscrMask.len = ones;
337 fpscrMask.stride = ones;
338 fpscrMask.rMode = ones;
339 fpscrMask.fz = ones;
340 fpscrMask.dn = ones;
341 fpscrMask.ahp = ones;
342 fpscrMask.qc = ones;
343 fpscrMask.v = ones;
344 fpscrMask.c = ones;
345 fpscrMask.z = ones;
346 fpscrMask.n = ones;
347 newVal = (newVal & (uint32_t)fpscrMask) |
348 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
349 }
350 break;
351 case MISCREG_CPSR_Q:
352 {
353 assert(!(newVal & ~CpsrMaskQ));
354 newVal = miscRegs[MISCREG_CPSR] | newVal;
355 misc_reg = MISCREG_CPSR;
356 }
357 break;
358 case MISCREG_FPSCR_QC:
359 {
360 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
361 misc_reg = MISCREG_FPSCR;
362 }
363 break;
364 case MISCREG_FPSCR_EXC:
365 {
366 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
367 misc_reg = MISCREG_FPSCR;
368 }
369 break;
370 case MISCREG_FPEXC:
371 {
372 // vfpv3 architecture, section B.6.1 of DDI04068
373 // bit 29 - valid only if fpexc[31] is 0
374 const uint32_t fpexcMask = 0x60000000;
375 newVal = (newVal & fpexcMask) |
376 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
377 }
378 break;
379 case MISCREG_SCTLR:
380 {
381 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
382 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
383 SCTLR new_sctlr = newVal;
384 new_sctlr.nmfi = (bool)sctlr.nmfi;
385 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
386 tc->getITBPtr()->invalidateMiscReg();
387 tc->getDTBPtr()->invalidateMiscReg();
388
389 // Check if all CPUs are booted with caches enabled
390 // so we can stop enforcing coherency of some kernel
391 // structures manually.
392 sys = tc->getSystemPtr();
393 for (x = 0; x < sys->numContexts(); x++) {
394 oc = sys->getThreadContext(x);
395 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
396 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
397 return;
398 }
399
400 for (x = 0; x < sys->numContexts(); x++) {
401 oc = sys->getThreadContext(x);
402 oc->getDTBPtr()->allCpusCaching();
403 oc->getITBPtr()->allCpusCaching();
| 302 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
303 misc_reg < MISCREG_CP15_END) {
304 panic("Unimplemented CP15 register %s wrote with %#x.\n",
305 miscRegName[misc_reg], val);
306 } else {
307 switch (misc_reg) {
308 case MISCREG_CPACR:
309 {
310
311 const uint32_t ones = (uint32_t)(-1);
312 CPACR cpacrMask = 0;
313 // Only cp10, cp11, and ase are implemented, nothing else should
314 // be writable
315 cpacrMask.cp10 = ones;
316 cpacrMask.cp11 = ones;
317 cpacrMask.asedis = ones;
318 newVal &= cpacrMask;
319 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
320 miscRegName[misc_reg], newVal);
321 }
322 break;
323 case MISCREG_CSSELR:
324 warn_once("The csselr register isn't implemented.\n");
325 return;
326 case MISCREG_FPSCR:
327 {
328 const uint32_t ones = (uint32_t)(-1);
329 FPSCR fpscrMask = 0;
330 fpscrMask.ioc = ones;
331 fpscrMask.dzc = ones;
332 fpscrMask.ofc = ones;
333 fpscrMask.ufc = ones;
334 fpscrMask.ixc = ones;
335 fpscrMask.idc = ones;
336 fpscrMask.len = ones;
337 fpscrMask.stride = ones;
338 fpscrMask.rMode = ones;
339 fpscrMask.fz = ones;
340 fpscrMask.dn = ones;
341 fpscrMask.ahp = ones;
342 fpscrMask.qc = ones;
343 fpscrMask.v = ones;
344 fpscrMask.c = ones;
345 fpscrMask.z = ones;
346 fpscrMask.n = ones;
347 newVal = (newVal & (uint32_t)fpscrMask) |
348 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
349 }
350 break;
351 case MISCREG_CPSR_Q:
352 {
353 assert(!(newVal & ~CpsrMaskQ));
354 newVal = miscRegs[MISCREG_CPSR] | newVal;
355 misc_reg = MISCREG_CPSR;
356 }
357 break;
358 case MISCREG_FPSCR_QC:
359 {
360 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
361 misc_reg = MISCREG_FPSCR;
362 }
363 break;
364 case MISCREG_FPSCR_EXC:
365 {
366 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
367 misc_reg = MISCREG_FPSCR;
368 }
369 break;
370 case MISCREG_FPEXC:
371 {
372 // vfpv3 architecture, section B.6.1 of DDI04068
373 // bit 29 - valid only if fpexc[31] is 0
374 const uint32_t fpexcMask = 0x60000000;
375 newVal = (newVal & fpexcMask) |
376 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
377 }
378 break;
379 case MISCREG_SCTLR:
380 {
381 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
382 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
383 SCTLR new_sctlr = newVal;
384 new_sctlr.nmfi = (bool)sctlr.nmfi;
385 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
386 tc->getITBPtr()->invalidateMiscReg();
387 tc->getDTBPtr()->invalidateMiscReg();
388
389 // Check if all CPUs are booted with caches enabled
390 // so we can stop enforcing coherency of some kernel
391 // structures manually.
392 sys = tc->getSystemPtr();
393 for (x = 0; x < sys->numContexts(); x++) {
394 oc = sys->getThreadContext(x);
395 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
396 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
397 return;
398 }
399
400 for (x = 0; x < sys->numContexts(); x++) {
401 oc = sys->getThreadContext(x);
402 oc->getDTBPtr()->allCpusCaching();
403 oc->getITBPtr()->allCpusCaching();
|
404#if USE_CHECKER
405 CheckerCPU *checker =
406 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
| 404
405 // If CheckerCPU is connected, need to notify it.
406 CheckerCPU *checker = oc->getCheckerCpuPtr();
|
407 if (checker) {
408 checker->getDTBPtr()->allCpusCaching();
409 checker->getITBPtr()->allCpusCaching();
410 }
| 407 if (checker) {
408 checker->getDTBPtr()->allCpusCaching();
409 checker->getITBPtr()->allCpusCaching();
410 }
|
411#endif
| |
412 }
413 return;
414 }
415 case MISCREG_TLBTR:
416 case MISCREG_MVFR0:
417 case MISCREG_MVFR1:
418 case MISCREG_MPIDR:
419 case MISCREG_FPSID:
420 return;
421 case MISCREG_TLBIALLIS:
422 case MISCREG_TLBIALL:
423 sys = tc->getSystemPtr();
424 for (x = 0; x < sys->numContexts(); x++) {
425 oc = sys->getThreadContext(x);
426 assert(oc->getITBPtr() && oc->getDTBPtr());
427 oc->getITBPtr()->flushAll();
428 oc->getDTBPtr()->flushAll();
| 411 }
412 return;
413 }
414 case MISCREG_TLBTR:
415 case MISCREG_MVFR0:
416 case MISCREG_MVFR1:
417 case MISCREG_MPIDR:
418 case MISCREG_FPSID:
419 return;
420 case MISCREG_TLBIALLIS:
421 case MISCREG_TLBIALL:
422 sys = tc->getSystemPtr();
423 for (x = 0; x < sys->numContexts(); x++) {
424 oc = sys->getThreadContext(x);
425 assert(oc->getITBPtr() && oc->getDTBPtr());
426 oc->getITBPtr()->flushAll();
427 oc->getDTBPtr()->flushAll();
|
429#if USE_CHECKER
430 CheckerCPU *checker =
431 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
| 428
429 // If CheckerCPU is connected, need to notify it of a flush
430 CheckerCPU *checker = oc->getCheckerCpuPtr();
|
432 if (checker) {
433 checker->getITBPtr()->flushAll();
434 checker->getDTBPtr()->flushAll();
435 }
| 431 if (checker) {
432 checker->getITBPtr()->flushAll();
433 checker->getDTBPtr()->flushAll();
434 }
|
436#endif
| |
437 }
438 return;
439 case MISCREG_ITLBIALL:
440 tc->getITBPtr()->flushAll();
441 return;
442 case MISCREG_DTLBIALL:
443 tc->getDTBPtr()->flushAll();
444 return;
445 case MISCREG_TLBIMVAIS:
446 case MISCREG_TLBIMVA:
447 sys = tc->getSystemPtr();
448 for (x = 0; x < sys->numContexts(); x++) {
449 oc = sys->getThreadContext(x);
450 assert(oc->getITBPtr() && oc->getDTBPtr());
451 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452 bits(newVal, 7,0));
453 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
454 bits(newVal, 7,0));
| 435 }
436 return;
437 case MISCREG_ITLBIALL:
438 tc->getITBPtr()->flushAll();
439 return;
440 case MISCREG_DTLBIALL:
441 tc->getDTBPtr()->flushAll();
442 return;
443 case MISCREG_TLBIMVAIS:
444 case MISCREG_TLBIMVA:
445 sys = tc->getSystemPtr();
446 for (x = 0; x < sys->numContexts(); x++) {
447 oc = sys->getThreadContext(x);
448 assert(oc->getITBPtr() && oc->getDTBPtr());
449 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
450 bits(newVal, 7,0));
451 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452 bits(newVal, 7,0));
|
455#if USE_CHECKER
456 CheckerCPU *checker =
457 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
| 453
454 CheckerCPU *checker = oc->getCheckerCpuPtr();
|
458 if (checker) {
459 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
460 bits(newVal, 7,0));
461 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
462 bits(newVal, 7,0));
463 }
| 455 if (checker) {
456 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
457 bits(newVal, 7,0));
458 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
459 bits(newVal, 7,0));
460 }
|
464#endif
| |
465 }
466 return;
467 case MISCREG_TLBIASIDIS:
468 case MISCREG_TLBIASID:
469 sys = tc->getSystemPtr();
470 for (x = 0; x < sys->numContexts(); x++) {
471 oc = sys->getThreadContext(x);
472 assert(oc->getITBPtr() && oc->getDTBPtr());
473 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
474 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
| 461 }
462 return;
463 case MISCREG_TLBIASIDIS:
464 case MISCREG_TLBIASID:
465 sys = tc->getSystemPtr();
466 for (x = 0; x < sys->numContexts(); x++) {
467 oc = sys->getThreadContext(x);
468 assert(oc->getITBPtr() && oc->getDTBPtr());
469 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
470 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
475#if USE_CHECKER
476 CheckerCPU *checker =
477 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
| 471 CheckerCPU *checker = oc->getCheckerCpuPtr();
|
478 if (checker) {
479 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
480 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
481 }
| 472 if (checker) {
473 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
474 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
475 }
|
482#endif
| |
483 }
484 return;
485 case MISCREG_TLBIMVAAIS:
486 case MISCREG_TLBIMVAA:
487 sys = tc->getSystemPtr();
488 for (x = 0; x < sys->numContexts(); x++) {
489 oc = sys->getThreadContext(x);
490 assert(oc->getITBPtr() && oc->getDTBPtr());
491 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
492 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
| 476 }
477 return;
478 case MISCREG_TLBIMVAAIS:
479 case MISCREG_TLBIMVAA:
480 sys = tc->getSystemPtr();
481 for (x = 0; x < sys->numContexts(); x++) {
482 oc = sys->getThreadContext(x);
483 assert(oc->getITBPtr() && oc->getDTBPtr());
484 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
485 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
|
493#if USE_CHECKER
494 CheckerCPU *checker =
495 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
| 486
487 CheckerCPU *checker = oc->getCheckerCpuPtr();
|
496 if (checker) {
497 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
498 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
499 }
| 488 if (checker) {
489 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
490 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
491 }
|
500#endif
| |
501 }
502 return;
503 case MISCREG_ITLBIMVA:
504 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
505 bits(newVal, 7,0));
506 return;
507 case MISCREG_DTLBIMVA:
508 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
509 bits(newVal, 7,0));
510 return;
511 case MISCREG_ITLBIASID:
512 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
513 return;
514 case MISCREG_DTLBIASID:
515 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
516 return;
517 case MISCREG_ACTLR:
518 warn("Not doing anything for write of miscreg ACTLR\n");
519 break;
520 case MISCREG_PMCR:
521 {
522 // Performance counters not implemented. Instead, interpret
523 // a reset command to this register to reset the simulator
524 // statistics.
525 // PMCR_E | PMCR_P | PMCR_C
526 const int ResetAndEnableCounters = 0x7;
527 if (newVal == ResetAndEnableCounters) {
528 inform("Resetting all simobject stats\n");
529 Stats::schedStatEvent(false, true);
530 break;
531 }
532 }
533 case MISCREG_PMCCNTR:
534 case MISCREG_PMSELR:
535 warn("Not doing anything for write to miscreg %s\n",
536 miscRegName[misc_reg]);
537 break;
538 case MISCREG_V2PCWPR:
539 case MISCREG_V2PCWPW:
540 case MISCREG_V2PCWUR:
541 case MISCREG_V2PCWUW:
542 case MISCREG_V2POWPR:
543 case MISCREG_V2POWPW:
544 case MISCREG_V2POWUR:
545 case MISCREG_V2POWUW:
546 {
547 RequestPtr req = new Request;
548 unsigned flags;
549 BaseTLB::Mode mode;
550 Fault fault;
551 switch(misc_reg) {
552 case MISCREG_V2PCWPR:
553 flags = TLB::MustBeOne;
554 mode = BaseTLB::Read;
555 break;
556 case MISCREG_V2PCWPW:
557 flags = TLB::MustBeOne;
558 mode = BaseTLB::Write;
559 break;
560 case MISCREG_V2PCWUR:
561 flags = TLB::MustBeOne | TLB::UserMode;
562 mode = BaseTLB::Read;
563 break;
564 case MISCREG_V2PCWUW:
565 flags = TLB::MustBeOne | TLB::UserMode;
566 mode = BaseTLB::Write;
567 break;
568 default:
569 panic("Security Extensions not implemented!");
570 }
571 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
572 req->setVirt(0, val, 1, flags, tc->pcState().pc(),
573 Request::funcMasterId);
574 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
575 if (fault == NoFault) {
576 miscRegs[MISCREG_PAR] =
577 (req->getPaddr() & 0xfffff000) |
578 (tc->getDTBPtr()->getAttr() );
579 DPRINTF(MiscRegs,
580 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
581 val, miscRegs[MISCREG_PAR]);
582 }
583 else {
584 // Set fault bit and FSR
585 FSR fsr = miscRegs[MISCREG_DFSR];
586 miscRegs[MISCREG_PAR] =
587 (fsr.ext << 6) |
588 (fsr.fsHigh << 5) |
589 (fsr.fsLow << 1) |
590 0x1; // F bit
591 }
592 return;
593 }
594 case MISCREG_CONTEXTIDR:
595 case MISCREG_PRRR:
596 case MISCREG_NMRR:
597 case MISCREG_DACR:
598 tc->getITBPtr()->invalidateMiscReg();
599 tc->getDTBPtr()->invalidateMiscReg();
600 break;
601 case MISCREG_CPSR_MODE:
602 // This miscreg is used by copy*Regs to set the CPSR mode
603 // without updating other CPSR variables. It's used to
604 // make sure the register map is in such a state that we can
605 // see all of the registers for the copy.
606 updateRegMap(val);
607 return;
608 case MISCREG_L2CTLR:
609 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
610 miscRegName[misc_reg], uint32_t(val));
611 }
612 }
613 setMiscRegNoEffect(misc_reg, newVal);
614}
615
616}
| 492 }
493 return;
494 case MISCREG_ITLBIMVA:
495 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
496 bits(newVal, 7,0));
497 return;
498 case MISCREG_DTLBIMVA:
499 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
500 bits(newVal, 7,0));
501 return;
502 case MISCREG_ITLBIASID:
503 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
504 return;
505 case MISCREG_DTLBIASID:
506 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
507 return;
508 case MISCREG_ACTLR:
509 warn("Not doing anything for write of miscreg ACTLR\n");
510 break;
511 case MISCREG_PMCR:
512 {
513 // Performance counters not implemented. Instead, interpret
514 // a reset command to this register to reset the simulator
515 // statistics.
516 // PMCR_E | PMCR_P | PMCR_C
517 const int ResetAndEnableCounters = 0x7;
518 if (newVal == ResetAndEnableCounters) {
519 inform("Resetting all simobject stats\n");
520 Stats::schedStatEvent(false, true);
521 break;
522 }
523 }
524 case MISCREG_PMCCNTR:
525 case MISCREG_PMSELR:
526 warn("Not doing anything for write to miscreg %s\n",
527 miscRegName[misc_reg]);
528 break;
529 case MISCREG_V2PCWPR:
530 case MISCREG_V2PCWPW:
531 case MISCREG_V2PCWUR:
532 case MISCREG_V2PCWUW:
533 case MISCREG_V2POWPR:
534 case MISCREG_V2POWPW:
535 case MISCREG_V2POWUR:
536 case MISCREG_V2POWUW:
537 {
538 RequestPtr req = new Request;
539 unsigned flags;
540 BaseTLB::Mode mode;
541 Fault fault;
542 switch(misc_reg) {
543 case MISCREG_V2PCWPR:
544 flags = TLB::MustBeOne;
545 mode = BaseTLB::Read;
546 break;
547 case MISCREG_V2PCWPW:
548 flags = TLB::MustBeOne;
549 mode = BaseTLB::Write;
550 break;
551 case MISCREG_V2PCWUR:
552 flags = TLB::MustBeOne | TLB::UserMode;
553 mode = BaseTLB::Read;
554 break;
555 case MISCREG_V2PCWUW:
556 flags = TLB::MustBeOne | TLB::UserMode;
557 mode = BaseTLB::Write;
558 break;
559 default:
560 panic("Security Extensions not implemented!");
561 }
562 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
563 req->setVirt(0, val, 1, flags, tc->pcState().pc(),
564 Request::funcMasterId);
565 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
566 if (fault == NoFault) {
567 miscRegs[MISCREG_PAR] =
568 (req->getPaddr() & 0xfffff000) |
569 (tc->getDTBPtr()->getAttr() );
570 DPRINTF(MiscRegs,
571 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
572 val, miscRegs[MISCREG_PAR]);
573 }
574 else {
575 // Set fault bit and FSR
576 FSR fsr = miscRegs[MISCREG_DFSR];
577 miscRegs[MISCREG_PAR] =
578 (fsr.ext << 6) |
579 (fsr.fsHigh << 5) |
580 (fsr.fsLow << 1) |
581 0x1; // F bit
582 }
583 return;
584 }
585 case MISCREG_CONTEXTIDR:
586 case MISCREG_PRRR:
587 case MISCREG_NMRR:
588 case MISCREG_DACR:
589 tc->getITBPtr()->invalidateMiscReg();
590 tc->getDTBPtr()->invalidateMiscReg();
591 break;
592 case MISCREG_CPSR_MODE:
593 // This miscreg is used by copy*Regs to set the CPSR mode
594 // without updating other CPSR variables. It's used to
595 // make sure the register map is in such a state that we can
596 // see all of the registers for the copy.
597 updateRegMap(val);
598 return;
599 case MISCREG_L2CTLR:
600 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
601 miscRegName[misc_reg], uint32_t(val));
602 }
603 }
604 setMiscRegNoEffect(misc_reg, newVal);
605}
606
607}
|