isa.cc (8284:2fcad6253525) isa.cc (8299:64a938a8b7fc)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
46#include "sim/system.hh"
47
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
46#include "sim/system.hh"
47
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
55
55 uint32_t midr = miscRegs[MISCREG_MIDR];
56 memset(miscRegs, 0, sizeof(miscRegs));
57 CPSR cpsr = 0;
58 cpsr.mode = MODE_USER;
59 miscRegs[MISCREG_CPSR] = cpsr;
60 updateRegMap(cpsr);
61
62 SCTLR sctlr = 0;
63 sctlr.te = (bool)sctlr_rst.te;
64 sctlr.nmfi = (bool)sctlr_rst.nmfi;
65 sctlr.v = (bool)sctlr_rst.v;
66 sctlr.u = 1;
67 sctlr.xp = 1;
68 sctlr.rao2 = 1;
69 sctlr.rao3 = 1;
70 sctlr.rao4 = 1;
71 miscRegs[MISCREG_SCTLR] = sctlr;
72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
73
56 memset(miscRegs, 0, sizeof(miscRegs));
57 CPSR cpsr = 0;
58 cpsr.mode = MODE_USER;
59 miscRegs[MISCREG_CPSR] = cpsr;
60 updateRegMap(cpsr);
61
62 SCTLR sctlr = 0;
63 sctlr.te = (bool)sctlr_rst.te;
64 sctlr.nmfi = (bool)sctlr_rst.nmfi;
65 sctlr.v = (bool)sctlr_rst.v;
66 sctlr.u = 1;
67 sctlr.xp = 1;
68 sctlr.rao2 = 1;
69 sctlr.rao3 = 1;
70 sctlr.rao4 = 1;
71 miscRegs[MISCREG_SCTLR] = sctlr;
72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
73
74 // Preserve MIDR accross reset
75 miscRegs[MISCREG_MIDR] = midr;
76
74 /* Start with an event in the mailbox */
75 miscRegs[MISCREG_SEV_MAILBOX] = 1;
76
77 /* Start with an event in the mailbox */
78 miscRegs[MISCREG_SEV_MAILBOX] = 1;
79
77 /*
78 * Implemented = '5' from "M5",
79 * Variant = 0,
80 */
81 miscRegs[MISCREG_MIDR] =
82 (0x35 << 24) | // Implementor is '5' from "M5"
83 (0 << 20) | // Variant
84 (0xf << 16) | // Architecture from CPUID scheme
85 (0xf00 << 4) | // Primary part number
86 (0 << 0) | // Revision
87 0;
88
89 // Separate Instruction and Data TLBs.
90 miscRegs[MISCREG_TLBTR] = 1;
91
92 MVFR0 mvfr0 = 0;
93 mvfr0.advSimdRegisters = 2;
94 mvfr0.singlePrecision = 2;
95 mvfr0.doublePrecision = 2;
96 mvfr0.vfpExceptionTrapping = 0;
97 mvfr0.divide = 1;
98 mvfr0.squareRoot = 1;
99 mvfr0.shortVectors = 1;
100 mvfr0.roundingModes = 1;
101 miscRegs[MISCREG_MVFR0] = mvfr0;
102
103 MVFR1 mvfr1 = 0;
104 mvfr1.flushToZero = 1;
105 mvfr1.defaultNaN = 1;
106 mvfr1.advSimdLoadStore = 1;
107 mvfr1.advSimdInteger = 1;
108 mvfr1.advSimdSinglePrecision = 1;
109 mvfr1.advSimdHalfPrecision = 1;
110 mvfr1.vfpHalfPrecision = 1;
111 miscRegs[MISCREG_MVFR1] = mvfr1;
112
113 miscRegs[MISCREG_MPIDR] = 0;
114
115 // Reset values of PRRR and NMRR are implementation dependent
116
117 miscRegs[MISCREG_PRRR] =
118 (1 << 19) | // 19
119 (0 << 18) | // 18
120 (0 << 17) | // 17
121 (1 << 16) | // 16
122 (2 << 14) | // 15:14
123 (0 << 12) | // 13:12
124 (2 << 10) | // 11:10
125 (2 << 8) | // 9:8
126 (2 << 6) | // 7:6
127 (2 << 4) | // 5:4
128 (1 << 2) | // 3:2
129 0; // 1:0
130 miscRegs[MISCREG_NMRR] =
131 (1 << 30) | // 31:30
132 (0 << 26) | // 27:26
133 (0 << 24) | // 25:24
134 (3 << 22) | // 23:22
135 (2 << 20) | // 21:20
136 (0 << 18) | // 19:18
137 (0 << 16) | // 17:16
138 (1 << 14) | // 15:14
139 (0 << 12) | // 13:12
140 (2 << 10) | // 11:10
141 (0 << 8) | // 9:8
142 (3 << 6) | // 7:6
143 (2 << 4) | // 5:4
144 (0 << 2) | // 3:2
145 0; // 1:0
146
147 miscRegs[MISCREG_CPACR] = 0;
148 miscRegs[MISCREG_FPSID] = 0x410430A0;
149
150 // See section B4.1.84 of ARM ARM
151 // All values are latest for ARMv7-A profile
152 miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
153 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
154 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
155 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
156 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
157 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
158
159 //XXX We need to initialize the rest of the state.
160}
161
162MiscReg
163ISA::readMiscRegNoEffect(int misc_reg)
164{
165 assert(misc_reg < NumMiscRegs);
166
167 int flat_idx;
168 if (misc_reg == MISCREG_SPSR)
169 flat_idx = flattenMiscIndex(misc_reg);
170 else
171 flat_idx = misc_reg;
172 MiscReg val = miscRegs[flat_idx];
173
174 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
175 misc_reg, flat_idx, val);
176 return val;
177}
178
179
180MiscReg
181ISA::readMiscReg(int misc_reg, ThreadContext *tc)
182{
183 if (misc_reg == MISCREG_CPSR) {
184 CPSR cpsr = miscRegs[misc_reg];
185 PCState pc = tc->pcState();
186 cpsr.j = pc.jazelle() ? 1 : 0;
187 cpsr.t = pc.thumb() ? 1 : 0;
188 return cpsr;
189 }
190 if (misc_reg >= MISCREG_CP15_UNIMP_START)
191 panic("Unimplemented CP15 register %s read.\n",
192 miscRegName[misc_reg]);
193
194 switch (misc_reg) {
195 case MISCREG_MPIDR:
196 return tc->cpuId();
197 break;
198 case MISCREG_ID_MMFR3:
199 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
200 // BP Maint | Cache Maint Set/way | Cache Maint MVA
201 case MISCREG_CLIDR:
202 warn_once("The clidr register always reports 0 caches.\n");
203 break;
204 case MISCREG_CCSIDR:
205 warn_once("The ccsidr register isn't implemented and "
206 "always reads as 0.\n");
207 break;
208 case MISCREG_ID_PFR0:
209 warn("Returning thumbEE disabled for now since we don't support CP14"
210 "config registers and jumping to ThumbEE vectors\n");
211 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
80 // Separate Instruction and Data TLBs.
81 miscRegs[MISCREG_TLBTR] = 1;
82
83 MVFR0 mvfr0 = 0;
84 mvfr0.advSimdRegisters = 2;
85 mvfr0.singlePrecision = 2;
86 mvfr0.doublePrecision = 2;
87 mvfr0.vfpExceptionTrapping = 0;
88 mvfr0.divide = 1;
89 mvfr0.squareRoot = 1;
90 mvfr0.shortVectors = 1;
91 mvfr0.roundingModes = 1;
92 miscRegs[MISCREG_MVFR0] = mvfr0;
93
94 MVFR1 mvfr1 = 0;
95 mvfr1.flushToZero = 1;
96 mvfr1.defaultNaN = 1;
97 mvfr1.advSimdLoadStore = 1;
98 mvfr1.advSimdInteger = 1;
99 mvfr1.advSimdSinglePrecision = 1;
100 mvfr1.advSimdHalfPrecision = 1;
101 mvfr1.vfpHalfPrecision = 1;
102 miscRegs[MISCREG_MVFR1] = mvfr1;
103
104 miscRegs[MISCREG_MPIDR] = 0;
105
106 // Reset values of PRRR and NMRR are implementation dependent
107
108 miscRegs[MISCREG_PRRR] =
109 (1 << 19) | // 19
110 (0 << 18) | // 18
111 (0 << 17) | // 17
112 (1 << 16) | // 16
113 (2 << 14) | // 15:14
114 (0 << 12) | // 13:12
115 (2 << 10) | // 11:10
116 (2 << 8) | // 9:8
117 (2 << 6) | // 7:6
118 (2 << 4) | // 5:4
119 (1 << 2) | // 3:2
120 0; // 1:0
121 miscRegs[MISCREG_NMRR] =
122 (1 << 30) | // 31:30
123 (0 << 26) | // 27:26
124 (0 << 24) | // 25:24
125 (3 << 22) | // 23:22
126 (2 << 20) | // 21:20
127 (0 << 18) | // 19:18
128 (0 << 16) | // 17:16
129 (1 << 14) | // 15:14
130 (0 << 12) | // 13:12
131 (2 << 10) | // 11:10
132 (0 << 8) | // 9:8
133 (3 << 6) | // 7:6
134 (2 << 4) | // 5:4
135 (0 << 2) | // 3:2
136 0; // 1:0
137
138 miscRegs[MISCREG_CPACR] = 0;
139 miscRegs[MISCREG_FPSID] = 0x410430A0;
140
141 // See section B4.1.84 of ARM ARM
142 // All values are latest for ARMv7-A profile
143 miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
144 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
145 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
146 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
147 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
148 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
149
150 //XXX We need to initialize the rest of the state.
151}
152
153MiscReg
154ISA::readMiscRegNoEffect(int misc_reg)
155{
156 assert(misc_reg < NumMiscRegs);
157
158 int flat_idx;
159 if (misc_reg == MISCREG_SPSR)
160 flat_idx = flattenMiscIndex(misc_reg);
161 else
162 flat_idx = misc_reg;
163 MiscReg val = miscRegs[flat_idx];
164
165 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
166 misc_reg, flat_idx, val);
167 return val;
168}
169
170
171MiscReg
172ISA::readMiscReg(int misc_reg, ThreadContext *tc)
173{
174 if (misc_reg == MISCREG_CPSR) {
175 CPSR cpsr = miscRegs[misc_reg];
176 PCState pc = tc->pcState();
177 cpsr.j = pc.jazelle() ? 1 : 0;
178 cpsr.t = pc.thumb() ? 1 : 0;
179 return cpsr;
180 }
181 if (misc_reg >= MISCREG_CP15_UNIMP_START)
182 panic("Unimplemented CP15 register %s read.\n",
183 miscRegName[misc_reg]);
184
185 switch (misc_reg) {
186 case MISCREG_MPIDR:
187 return tc->cpuId();
188 break;
189 case MISCREG_ID_MMFR3:
190 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
191 // BP Maint | Cache Maint Set/way | Cache Maint MVA
192 case MISCREG_CLIDR:
193 warn_once("The clidr register always reports 0 caches.\n");
194 break;
195 case MISCREG_CCSIDR:
196 warn_once("The ccsidr register isn't implemented and "
197 "always reads as 0.\n");
198 break;
199 case MISCREG_ID_PFR0:
200 warn("Returning thumbEE disabled for now since we don't support CP14"
201 "config registers and jumping to ThumbEE vectors\n");
202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
203 case MISCREG_ID_PFR1:
204 warn("reading unimplmented register ID_PFR1");
205 return 0;
212 case MISCREG_ID_MMFR0:
213 return 0x03; //VMSAz7
214 case MISCREG_CTR:
215 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
216 case MISCREG_ACTLR:
217 warn("Not doing anything for miscreg ACTLR\n");
218 break;
219 case MISCREG_PMCR:
220 case MISCREG_PMCCNTR:
221 case MISCREG_PMSELR:
206 case MISCREG_ID_MMFR0:
207 return 0x03; //VMSAz7
208 case MISCREG_CTR:
209 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
210 case MISCREG_ACTLR:
211 warn("Not doing anything for miscreg ACTLR\n");
212 break;
213 case MISCREG_PMCR:
214 case MISCREG_PMCCNTR:
215 case MISCREG_PMSELR:
222 warn("Not doing anyhting for read to miscreg %s\n",
216 warn("Not doing anything for read to miscreg %s\n",
223 miscRegName[misc_reg]);
224 break;
225 case MISCREG_FPSCR_QC:
226 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
227 case MISCREG_FPSCR_EXC:
228 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
229 }
230 return readMiscRegNoEffect(misc_reg);
231}
232
233void
234ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
235{
236 assert(misc_reg < NumMiscRegs);
237
238 int flat_idx;
239 if (misc_reg == MISCREG_SPSR)
240 flat_idx = flattenMiscIndex(misc_reg);
241 else
242 flat_idx = misc_reg;
243 miscRegs[flat_idx] = val;
244
245 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
246 flat_idx, val);
247}
248
249void
250ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
251{
252
253 MiscReg newVal = val;
254 int x;
255 System *sys;
256 ThreadContext *oc;
257
258 if (misc_reg == MISCREG_CPSR) {
259 updateRegMap(val);
260
261
262 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
263 int old_mode = old_cpsr.mode;
264 CPSR cpsr = val;
265 if (old_mode != cpsr.mode) {
266 tc->getITBPtr()->invalidateMiscReg();
267 tc->getDTBPtr()->invalidateMiscReg();
268 }
269
270 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
271 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
272 PCState pc = tc->pcState();
273 pc.nextThumb(cpsr.t);
274 pc.nextJazelle(cpsr.j);
275 tc->pcState(pc);
276 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
277 misc_reg < MISCREG_CP15_END) {
278 panic("Unimplemented CP15 register %s wrote with %#x.\n",
279 miscRegName[misc_reg], val);
280 } else {
281 switch (misc_reg) {
282 case MISCREG_CPACR:
283 {
284
285 const uint32_t ones = (uint32_t)(-1);
286 CPACR cpacrMask = 0;
287 // Only cp10, cp11, and ase are implemented, nothing else should
288 // be writable
289 cpacrMask.cp10 = ones;
290 cpacrMask.cp11 = ones;
291 cpacrMask.asedis = ones;
292 newVal &= cpacrMask;
293 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
294 miscRegName[misc_reg], newVal);
295 }
296 break;
297 case MISCREG_CSSELR:
298 warn_once("The csselr register isn't implemented.\n");
299 return;
300 case MISCREG_FPSCR:
301 {
302 const uint32_t ones = (uint32_t)(-1);
303 FPSCR fpscrMask = 0;
304 fpscrMask.ioc = ones;
305 fpscrMask.dzc = ones;
306 fpscrMask.ofc = ones;
307 fpscrMask.ufc = ones;
308 fpscrMask.ixc = ones;
309 fpscrMask.idc = ones;
310 fpscrMask.len = ones;
311 fpscrMask.stride = ones;
312 fpscrMask.rMode = ones;
313 fpscrMask.fz = ones;
314 fpscrMask.dn = ones;
315 fpscrMask.ahp = ones;
316 fpscrMask.qc = ones;
317 fpscrMask.v = ones;
318 fpscrMask.c = ones;
319 fpscrMask.z = ones;
320 fpscrMask.n = ones;
321 newVal = (newVal & (uint32_t)fpscrMask) |
322 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
323 }
324 break;
325 case MISCREG_FPSCR_QC:
326 {
327 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
328 misc_reg = MISCREG_FPSCR;
329 }
330 break;
331 case MISCREG_FPSCR_EXC:
332 {
333 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
334 misc_reg = MISCREG_FPSCR;
335 }
336 break;
337 case MISCREG_FPEXC:
338 {
339 // vfpv3 architecture, section B.6.1 of DDI04068
340 // bit 29 - valid only if fpexc[31] is 0
341 const uint32_t fpexcMask = 0x60000000;
342 newVal = (newVal & fpexcMask) |
343 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
344 }
345 break;
346 case MISCREG_SCTLR:
347 {
348 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
349 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
350 SCTLR new_sctlr = newVal;
351 new_sctlr.nmfi = (bool)sctlr.nmfi;
352 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
353 tc->getITBPtr()->invalidateMiscReg();
354 tc->getDTBPtr()->invalidateMiscReg();
355 return;
356 }
357 case MISCREG_TLBTR:
358 case MISCREG_MVFR0:
359 case MISCREG_MVFR1:
360 case MISCREG_MPIDR:
361 case MISCREG_FPSID:
362 return;
363 case MISCREG_TLBIALLIS:
364 case MISCREG_TLBIALL:
365 sys = tc->getSystemPtr();
366 for (x = 0; x < sys->numContexts(); x++) {
367 oc = sys->getThreadContext(x);
368 assert(oc->getITBPtr() && oc->getDTBPtr());
369 oc->getITBPtr()->flushAll();
370 oc->getDTBPtr()->flushAll();
371 }
372 return;
373 case MISCREG_ITLBIALL:
374 tc->getITBPtr()->flushAll();
375 return;
376 case MISCREG_DTLBIALL:
377 tc->getDTBPtr()->flushAll();
378 return;
379 case MISCREG_TLBIMVAIS:
380 case MISCREG_TLBIMVA:
381 sys = tc->getSystemPtr();
382 for (x = 0; x < sys->numContexts(); x++) {
383 oc = sys->getThreadContext(x);
384 assert(oc->getITBPtr() && oc->getDTBPtr());
385 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
386 bits(newVal, 7,0));
387 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
388 bits(newVal, 7,0));
389 }
390 return;
391 case MISCREG_TLBIASIDIS:
392 case MISCREG_TLBIASID:
393 sys = tc->getSystemPtr();
394 for (x = 0; x < sys->numContexts(); x++) {
395 oc = sys->getThreadContext(x);
396 assert(oc->getITBPtr() && oc->getDTBPtr());
397 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
398 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
399 }
400 return;
401 case MISCREG_TLBIMVAAIS:
402 case MISCREG_TLBIMVAA:
403 sys = tc->getSystemPtr();
404 for (x = 0; x < sys->numContexts(); x++) {
405 oc = sys->getThreadContext(x);
406 assert(oc->getITBPtr() && oc->getDTBPtr());
407 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
408 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
409 }
410 return;
411 case MISCREG_ITLBIMVA:
412 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
413 bits(newVal, 7,0));
414 return;
415 case MISCREG_DTLBIMVA:
416 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
417 bits(newVal, 7,0));
418 return;
419 case MISCREG_ITLBIASID:
420 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
421 return;
422 case MISCREG_DTLBIASID:
423 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
424 return;
425 case MISCREG_ACTLR:
426 warn("Not doing anything for write of miscreg ACTLR\n");
427 break;
428 case MISCREG_PMCR:
429 {
430 // Performance counters not implemented. Instead, interpret
431 // a reset command to this register to reset the simulator
432 // statistics.
433 // PMCR_E | PMCR_P | PMCR_C
434 const int ResetAndEnableCounters = 0x7;
435 if (newVal == ResetAndEnableCounters) {
436 inform("Resetting all simobject stats\n");
437 Stats::schedStatEvent(false, true);
438 break;
439 }
440 }
441 case MISCREG_PMCCNTR:
442 case MISCREG_PMSELR:
443 warn("Not doing anything for write to miscreg %s\n",
444 miscRegName[misc_reg]);
445 break;
446 case MISCREG_V2PCWPR:
447 case MISCREG_V2PCWPW:
448 case MISCREG_V2PCWUR:
449 case MISCREG_V2PCWUW:
450 case MISCREG_V2POWPR:
451 case MISCREG_V2POWPW:
452 case MISCREG_V2POWUR:
453 case MISCREG_V2POWUW:
454 {
455 RequestPtr req = new Request;
456 unsigned flags;
457 BaseTLB::Mode mode;
458 Fault fault;
459 switch(misc_reg) {
460 case MISCREG_V2PCWPR:
461 flags = TLB::MustBeOne;
462 mode = BaseTLB::Read;
463 break;
464 case MISCREG_V2PCWPW:
465 flags = TLB::MustBeOne;
466 mode = BaseTLB::Write;
467 break;
468 case MISCREG_V2PCWUR:
469 flags = TLB::MustBeOne | TLB::UserMode;
470 mode = BaseTLB::Read;
471 break;
472 case MISCREG_V2PCWUW:
473 flags = TLB::MustBeOne | TLB::UserMode;
474 mode = BaseTLB::Write;
475 break;
476 default:
477 panic("Security Extensions not implemented!");
478 }
479 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
480 req->setVirt(0, val, 1, flags, tc->pcState().pc());
481 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
482 if (fault == NoFault) {
483 miscRegs[MISCREG_PAR] =
484 (req->getPaddr() & 0xfffff000) |
485 (tc->getDTBPtr()->getAttr() );
486 DPRINTF(MiscRegs,
487 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
488 val, miscRegs[MISCREG_PAR]);
489 }
490 else {
491 // Set fault bit and FSR
492 FSR fsr = miscRegs[MISCREG_DFSR];
493 miscRegs[MISCREG_PAR] =
494 (fsr.ext << 6) |
495 (fsr.fsHigh << 5) |
496 (fsr.fsLow << 1) |
497 0x1; // F bit
498 }
499 return;
500 }
501 case MISCREG_CONTEXTIDR:
502 case MISCREG_PRRR:
503 case MISCREG_NMRR:
504 case MISCREG_DACR:
505 tc->getITBPtr()->invalidateMiscReg();
506 tc->getDTBPtr()->invalidateMiscReg();
507 break;
508 case MISCREG_CPSR_MODE:
509 // This miscreg is used by copy*Regs to set the CPSR mode
510 // without updating other CPSR variables. It's used to
511 // make sure the register map is in such a state that we can
512 // see all of the registers for the copy.
513 updateRegMap(val);
514 return;
515 }
516 }
517 setMiscRegNoEffect(misc_reg, newVal);
518}
519
520}
217 miscRegName[misc_reg]);
218 break;
219 case MISCREG_FPSCR_QC:
220 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
221 case MISCREG_FPSCR_EXC:
222 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
223 }
224 return readMiscRegNoEffect(misc_reg);
225}
226
227void
228ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
229{
230 assert(misc_reg < NumMiscRegs);
231
232 int flat_idx;
233 if (misc_reg == MISCREG_SPSR)
234 flat_idx = flattenMiscIndex(misc_reg);
235 else
236 flat_idx = misc_reg;
237 miscRegs[flat_idx] = val;
238
239 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
240 flat_idx, val);
241}
242
243void
244ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
245{
246
247 MiscReg newVal = val;
248 int x;
249 System *sys;
250 ThreadContext *oc;
251
252 if (misc_reg == MISCREG_CPSR) {
253 updateRegMap(val);
254
255
256 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
257 int old_mode = old_cpsr.mode;
258 CPSR cpsr = val;
259 if (old_mode != cpsr.mode) {
260 tc->getITBPtr()->invalidateMiscReg();
261 tc->getDTBPtr()->invalidateMiscReg();
262 }
263
264 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
265 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
266 PCState pc = tc->pcState();
267 pc.nextThumb(cpsr.t);
268 pc.nextJazelle(cpsr.j);
269 tc->pcState(pc);
270 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
271 misc_reg < MISCREG_CP15_END) {
272 panic("Unimplemented CP15 register %s wrote with %#x.\n",
273 miscRegName[misc_reg], val);
274 } else {
275 switch (misc_reg) {
276 case MISCREG_CPACR:
277 {
278
279 const uint32_t ones = (uint32_t)(-1);
280 CPACR cpacrMask = 0;
281 // Only cp10, cp11, and ase are implemented, nothing else should
282 // be writable
283 cpacrMask.cp10 = ones;
284 cpacrMask.cp11 = ones;
285 cpacrMask.asedis = ones;
286 newVal &= cpacrMask;
287 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
288 miscRegName[misc_reg], newVal);
289 }
290 break;
291 case MISCREG_CSSELR:
292 warn_once("The csselr register isn't implemented.\n");
293 return;
294 case MISCREG_FPSCR:
295 {
296 const uint32_t ones = (uint32_t)(-1);
297 FPSCR fpscrMask = 0;
298 fpscrMask.ioc = ones;
299 fpscrMask.dzc = ones;
300 fpscrMask.ofc = ones;
301 fpscrMask.ufc = ones;
302 fpscrMask.ixc = ones;
303 fpscrMask.idc = ones;
304 fpscrMask.len = ones;
305 fpscrMask.stride = ones;
306 fpscrMask.rMode = ones;
307 fpscrMask.fz = ones;
308 fpscrMask.dn = ones;
309 fpscrMask.ahp = ones;
310 fpscrMask.qc = ones;
311 fpscrMask.v = ones;
312 fpscrMask.c = ones;
313 fpscrMask.z = ones;
314 fpscrMask.n = ones;
315 newVal = (newVal & (uint32_t)fpscrMask) |
316 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
317 }
318 break;
319 case MISCREG_FPSCR_QC:
320 {
321 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
322 misc_reg = MISCREG_FPSCR;
323 }
324 break;
325 case MISCREG_FPSCR_EXC:
326 {
327 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
328 misc_reg = MISCREG_FPSCR;
329 }
330 break;
331 case MISCREG_FPEXC:
332 {
333 // vfpv3 architecture, section B.6.1 of DDI04068
334 // bit 29 - valid only if fpexc[31] is 0
335 const uint32_t fpexcMask = 0x60000000;
336 newVal = (newVal & fpexcMask) |
337 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
338 }
339 break;
340 case MISCREG_SCTLR:
341 {
342 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
343 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
344 SCTLR new_sctlr = newVal;
345 new_sctlr.nmfi = (bool)sctlr.nmfi;
346 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
347 tc->getITBPtr()->invalidateMiscReg();
348 tc->getDTBPtr()->invalidateMiscReg();
349 return;
350 }
351 case MISCREG_TLBTR:
352 case MISCREG_MVFR0:
353 case MISCREG_MVFR1:
354 case MISCREG_MPIDR:
355 case MISCREG_FPSID:
356 return;
357 case MISCREG_TLBIALLIS:
358 case MISCREG_TLBIALL:
359 sys = tc->getSystemPtr();
360 for (x = 0; x < sys->numContexts(); x++) {
361 oc = sys->getThreadContext(x);
362 assert(oc->getITBPtr() && oc->getDTBPtr());
363 oc->getITBPtr()->flushAll();
364 oc->getDTBPtr()->flushAll();
365 }
366 return;
367 case MISCREG_ITLBIALL:
368 tc->getITBPtr()->flushAll();
369 return;
370 case MISCREG_DTLBIALL:
371 tc->getDTBPtr()->flushAll();
372 return;
373 case MISCREG_TLBIMVAIS:
374 case MISCREG_TLBIMVA:
375 sys = tc->getSystemPtr();
376 for (x = 0; x < sys->numContexts(); x++) {
377 oc = sys->getThreadContext(x);
378 assert(oc->getITBPtr() && oc->getDTBPtr());
379 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
380 bits(newVal, 7,0));
381 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
382 bits(newVal, 7,0));
383 }
384 return;
385 case MISCREG_TLBIASIDIS:
386 case MISCREG_TLBIASID:
387 sys = tc->getSystemPtr();
388 for (x = 0; x < sys->numContexts(); x++) {
389 oc = sys->getThreadContext(x);
390 assert(oc->getITBPtr() && oc->getDTBPtr());
391 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
392 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
393 }
394 return;
395 case MISCREG_TLBIMVAAIS:
396 case MISCREG_TLBIMVAA:
397 sys = tc->getSystemPtr();
398 for (x = 0; x < sys->numContexts(); x++) {
399 oc = sys->getThreadContext(x);
400 assert(oc->getITBPtr() && oc->getDTBPtr());
401 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
402 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
403 }
404 return;
405 case MISCREG_ITLBIMVA:
406 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
407 bits(newVal, 7,0));
408 return;
409 case MISCREG_DTLBIMVA:
410 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
411 bits(newVal, 7,0));
412 return;
413 case MISCREG_ITLBIASID:
414 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
415 return;
416 case MISCREG_DTLBIASID:
417 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
418 return;
419 case MISCREG_ACTLR:
420 warn("Not doing anything for write of miscreg ACTLR\n");
421 break;
422 case MISCREG_PMCR:
423 {
424 // Performance counters not implemented. Instead, interpret
425 // a reset command to this register to reset the simulator
426 // statistics.
427 // PMCR_E | PMCR_P | PMCR_C
428 const int ResetAndEnableCounters = 0x7;
429 if (newVal == ResetAndEnableCounters) {
430 inform("Resetting all simobject stats\n");
431 Stats::schedStatEvent(false, true);
432 break;
433 }
434 }
435 case MISCREG_PMCCNTR:
436 case MISCREG_PMSELR:
437 warn("Not doing anything for write to miscreg %s\n",
438 miscRegName[misc_reg]);
439 break;
440 case MISCREG_V2PCWPR:
441 case MISCREG_V2PCWPW:
442 case MISCREG_V2PCWUR:
443 case MISCREG_V2PCWUW:
444 case MISCREG_V2POWPR:
445 case MISCREG_V2POWPW:
446 case MISCREG_V2POWUR:
447 case MISCREG_V2POWUW:
448 {
449 RequestPtr req = new Request;
450 unsigned flags;
451 BaseTLB::Mode mode;
452 Fault fault;
453 switch(misc_reg) {
454 case MISCREG_V2PCWPR:
455 flags = TLB::MustBeOne;
456 mode = BaseTLB::Read;
457 break;
458 case MISCREG_V2PCWPW:
459 flags = TLB::MustBeOne;
460 mode = BaseTLB::Write;
461 break;
462 case MISCREG_V2PCWUR:
463 flags = TLB::MustBeOne | TLB::UserMode;
464 mode = BaseTLB::Read;
465 break;
466 case MISCREG_V2PCWUW:
467 flags = TLB::MustBeOne | TLB::UserMode;
468 mode = BaseTLB::Write;
469 break;
470 default:
471 panic("Security Extensions not implemented!");
472 }
473 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
474 req->setVirt(0, val, 1, flags, tc->pcState().pc());
475 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
476 if (fault == NoFault) {
477 miscRegs[MISCREG_PAR] =
478 (req->getPaddr() & 0xfffff000) |
479 (tc->getDTBPtr()->getAttr() );
480 DPRINTF(MiscRegs,
481 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
482 val, miscRegs[MISCREG_PAR]);
483 }
484 else {
485 // Set fault bit and FSR
486 FSR fsr = miscRegs[MISCREG_DFSR];
487 miscRegs[MISCREG_PAR] =
488 (fsr.ext << 6) |
489 (fsr.fsHigh << 5) |
490 (fsr.fsLow << 1) |
491 0x1; // F bit
492 }
493 return;
494 }
495 case MISCREG_CONTEXTIDR:
496 case MISCREG_PRRR:
497 case MISCREG_NMRR:
498 case MISCREG_DACR:
499 tc->getITBPtr()->invalidateMiscReg();
500 tc->getDTBPtr()->invalidateMiscReg();
501 break;
502 case MISCREG_CPSR_MODE:
503 // This miscreg is used by copy*Regs to set the CPSR mode
504 // without updating other CPSR variables. It's used to
505 // make sure the register map is in such a state that we can
506 // see all of the registers for the copy.
507 updateRegMap(val);
508 return;
509 }
510 }
511 setMiscRegNoEffect(misc_reg, newVal);
512}
513
514}