isa.cc (8147:ac8ef72e9700) isa.cc (8205:7ecbffb674aa)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43#include "sim/stat_control.hh"
44
45namespace ArmISA
46{
47
48void
49ISA::clear()
50{
51 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
52
53 memset(miscRegs, 0, sizeof(miscRegs));
54 CPSR cpsr = 0;
55 cpsr.mode = MODE_USER;
56 miscRegs[MISCREG_CPSR] = cpsr;
57 updateRegMap(cpsr);
58
59 SCTLR sctlr = 0;
60 sctlr.te = (bool)sctlr_rst.te;
61 sctlr.nmfi = (bool)sctlr_rst.nmfi;
62 sctlr.v = (bool)sctlr_rst.v;
63 sctlr.u = 1;
64 sctlr.xp = 1;
65 sctlr.rao2 = 1;
66 sctlr.rao3 = 1;
67 sctlr.rao4 = 1;
68 miscRegs[MISCREG_SCTLR] = sctlr;
69 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
70
71 /* Start with an event in the mailbox */
72 miscRegs[MISCREG_SEV_MAILBOX] = 1;
73
74 /*
75 * Implemented = '5' from "M5",
76 * Variant = 0,
77 */
78 miscRegs[MISCREG_MIDR] =
79 (0x35 << 24) | // Implementor is '5' from "M5"
80 (0 << 20) | // Variant
81 (0xf << 16) | // Architecture from CPUID scheme
82 (0xf00 << 4) | // Primary part number
83 (0 << 0) | // Revision
84 0;
85
86 // Separate Instruction and Data TLBs.
87 miscRegs[MISCREG_TLBTR] = 1;
88
89 MVFR0 mvfr0 = 0;
90 mvfr0.advSimdRegisters = 2;
91 mvfr0.singlePrecision = 2;
92 mvfr0.doublePrecision = 2;
93 mvfr0.vfpExceptionTrapping = 0;
94 mvfr0.divide = 1;
95 mvfr0.squareRoot = 1;
96 mvfr0.shortVectors = 1;
97 mvfr0.roundingModes = 1;
98 miscRegs[MISCREG_MVFR0] = mvfr0;
99
100 MVFR1 mvfr1 = 0;
101 mvfr1.flushToZero = 1;
102 mvfr1.defaultNaN = 1;
103 mvfr1.advSimdLoadStore = 1;
104 mvfr1.advSimdInteger = 1;
105 mvfr1.advSimdSinglePrecision = 1;
106 mvfr1.advSimdHalfPrecision = 1;
107 mvfr1.vfpHalfPrecision = 1;
108 miscRegs[MISCREG_MVFR1] = mvfr1;
109
110 miscRegs[MISCREG_MPIDR] = 0;
111
112 // Reset values of PRRR and NMRR are implementation dependent
113
114 miscRegs[MISCREG_PRRR] =
115 (1 << 19) | // 19
116 (0 << 18) | // 18
117 (0 << 17) | // 17
118 (1 << 16) | // 16
119 (2 << 14) | // 15:14
120 (0 << 12) | // 13:12
121 (2 << 10) | // 11:10
122 (2 << 8) | // 9:8
123 (2 << 6) | // 7:6
124 (2 << 4) | // 5:4
125 (1 << 2) | // 3:2
126 0; // 1:0
127 miscRegs[MISCREG_NMRR] =
128 (1 << 30) | // 31:30
129 (0 << 26) | // 27:26
130 (0 << 24) | // 25:24
131 (3 << 22) | // 23:22
132 (2 << 20) | // 21:20
133 (0 << 18) | // 19:18
134 (0 << 16) | // 17:16
135 (1 << 14) | // 15:14
136 (0 << 12) | // 13:12
137 (2 << 10) | // 11:10
138 (0 << 8) | // 9:8
139 (3 << 6) | // 7:6
140 (2 << 4) | // 5:4
141 (0 << 2) | // 3:2
142 0; // 1:0
143
144 miscRegs[MISCREG_CPACR] = 0;
145 miscRegs[MISCREG_FPSID] = 0x410430A0;
146
147 // See section B4.1.84 of ARM ARM
148 // All values are latest for ARMv7-A profile
149 miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
150 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
151 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
152 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
153 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
154 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
155
156 //XXX We need to initialize the rest of the state.
157}
158
159MiscReg
160ISA::readMiscRegNoEffect(int misc_reg)
161{
162 assert(misc_reg < NumMiscRegs);
163
164 int flat_idx;
165 if (misc_reg == MISCREG_SPSR)
166 flat_idx = flattenMiscIndex(misc_reg);
167 else
168 flat_idx = misc_reg;
169 MiscReg val = miscRegs[flat_idx];
170
171 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
172 misc_reg, flat_idx, val);
173 return val;
174}
175
176
177MiscReg
178ISA::readMiscReg(int misc_reg, ThreadContext *tc)
179{
180 if (misc_reg == MISCREG_CPSR) {
181 CPSR cpsr = miscRegs[misc_reg];
182 PCState pc = tc->pcState();
183 cpsr.j = pc.jazelle() ? 1 : 0;
184 cpsr.t = pc.thumb() ? 1 : 0;
185 return cpsr;
186 }
187 if (misc_reg >= MISCREG_CP15_UNIMP_START)
188 panic("Unimplemented CP15 register %s read.\n",
189 miscRegName[misc_reg]);
190
191 switch (misc_reg) {
192 case MISCREG_CLIDR:
193 warn_once("The clidr register always reports 0 caches.\n");
194 break;
195 case MISCREG_CCSIDR:
196 warn_once("The ccsidr register isn't implemented and "
197 "always reads as 0.\n");
198 break;
199 case MISCREG_ID_PFR0:
200 warn("Returning thumbEE disabled for now since we don't support CP14"
201 "config registers and jumping to ThumbEE vectors\n");
202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
203 case MISCREG_ID_MMFR0:
204 return 0x03; //VMSAz7
205 case MISCREG_CTR:
206 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
207 case MISCREG_ACTLR:
208 warn("Not doing anything for miscreg ACTLR\n");
209 break;
210 case MISCREG_PMCR:
211 case MISCREG_PMCCNTR:
212 case MISCREG_PMSELR:
213 warn("Not doing anyhting for read to miscreg %s\n",
214 miscRegName[misc_reg]);
215 break;
216 case MISCREG_FPSCR_QC:
217 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
218 case MISCREG_FPSCR_EXC:
219 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
220 }
221 return readMiscRegNoEffect(misc_reg);
222}
223
224void
225ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
226{
227 assert(misc_reg < NumMiscRegs);
228
229 int flat_idx;
230 if (misc_reg == MISCREG_SPSR)
231 flat_idx = flattenMiscIndex(misc_reg);
232 else
233 flat_idx = misc_reg;
234 miscRegs[flat_idx] = val;
235
236 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
237 flat_idx, val);
238}
239
240void
241ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
242{
243
244 MiscReg newVal = val;
245 if (misc_reg == MISCREG_CPSR) {
246 updateRegMap(val);
247
248
249 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
250 int old_mode = old_cpsr.mode;
251 CPSR cpsr = val;
252 if (old_mode != cpsr.mode) {
253 tc->getITBPtr()->invalidateMiscReg();
254 tc->getDTBPtr()->invalidateMiscReg();
255 }
256
257 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
258 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
259 PCState pc = tc->pcState();
260 pc.nextThumb(cpsr.t);
261 pc.nextJazelle(cpsr.j);
262 tc->pcState(pc);
263 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
264 misc_reg < MISCREG_CP15_END) {
265 panic("Unimplemented CP15 register %s wrote with %#x.\n",
266 miscRegName[misc_reg], val);
267 } else {
268 switch (misc_reg) {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43#include "sim/stat_control.hh"
44
45namespace ArmISA
46{
47
48void
49ISA::clear()
50{
51 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
52
53 memset(miscRegs, 0, sizeof(miscRegs));
54 CPSR cpsr = 0;
55 cpsr.mode = MODE_USER;
56 miscRegs[MISCREG_CPSR] = cpsr;
57 updateRegMap(cpsr);
58
59 SCTLR sctlr = 0;
60 sctlr.te = (bool)sctlr_rst.te;
61 sctlr.nmfi = (bool)sctlr_rst.nmfi;
62 sctlr.v = (bool)sctlr_rst.v;
63 sctlr.u = 1;
64 sctlr.xp = 1;
65 sctlr.rao2 = 1;
66 sctlr.rao3 = 1;
67 sctlr.rao4 = 1;
68 miscRegs[MISCREG_SCTLR] = sctlr;
69 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
70
71 /* Start with an event in the mailbox */
72 miscRegs[MISCREG_SEV_MAILBOX] = 1;
73
74 /*
75 * Implemented = '5' from "M5",
76 * Variant = 0,
77 */
78 miscRegs[MISCREG_MIDR] =
79 (0x35 << 24) | // Implementor is '5' from "M5"
80 (0 << 20) | // Variant
81 (0xf << 16) | // Architecture from CPUID scheme
82 (0xf00 << 4) | // Primary part number
83 (0 << 0) | // Revision
84 0;
85
86 // Separate Instruction and Data TLBs.
87 miscRegs[MISCREG_TLBTR] = 1;
88
89 MVFR0 mvfr0 = 0;
90 mvfr0.advSimdRegisters = 2;
91 mvfr0.singlePrecision = 2;
92 mvfr0.doublePrecision = 2;
93 mvfr0.vfpExceptionTrapping = 0;
94 mvfr0.divide = 1;
95 mvfr0.squareRoot = 1;
96 mvfr0.shortVectors = 1;
97 mvfr0.roundingModes = 1;
98 miscRegs[MISCREG_MVFR0] = mvfr0;
99
100 MVFR1 mvfr1 = 0;
101 mvfr1.flushToZero = 1;
102 mvfr1.defaultNaN = 1;
103 mvfr1.advSimdLoadStore = 1;
104 mvfr1.advSimdInteger = 1;
105 mvfr1.advSimdSinglePrecision = 1;
106 mvfr1.advSimdHalfPrecision = 1;
107 mvfr1.vfpHalfPrecision = 1;
108 miscRegs[MISCREG_MVFR1] = mvfr1;
109
110 miscRegs[MISCREG_MPIDR] = 0;
111
112 // Reset values of PRRR and NMRR are implementation dependent
113
114 miscRegs[MISCREG_PRRR] =
115 (1 << 19) | // 19
116 (0 << 18) | // 18
117 (0 << 17) | // 17
118 (1 << 16) | // 16
119 (2 << 14) | // 15:14
120 (0 << 12) | // 13:12
121 (2 << 10) | // 11:10
122 (2 << 8) | // 9:8
123 (2 << 6) | // 7:6
124 (2 << 4) | // 5:4
125 (1 << 2) | // 3:2
126 0; // 1:0
127 miscRegs[MISCREG_NMRR] =
128 (1 << 30) | // 31:30
129 (0 << 26) | // 27:26
130 (0 << 24) | // 25:24
131 (3 << 22) | // 23:22
132 (2 << 20) | // 21:20
133 (0 << 18) | // 19:18
134 (0 << 16) | // 17:16
135 (1 << 14) | // 15:14
136 (0 << 12) | // 13:12
137 (2 << 10) | // 11:10
138 (0 << 8) | // 9:8
139 (3 << 6) | // 7:6
140 (2 << 4) | // 5:4
141 (0 << 2) | // 3:2
142 0; // 1:0
143
144 miscRegs[MISCREG_CPACR] = 0;
145 miscRegs[MISCREG_FPSID] = 0x410430A0;
146
147 // See section B4.1.84 of ARM ARM
148 // All values are latest for ARMv7-A profile
149 miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
150 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
151 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
152 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
153 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
154 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
155
156 //XXX We need to initialize the rest of the state.
157}
158
159MiscReg
160ISA::readMiscRegNoEffect(int misc_reg)
161{
162 assert(misc_reg < NumMiscRegs);
163
164 int flat_idx;
165 if (misc_reg == MISCREG_SPSR)
166 flat_idx = flattenMiscIndex(misc_reg);
167 else
168 flat_idx = misc_reg;
169 MiscReg val = miscRegs[flat_idx];
170
171 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
172 misc_reg, flat_idx, val);
173 return val;
174}
175
176
177MiscReg
178ISA::readMiscReg(int misc_reg, ThreadContext *tc)
179{
180 if (misc_reg == MISCREG_CPSR) {
181 CPSR cpsr = miscRegs[misc_reg];
182 PCState pc = tc->pcState();
183 cpsr.j = pc.jazelle() ? 1 : 0;
184 cpsr.t = pc.thumb() ? 1 : 0;
185 return cpsr;
186 }
187 if (misc_reg >= MISCREG_CP15_UNIMP_START)
188 panic("Unimplemented CP15 register %s read.\n",
189 miscRegName[misc_reg]);
190
191 switch (misc_reg) {
192 case MISCREG_CLIDR:
193 warn_once("The clidr register always reports 0 caches.\n");
194 break;
195 case MISCREG_CCSIDR:
196 warn_once("The ccsidr register isn't implemented and "
197 "always reads as 0.\n");
198 break;
199 case MISCREG_ID_PFR0:
200 warn("Returning thumbEE disabled for now since we don't support CP14"
201 "config registers and jumping to ThumbEE vectors\n");
202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
203 case MISCREG_ID_MMFR0:
204 return 0x03; //VMSAz7
205 case MISCREG_CTR:
206 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
207 case MISCREG_ACTLR:
208 warn("Not doing anything for miscreg ACTLR\n");
209 break;
210 case MISCREG_PMCR:
211 case MISCREG_PMCCNTR:
212 case MISCREG_PMSELR:
213 warn("Not doing anyhting for read to miscreg %s\n",
214 miscRegName[misc_reg]);
215 break;
216 case MISCREG_FPSCR_QC:
217 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
218 case MISCREG_FPSCR_EXC:
219 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
220 }
221 return readMiscRegNoEffect(misc_reg);
222}
223
224void
225ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
226{
227 assert(misc_reg < NumMiscRegs);
228
229 int flat_idx;
230 if (misc_reg == MISCREG_SPSR)
231 flat_idx = flattenMiscIndex(misc_reg);
232 else
233 flat_idx = misc_reg;
234 miscRegs[flat_idx] = val;
235
236 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
237 flat_idx, val);
238}
239
240void
241ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
242{
243
244 MiscReg newVal = val;
245 if (misc_reg == MISCREG_CPSR) {
246 updateRegMap(val);
247
248
249 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
250 int old_mode = old_cpsr.mode;
251 CPSR cpsr = val;
252 if (old_mode != cpsr.mode) {
253 tc->getITBPtr()->invalidateMiscReg();
254 tc->getDTBPtr()->invalidateMiscReg();
255 }
256
257 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
258 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
259 PCState pc = tc->pcState();
260 pc.nextThumb(cpsr.t);
261 pc.nextJazelle(cpsr.j);
262 tc->pcState(pc);
263 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
264 misc_reg < MISCREG_CP15_END) {
265 panic("Unimplemented CP15 register %s wrote with %#x.\n",
266 miscRegName[misc_reg], val);
267 } else {
268 switch (misc_reg) {
269 case MISCREG_ITSTATE:
270 {
271 ITSTATE itstate = newVal;
272 CPSR cpsr = miscRegs[MISCREG_CPSR];
273 cpsr.it1 = itstate.bottom2;
274 cpsr.it2 = itstate.top6;
275 miscRegs[MISCREG_CPSR] = cpsr;
276 DPRINTF(MiscRegs,
277 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
278 (uint8_t)itstate, (uint32_t)cpsr);
279 }
280 break;
281 case MISCREG_CPACR:
282 {
283 CPACR newCpacr = 0;
284 CPACR valCpacr = val;
285 newCpacr.cp10 = valCpacr.cp10;
286 newCpacr.cp11 = valCpacr.cp11;
287 //XXX d32dis isn't implemented. The manual says whether or not
288 //it works is implementation defined.
289 newCpacr.asedis = valCpacr.asedis;
290 newVal = newCpacr;
291 }
292 break;
293 case MISCREG_CSSELR:
294 warn_once("The csselr register isn't implemented.\n");
295 break;
296 case MISCREG_FPSCR:
297 {
298 const uint32_t ones = (uint32_t)(-1);
299 FPSCR fpscrMask = 0;
300 fpscrMask.ioc = ones;
301 fpscrMask.dzc = ones;
302 fpscrMask.ofc = ones;
303 fpscrMask.ufc = ones;
304 fpscrMask.ixc = ones;
305 fpscrMask.idc = ones;
306 fpscrMask.len = ones;
307 fpscrMask.stride = ones;
308 fpscrMask.rMode = ones;
309 fpscrMask.fz = ones;
310 fpscrMask.dn = ones;
311 fpscrMask.ahp = ones;
312 fpscrMask.qc = ones;
313 fpscrMask.v = ones;
314 fpscrMask.c = ones;
315 fpscrMask.z = ones;
316 fpscrMask.n = ones;
317 newVal = (newVal & (uint32_t)fpscrMask) |
318 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
319 }
320 break;
321 case MISCREG_FPSCR_QC:
322 {
323 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
324 misc_reg = MISCREG_FPSCR;
325 }
326 break;
327 case MISCREG_FPSCR_EXC:
328 {
329 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
330 misc_reg = MISCREG_FPSCR;
331 }
332 break;
333 case MISCREG_FPEXC:
334 {
335 const uint32_t fpexcMask = 0x60000000;
336 newVal = (newVal & fpexcMask) |
337 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
338 }
339 break;
340 case MISCREG_SCTLR:
341 {
342 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
343 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
344 SCTLR new_sctlr = newVal;
345 new_sctlr.nmfi = (bool)sctlr.nmfi;
346 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
347 tc->getITBPtr()->invalidateMiscReg();
348 tc->getDTBPtr()->invalidateMiscReg();
349 return;
350 }
351 case MISCREG_TLBTR:
352 case MISCREG_MVFR0:
353 case MISCREG_MVFR1:
354 case MISCREG_MPIDR:
355 case MISCREG_FPSID:
356 return;
357 case MISCREG_TLBIALLIS:
358 case MISCREG_TLBIALL:
359 warn_once("Need to flush all TLBs in MP\n");
360 tc->getITBPtr()->flushAll();
361 tc->getDTBPtr()->flushAll();
362 return;
363 case MISCREG_ITLBIALL:
364 tc->getITBPtr()->flushAll();
365 return;
366 case MISCREG_DTLBIALL:
367 tc->getDTBPtr()->flushAll();
368 return;
369 case MISCREG_TLBIMVAIS:
370 case MISCREG_TLBIMVA:
371 warn_once("Need to flush all TLBs in MP\n");
372 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
373 bits(newVal, 7,0));
374 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
375 bits(newVal, 7,0));
376 return;
377 case MISCREG_TLBIASIDIS:
378 case MISCREG_TLBIASID:
379 warn_once("Need to flush all TLBs in MP\n");
380 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
381 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
382 return;
383 case MISCREG_TLBIMVAAIS:
384 case MISCREG_TLBIMVAA:
385 warn_once("Need to flush all TLBs in MP\n");
386 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
387 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
388 return;
389 case MISCREG_ITLBIMVA:
390 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
391 bits(newVal, 7,0));
392 return;
393 case MISCREG_DTLBIMVA:
394 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
395 bits(newVal, 7,0));
396 return;
397 case MISCREG_ITLBIASID:
398 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
399 return;
400 case MISCREG_DTLBIASID:
401 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
402 return;
403 case MISCREG_ACTLR:
404 warn("Not doing anything for write of miscreg ACTLR\n");
405 break;
406 case MISCREG_PMCR:
407 {
408 // Performance counters not implemented. Instead, interpret
409 // a reset command to this register to reset the simulator
410 // statistics.
411 // PMCR_E | PMCR_P | PMCR_C
412 const int ResetAndEnableCounters = 0x7;
413 if (newVal == ResetAndEnableCounters) {
414 inform("Resetting all simobject stats\n");
415 Stats::schedStatEvent(false, true);
416 break;
417 }
418 }
419 case MISCREG_PMCCNTR:
420 case MISCREG_PMSELR:
421 warn("Not doing anything for write to miscreg %s\n",
422 miscRegName[misc_reg]);
423 break;
424 case MISCREG_V2PCWPR:
425 case MISCREG_V2PCWPW:
426 case MISCREG_V2PCWUR:
427 case MISCREG_V2PCWUW:
428 case MISCREG_V2POWPR:
429 case MISCREG_V2POWPW:
430 case MISCREG_V2POWUR:
431 case MISCREG_V2POWUW:
432 {
433 RequestPtr req = new Request;
434 unsigned flags;
435 BaseTLB::Mode mode;
436 Fault fault;
437 switch(misc_reg) {
438 case MISCREG_V2PCWPR:
439 flags = TLB::MustBeOne;
440 mode = BaseTLB::Read;
441 break;
442 case MISCREG_V2PCWPW:
443 flags = TLB::MustBeOne;
444 mode = BaseTLB::Write;
445 break;
446 case MISCREG_V2PCWUR:
447 flags = TLB::MustBeOne | TLB::UserMode;
448 mode = BaseTLB::Read;
449 break;
450 case MISCREG_V2PCWUW:
451 flags = TLB::MustBeOne | TLB::UserMode;
452 mode = BaseTLB::Write;
453 break;
454 default:
455 panic("Security Extensions not implemented!");
456 }
457 req->setVirt(0, val, 1, flags, tc->pcState().pc());
458 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
459 if (fault == NoFault) {
460 miscRegs[MISCREG_PAR] =
461 (req->getPaddr() & 0xfffff000) |
462 (tc->getDTBPtr()->getAttr() );
463 DPRINTF(MiscRegs,
464 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
465 val, miscRegs[MISCREG_PAR]);
466 }
467 else {
468 // Set fault bit and FSR
469 FSR fsr = miscRegs[MISCREG_DFSR];
470 miscRegs[MISCREG_PAR] =
471 (fsr.ext << 6) |
472 (fsr.fsHigh << 5) |
473 (fsr.fsLow << 1) |
474 0x1; // F bit
475 }
476 return;
477 }
478 case MISCREG_CONTEXTIDR:
479 case MISCREG_PRRR:
480 case MISCREG_NMRR:
481 case MISCREG_DACR:
482 tc->getITBPtr()->invalidateMiscReg();
483 tc->getDTBPtr()->invalidateMiscReg();
484 break;
485
486 }
487 }
488 setMiscRegNoEffect(misc_reg, newVal);
489}
490
491}
269 case MISCREG_CPACR:
270 {
271 CPACR newCpacr = 0;
272 CPACR valCpacr = val;
273 newCpacr.cp10 = valCpacr.cp10;
274 newCpacr.cp11 = valCpacr.cp11;
275 //XXX d32dis isn't implemented. The manual says whether or not
276 //it works is implementation defined.
277 newCpacr.asedis = valCpacr.asedis;
278 newVal = newCpacr;
279 }
280 break;
281 case MISCREG_CSSELR:
282 warn_once("The csselr register isn't implemented.\n");
283 break;
284 case MISCREG_FPSCR:
285 {
286 const uint32_t ones = (uint32_t)(-1);
287 FPSCR fpscrMask = 0;
288 fpscrMask.ioc = ones;
289 fpscrMask.dzc = ones;
290 fpscrMask.ofc = ones;
291 fpscrMask.ufc = ones;
292 fpscrMask.ixc = ones;
293 fpscrMask.idc = ones;
294 fpscrMask.len = ones;
295 fpscrMask.stride = ones;
296 fpscrMask.rMode = ones;
297 fpscrMask.fz = ones;
298 fpscrMask.dn = ones;
299 fpscrMask.ahp = ones;
300 fpscrMask.qc = ones;
301 fpscrMask.v = ones;
302 fpscrMask.c = ones;
303 fpscrMask.z = ones;
304 fpscrMask.n = ones;
305 newVal = (newVal & (uint32_t)fpscrMask) |
306 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
307 }
308 break;
309 case MISCREG_FPSCR_QC:
310 {
311 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
312 misc_reg = MISCREG_FPSCR;
313 }
314 break;
315 case MISCREG_FPSCR_EXC:
316 {
317 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
318 misc_reg = MISCREG_FPSCR;
319 }
320 break;
321 case MISCREG_FPEXC:
322 {
323 const uint32_t fpexcMask = 0x60000000;
324 newVal = (newVal & fpexcMask) |
325 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
326 }
327 break;
328 case MISCREG_SCTLR:
329 {
330 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
331 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
332 SCTLR new_sctlr = newVal;
333 new_sctlr.nmfi = (bool)sctlr.nmfi;
334 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
335 tc->getITBPtr()->invalidateMiscReg();
336 tc->getDTBPtr()->invalidateMiscReg();
337 return;
338 }
339 case MISCREG_TLBTR:
340 case MISCREG_MVFR0:
341 case MISCREG_MVFR1:
342 case MISCREG_MPIDR:
343 case MISCREG_FPSID:
344 return;
345 case MISCREG_TLBIALLIS:
346 case MISCREG_TLBIALL:
347 warn_once("Need to flush all TLBs in MP\n");
348 tc->getITBPtr()->flushAll();
349 tc->getDTBPtr()->flushAll();
350 return;
351 case MISCREG_ITLBIALL:
352 tc->getITBPtr()->flushAll();
353 return;
354 case MISCREG_DTLBIALL:
355 tc->getDTBPtr()->flushAll();
356 return;
357 case MISCREG_TLBIMVAIS:
358 case MISCREG_TLBIMVA:
359 warn_once("Need to flush all TLBs in MP\n");
360 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
361 bits(newVal, 7,0));
362 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
363 bits(newVal, 7,0));
364 return;
365 case MISCREG_TLBIASIDIS:
366 case MISCREG_TLBIASID:
367 warn_once("Need to flush all TLBs in MP\n");
368 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
369 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
370 return;
371 case MISCREG_TLBIMVAAIS:
372 case MISCREG_TLBIMVAA:
373 warn_once("Need to flush all TLBs in MP\n");
374 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
375 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
376 return;
377 case MISCREG_ITLBIMVA:
378 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
379 bits(newVal, 7,0));
380 return;
381 case MISCREG_DTLBIMVA:
382 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
383 bits(newVal, 7,0));
384 return;
385 case MISCREG_ITLBIASID:
386 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
387 return;
388 case MISCREG_DTLBIASID:
389 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
390 return;
391 case MISCREG_ACTLR:
392 warn("Not doing anything for write of miscreg ACTLR\n");
393 break;
394 case MISCREG_PMCR:
395 {
396 // Performance counters not implemented. Instead, interpret
397 // a reset command to this register to reset the simulator
398 // statistics.
399 // PMCR_E | PMCR_P | PMCR_C
400 const int ResetAndEnableCounters = 0x7;
401 if (newVal == ResetAndEnableCounters) {
402 inform("Resetting all simobject stats\n");
403 Stats::schedStatEvent(false, true);
404 break;
405 }
406 }
407 case MISCREG_PMCCNTR:
408 case MISCREG_PMSELR:
409 warn("Not doing anything for write to miscreg %s\n",
410 miscRegName[misc_reg]);
411 break;
412 case MISCREG_V2PCWPR:
413 case MISCREG_V2PCWPW:
414 case MISCREG_V2PCWUR:
415 case MISCREG_V2PCWUW:
416 case MISCREG_V2POWPR:
417 case MISCREG_V2POWPW:
418 case MISCREG_V2POWUR:
419 case MISCREG_V2POWUW:
420 {
421 RequestPtr req = new Request;
422 unsigned flags;
423 BaseTLB::Mode mode;
424 Fault fault;
425 switch(misc_reg) {
426 case MISCREG_V2PCWPR:
427 flags = TLB::MustBeOne;
428 mode = BaseTLB::Read;
429 break;
430 case MISCREG_V2PCWPW:
431 flags = TLB::MustBeOne;
432 mode = BaseTLB::Write;
433 break;
434 case MISCREG_V2PCWUR:
435 flags = TLB::MustBeOne | TLB::UserMode;
436 mode = BaseTLB::Read;
437 break;
438 case MISCREG_V2PCWUW:
439 flags = TLB::MustBeOne | TLB::UserMode;
440 mode = BaseTLB::Write;
441 break;
442 default:
443 panic("Security Extensions not implemented!");
444 }
445 req->setVirt(0, val, 1, flags, tc->pcState().pc());
446 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
447 if (fault == NoFault) {
448 miscRegs[MISCREG_PAR] =
449 (req->getPaddr() & 0xfffff000) |
450 (tc->getDTBPtr()->getAttr() );
451 DPRINTF(MiscRegs,
452 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
453 val, miscRegs[MISCREG_PAR]);
454 }
455 else {
456 // Set fault bit and FSR
457 FSR fsr = miscRegs[MISCREG_DFSR];
458 miscRegs[MISCREG_PAR] =
459 (fsr.ext << 6) |
460 (fsr.fsHigh << 5) |
461 (fsr.fsLow << 1) |
462 0x1; // F bit
463 }
464 return;
465 }
466 case MISCREG_CONTEXTIDR:
467 case MISCREG_PRRR:
468 case MISCREG_NMRR:
469 case MISCREG_DACR:
470 tc->getITBPtr()->invalidateMiscReg();
471 tc->getDTBPtr()->invalidateMiscReg();
472 break;
473
474 }
475 }
476 setMiscRegNoEffect(misc_reg, newVal);
477}
478
479}