1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43
44namespace ArmISA
45{
46
47void
48ISA::clear()
49{
50 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
51
52 memset(miscRegs, 0, sizeof(miscRegs));
53 CPSR cpsr = 0;
54 cpsr.mode = MODE_USER;
55 miscRegs[MISCREG_CPSR] = cpsr;
56 updateRegMap(cpsr);
57
58 SCTLR sctlr = 0;
59 sctlr.te = (bool)sctlr_rst.te;
60 sctlr.nmfi = (bool)sctlr_rst.nmfi;
61 sctlr.v = (bool)sctlr_rst.v;
62 sctlr.u = 1;
63 sctlr.xp = 1;
64 sctlr.rao2 = 1;
65 sctlr.rao3 = 1;
66 sctlr.rao4 = 1;
67 miscRegs[MISCREG_SCTLR] = sctlr;
68 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
69
70 /* Start with an event in the mailbox */
71 miscRegs[MISCREG_SEV_MAILBOX] = 1;
72
73 /*
74 * Implemented = '5' from "M5",
75 * Variant = 0,
76 */
77 miscRegs[MISCREG_MIDR] =
78 (0x35 << 24) | // Implementor is '5' from "M5"
79 (0 << 20) | // Variant
80 (0xf << 16) | // Architecture from CPUID scheme
81 (0xf00 << 4) | // Primary part number
82 (0 << 0) | // Revision
83 0;
84
85 // Separate Instruction and Data TLBs.
86 miscRegs[MISCREG_TLBTR] = 1;
87
88 MVFR0 mvfr0 = 0;
89 mvfr0.advSimdRegisters = 2;
90 mvfr0.singlePrecision = 2;
91 mvfr0.doublePrecision = 2;
92 mvfr0.vfpExceptionTrapping = 0;
93 mvfr0.divide = 1;
94 mvfr0.squareRoot = 1;
95 mvfr0.shortVectors = 1;
96 mvfr0.roundingModes = 1;
97 miscRegs[MISCREG_MVFR0] = mvfr0;
98
99 MVFR1 mvfr1 = 0;
100 mvfr1.flushToZero = 1;
101 mvfr1.defaultNaN = 1;
102 mvfr1.advSimdLoadStore = 1;
103 mvfr1.advSimdInteger = 1;
104 mvfr1.advSimdSinglePrecision = 1;
105 mvfr1.advSimdHalfPrecision = 1;
106 mvfr1.vfpHalfPrecision = 1;
107 miscRegs[MISCREG_MVFR1] = mvfr1;
108
109 miscRegs[MISCREG_MPIDR] = 0;
110
111 // Reset values of PRRR and NMRR are implementation dependent
112
113 miscRegs[MISCREG_PRRR] =
114 (1 << 19) | // 19
115 (0 << 18) | // 18
116 (0 << 17) | // 17
117 (1 << 16) | // 16
118 (2 << 14) | // 15:14
119 (0 << 12) | // 13:12
120 (2 << 10) | // 11:10
121 (2 << 8) | // 9:8
122 (2 << 6) | // 7:6
123 (2 << 4) | // 5:4
124 (1 << 2) | // 3:2
125 0; // 1:0
126 miscRegs[MISCREG_NMRR] =
127 (1 << 30) | // 31:30
128 (0 << 26) | // 27:26
129 (0 << 24) | // 25:24
130 (3 << 22) | // 23:22
131 (2 << 20) | // 21:20
132 (0 << 18) | // 19:18
133 (0 << 16) | // 17:16
134 (1 << 14) | // 15:14
135 (0 << 12) | // 13:12
136 (2 << 10) | // 11:10
137 (0 << 8) | // 9:8
138 (3 << 6) | // 7:6
139 (2 << 4) | // 5:4
140 (0 << 2) | // 3:2
141 0; // 1:0
142
143 miscRegs[MISCREG_CPACR] = 0;
144 miscRegs[MISCREG_FPSID] = 0x410430A0;
145 //XXX We need to initialize the rest of the state.
146}
147
148MiscReg
149ISA::readMiscRegNoEffect(int misc_reg)
150{
151 assert(misc_reg < NumMiscRegs);
152
153 int flat_idx;
154 if (misc_reg == MISCREG_SPSR)
155 flat_idx = flattenMiscIndex(misc_reg);
156 else
157 flat_idx = misc_reg;
158 MiscReg val = miscRegs[flat_idx];
159
160 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
161 misc_reg, flat_idx, val);
162 return val;
163}
164
165
166MiscReg
167ISA::readMiscReg(int misc_reg, ThreadContext *tc)
168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
171 PCState pc = tc->pcState();
172 cpsr.j = pc.jazelle() ? 1 : 0;
173 cpsr.t = pc.thumb() ? 1 : 0;
174 return cpsr;
175 }
176 if (misc_reg >= MISCREG_CP15_UNIMP_START)
177 panic("Unimplemented CP15 register %s read.\n",
178 miscRegName[misc_reg]);
179
180 switch (misc_reg) {
181 case MISCREG_CLIDR:
182 warn_once("The clidr register always reports 0 caches.\n");
183 break;
184 case MISCREG_CCSIDR:
185 warn_once("The ccsidr register isn't implemented and "
186 "always reads as 0.\n");
187 break;
188 case MISCREG_ID_PFR0:
189 warn("Returning thumbEE disabled for now since we don't support CP14"
190 "config registers and jumping to ThumbEE vectors\n");
191 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
192 case MISCREG_ID_MMFR0:
193 return 0x03; //VMSAz7
194 case MISCREG_CTR:
195 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
196 case MISCREG_ACTLR:
197 warn("Not doing anything for miscreg ACTLR\n");
198 break;
199 case MISCREG_PMCR:
200 case MISCREG_PMCCNTR:
201 case MISCREG_PMSELR:
202 warn("Not doing anyhting for read to miscreg %s\n",
203 miscRegName[misc_reg]);
204 break;
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43
44namespace ArmISA
45{
46
47void
48ISA::clear()
49{
50 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
51
52 memset(miscRegs, 0, sizeof(miscRegs));
53 CPSR cpsr = 0;
54 cpsr.mode = MODE_USER;
55 miscRegs[MISCREG_CPSR] = cpsr;
56 updateRegMap(cpsr);
57
58 SCTLR sctlr = 0;
59 sctlr.te = (bool)sctlr_rst.te;
60 sctlr.nmfi = (bool)sctlr_rst.nmfi;
61 sctlr.v = (bool)sctlr_rst.v;
62 sctlr.u = 1;
63 sctlr.xp = 1;
64 sctlr.rao2 = 1;
65 sctlr.rao3 = 1;
66 sctlr.rao4 = 1;
67 miscRegs[MISCREG_SCTLR] = sctlr;
68 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
69
70 /* Start with an event in the mailbox */
71 miscRegs[MISCREG_SEV_MAILBOX] = 1;
72
73 /*
74 * Implemented = '5' from "M5",
75 * Variant = 0,
76 */
77 miscRegs[MISCREG_MIDR] =
78 (0x35 << 24) | // Implementor is '5' from "M5"
79 (0 << 20) | // Variant
80 (0xf << 16) | // Architecture from CPUID scheme
81 (0xf00 << 4) | // Primary part number
82 (0 << 0) | // Revision
83 0;
84
85 // Separate Instruction and Data TLBs.
86 miscRegs[MISCREG_TLBTR] = 1;
87
88 MVFR0 mvfr0 = 0;
89 mvfr0.advSimdRegisters = 2;
90 mvfr0.singlePrecision = 2;
91 mvfr0.doublePrecision = 2;
92 mvfr0.vfpExceptionTrapping = 0;
93 mvfr0.divide = 1;
94 mvfr0.squareRoot = 1;
95 mvfr0.shortVectors = 1;
96 mvfr0.roundingModes = 1;
97 miscRegs[MISCREG_MVFR0] = mvfr0;
98
99 MVFR1 mvfr1 = 0;
100 mvfr1.flushToZero = 1;
101 mvfr1.defaultNaN = 1;
102 mvfr1.advSimdLoadStore = 1;
103 mvfr1.advSimdInteger = 1;
104 mvfr1.advSimdSinglePrecision = 1;
105 mvfr1.advSimdHalfPrecision = 1;
106 mvfr1.vfpHalfPrecision = 1;
107 miscRegs[MISCREG_MVFR1] = mvfr1;
108
109 miscRegs[MISCREG_MPIDR] = 0;
110
111 // Reset values of PRRR and NMRR are implementation dependent
112
113 miscRegs[MISCREG_PRRR] =
114 (1 << 19) | // 19
115 (0 << 18) | // 18
116 (0 << 17) | // 17
117 (1 << 16) | // 16
118 (2 << 14) | // 15:14
119 (0 << 12) | // 13:12
120 (2 << 10) | // 11:10
121 (2 << 8) | // 9:8
122 (2 << 6) | // 7:6
123 (2 << 4) | // 5:4
124 (1 << 2) | // 3:2
125 0; // 1:0
126 miscRegs[MISCREG_NMRR] =
127 (1 << 30) | // 31:30
128 (0 << 26) | // 27:26
129 (0 << 24) | // 25:24
130 (3 << 22) | // 23:22
131 (2 << 20) | // 21:20
132 (0 << 18) | // 19:18
133 (0 << 16) | // 17:16
134 (1 << 14) | // 15:14
135 (0 << 12) | // 13:12
136 (2 << 10) | // 11:10
137 (0 << 8) | // 9:8
138 (3 << 6) | // 7:6
139 (2 << 4) | // 5:4
140 (0 << 2) | // 3:2
141 0; // 1:0
142
143 miscRegs[MISCREG_CPACR] = 0;
144 miscRegs[MISCREG_FPSID] = 0x410430A0;
145 //XXX We need to initialize the rest of the state.
146}
147
148MiscReg
149ISA::readMiscRegNoEffect(int misc_reg)
150{
151 assert(misc_reg < NumMiscRegs);
152
153 int flat_idx;
154 if (misc_reg == MISCREG_SPSR)
155 flat_idx = flattenMiscIndex(misc_reg);
156 else
157 flat_idx = misc_reg;
158 MiscReg val = miscRegs[flat_idx];
159
160 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
161 misc_reg, flat_idx, val);
162 return val;
163}
164
165
166MiscReg
167ISA::readMiscReg(int misc_reg, ThreadContext *tc)
168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
171 PCState pc = tc->pcState();
172 cpsr.j = pc.jazelle() ? 1 : 0;
173 cpsr.t = pc.thumb() ? 1 : 0;
174 return cpsr;
175 }
176 if (misc_reg >= MISCREG_CP15_UNIMP_START)
177 panic("Unimplemented CP15 register %s read.\n",
178 miscRegName[misc_reg]);
179
180 switch (misc_reg) {
181 case MISCREG_CLIDR:
182 warn_once("The clidr register always reports 0 caches.\n");
183 break;
184 case MISCREG_CCSIDR:
185 warn_once("The ccsidr register isn't implemented and "
186 "always reads as 0.\n");
187 break;
188 case MISCREG_ID_PFR0:
189 warn("Returning thumbEE disabled for now since we don't support CP14"
190 "config registers and jumping to ThumbEE vectors\n");
191 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
192 case MISCREG_ID_MMFR0:
193 return 0x03; //VMSAz7
194 case MISCREG_CTR:
195 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
196 case MISCREG_ACTLR:
197 warn("Not doing anything for miscreg ACTLR\n");
198 break;
199 case MISCREG_PMCR:
200 case MISCREG_PMCCNTR:
201 case MISCREG_PMSELR:
202 warn("Not doing anyhting for read to miscreg %s\n",
203 miscRegName[misc_reg]);
204 break;
|
205
| 205 case MISCREG_FPSCR_QC:
206 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
207 case MISCREG_FPSCR_EXC:
208 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
|
206 }
207 return readMiscRegNoEffect(misc_reg);
208}
209
210void
211ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
212{
213 assert(misc_reg < NumMiscRegs);
214
215 int flat_idx;
216 if (misc_reg == MISCREG_SPSR)
217 flat_idx = flattenMiscIndex(misc_reg);
218 else
219 flat_idx = misc_reg;
220 miscRegs[flat_idx] = val;
221
222 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
223 flat_idx, val);
224}
225
226void
227ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
228{
229
230 MiscReg newVal = val;
231 if (misc_reg == MISCREG_CPSR) {
232 updateRegMap(val);
233
234
235 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
236 int old_mode = old_cpsr.mode;
237 CPSR cpsr = val;
238 if (old_mode != cpsr.mode) {
239 tc->getITBPtr()->invalidateMiscReg();
240 tc->getDTBPtr()->invalidateMiscReg();
241 }
242
243 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
244 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
245 PCState pc = tc->pcState();
246 pc.nextThumb(cpsr.t);
247 pc.nextJazelle(cpsr.j);
248 tc->pcState(pc);
249 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
250 misc_reg < MISCREG_CP15_END) {
251 panic("Unimplemented CP15 register %s wrote with %#x.\n",
252 miscRegName[misc_reg], val);
253 } else {
254 switch (misc_reg) {
255 case MISCREG_ITSTATE:
256 {
257 ITSTATE itstate = newVal;
258 CPSR cpsr = miscRegs[MISCREG_CPSR];
259 cpsr.it1 = itstate.bottom2;
260 cpsr.it2 = itstate.top6;
261 miscRegs[MISCREG_CPSR] = cpsr;
262 DPRINTF(MiscRegs,
263 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
264 (uint8_t)itstate, (uint32_t)cpsr);
265 }
266 break;
267 case MISCREG_CPACR:
268 {
269 CPACR newCpacr = 0;
270 CPACR valCpacr = val;
271 newCpacr.cp10 = valCpacr.cp10;
272 newCpacr.cp11 = valCpacr.cp11;
273 //XXX d32dis isn't implemented. The manual says whether or not
274 //it works is implementation defined.
275 newCpacr.asedis = valCpacr.asedis;
276 newVal = newCpacr;
277 }
278 break;
279 case MISCREG_CSSELR:
280 warn_once("The csselr register isn't implemented.\n");
281 break;
282 case MISCREG_FPSCR:
283 {
284 const uint32_t ones = (uint32_t)(-1);
285 FPSCR fpscrMask = 0;
286 fpscrMask.ioc = ones;
287 fpscrMask.dzc = ones;
288 fpscrMask.ofc = ones;
289 fpscrMask.ufc = ones;
290 fpscrMask.ixc = ones;
291 fpscrMask.idc = ones;
292 fpscrMask.len = ones;
293 fpscrMask.stride = ones;
294 fpscrMask.rMode = ones;
295 fpscrMask.fz = ones;
296 fpscrMask.dn = ones;
297 fpscrMask.ahp = ones;
298 fpscrMask.qc = ones;
299 fpscrMask.v = ones;
300 fpscrMask.c = ones;
301 fpscrMask.z = ones;
302 fpscrMask.n = ones;
303 newVal = (newVal & (uint32_t)fpscrMask) |
304 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
305 }
306 break;
| 209 }
210 return readMiscRegNoEffect(misc_reg);
211}
212
213void
214ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
215{
216 assert(misc_reg < NumMiscRegs);
217
218 int flat_idx;
219 if (misc_reg == MISCREG_SPSR)
220 flat_idx = flattenMiscIndex(misc_reg);
221 else
222 flat_idx = misc_reg;
223 miscRegs[flat_idx] = val;
224
225 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
226 flat_idx, val);
227}
228
229void
230ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
231{
232
233 MiscReg newVal = val;
234 if (misc_reg == MISCREG_CPSR) {
235 updateRegMap(val);
236
237
238 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
239 int old_mode = old_cpsr.mode;
240 CPSR cpsr = val;
241 if (old_mode != cpsr.mode) {
242 tc->getITBPtr()->invalidateMiscReg();
243 tc->getDTBPtr()->invalidateMiscReg();
244 }
245
246 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
247 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
248 PCState pc = tc->pcState();
249 pc.nextThumb(cpsr.t);
250 pc.nextJazelle(cpsr.j);
251 tc->pcState(pc);
252 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
253 misc_reg < MISCREG_CP15_END) {
254 panic("Unimplemented CP15 register %s wrote with %#x.\n",
255 miscRegName[misc_reg], val);
256 } else {
257 switch (misc_reg) {
258 case MISCREG_ITSTATE:
259 {
260 ITSTATE itstate = newVal;
261 CPSR cpsr = miscRegs[MISCREG_CPSR];
262 cpsr.it1 = itstate.bottom2;
263 cpsr.it2 = itstate.top6;
264 miscRegs[MISCREG_CPSR] = cpsr;
265 DPRINTF(MiscRegs,
266 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
267 (uint8_t)itstate, (uint32_t)cpsr);
268 }
269 break;
270 case MISCREG_CPACR:
271 {
272 CPACR newCpacr = 0;
273 CPACR valCpacr = val;
274 newCpacr.cp10 = valCpacr.cp10;
275 newCpacr.cp11 = valCpacr.cp11;
276 //XXX d32dis isn't implemented. The manual says whether or not
277 //it works is implementation defined.
278 newCpacr.asedis = valCpacr.asedis;
279 newVal = newCpacr;
280 }
281 break;
282 case MISCREG_CSSELR:
283 warn_once("The csselr register isn't implemented.\n");
284 break;
285 case MISCREG_FPSCR:
286 {
287 const uint32_t ones = (uint32_t)(-1);
288 FPSCR fpscrMask = 0;
289 fpscrMask.ioc = ones;
290 fpscrMask.dzc = ones;
291 fpscrMask.ofc = ones;
292 fpscrMask.ufc = ones;
293 fpscrMask.ixc = ones;
294 fpscrMask.idc = ones;
295 fpscrMask.len = ones;
296 fpscrMask.stride = ones;
297 fpscrMask.rMode = ones;
298 fpscrMask.fz = ones;
299 fpscrMask.dn = ones;
300 fpscrMask.ahp = ones;
301 fpscrMask.qc = ones;
302 fpscrMask.v = ones;
303 fpscrMask.c = ones;
304 fpscrMask.z = ones;
305 fpscrMask.n = ones;
306 newVal = (newVal & (uint32_t)fpscrMask) |
307 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
308 }
309 break;
|
| 310 case MISCREG_FPSCR_QC:
311 {
312 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
313 misc_reg = MISCREG_FPSCR;
314 }
315 break;
316 case MISCREG_FPSCR_EXC:
317 {
318 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
319 misc_reg = MISCREG_FPSCR;
320 }
321 break;
|
307 case MISCREG_FPEXC:
308 {
309 const uint32_t fpexcMask = 0x60000000;
310 newVal = (newVal & fpexcMask) |
311 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
312 }
313 break;
314 case MISCREG_SCTLR:
315 {
316 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
317 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
318 SCTLR new_sctlr = newVal;
319 new_sctlr.nmfi = (bool)sctlr.nmfi;
320 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
321 tc->getITBPtr()->invalidateMiscReg();
322 tc->getDTBPtr()->invalidateMiscReg();
323 return;
324 }
325 case MISCREG_TLBTR:
326 case MISCREG_MVFR0:
327 case MISCREG_MVFR1:
328 case MISCREG_MPIDR:
329 case MISCREG_FPSID:
330 return;
331 case MISCREG_TLBIALLIS:
332 case MISCREG_TLBIALL:
333 warn_once("Need to flush all TLBs in MP\n");
334 tc->getITBPtr()->flushAll();
335 tc->getDTBPtr()->flushAll();
336 return;
337 case MISCREG_ITLBIALL:
338 tc->getITBPtr()->flushAll();
339 return;
340 case MISCREG_DTLBIALL:
341 tc->getDTBPtr()->flushAll();
342 return;
343 case MISCREG_TLBIMVAIS:
344 case MISCREG_TLBIMVA:
345 warn_once("Need to flush all TLBs in MP\n");
346 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
347 bits(newVal, 7,0));
348 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
349 bits(newVal, 7,0));
350 return;
351 case MISCREG_TLBIASIDIS:
352 case MISCREG_TLBIASID:
353 warn_once("Need to flush all TLBs in MP\n");
354 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
355 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
356 return;
357 case MISCREG_TLBIMVAAIS:
358 case MISCREG_TLBIMVAA:
359 warn_once("Need to flush all TLBs in MP\n");
360 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
361 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
362 return;
363 case MISCREG_ITLBIMVA:
364 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
365 bits(newVal, 7,0));
366 return;
367 case MISCREG_DTLBIMVA:
368 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
369 bits(newVal, 7,0));
370 return;
371 case MISCREG_ITLBIASID:
372 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
373 return;
374 case MISCREG_DTLBIASID:
375 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
376 return;
377 case MISCREG_ACTLR:
378 warn("Not doing anything for write of miscreg ACTLR\n");
379 break;
380 case MISCREG_PMCR:
381 case MISCREG_PMCCNTR:
382 case MISCREG_PMSELR:
383 warn("Not doing anything for write to miscreg %s\n",
384 miscRegName[misc_reg]);
385 break;
386 case MISCREG_V2PCWPR:
387 case MISCREG_V2PCWPW:
388 case MISCREG_V2PCWUR:
389 case MISCREG_V2PCWUW:
390 case MISCREG_V2POWPR:
391 case MISCREG_V2POWPW:
392 case MISCREG_V2POWUR:
393 case MISCREG_V2POWUW:
394 {
395 RequestPtr req = new Request;
396 unsigned flags;
397 BaseTLB::Mode mode;
398 Fault fault;
399 switch(misc_reg) {
400 case MISCREG_V2PCWPR:
401 flags = TLB::MustBeOne;
402 mode = BaseTLB::Read;
403 break;
404 case MISCREG_V2PCWPW:
405 flags = TLB::MustBeOne;
406 mode = BaseTLB::Write;
407 break;
408 case MISCREG_V2PCWUR:
409 flags = TLB::MustBeOne | TLB::UserMode;
410 mode = BaseTLB::Read;
411 break;
412 case MISCREG_V2PCWUW:
413 flags = TLB::MustBeOne | TLB::UserMode;
414 mode = BaseTLB::Write;
415 break;
416 default:
417 panic("Security Extensions not implemented!");
418 }
419 req->setVirt(0, val, 1, flags, tc->pcState().pc());
420 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
421 if (fault == NoFault) {
422 miscRegs[MISCREG_PAR] =
423 (req->getPaddr() & 0xfffff000) |
424 (tc->getDTBPtr()->getAttr() );
425 DPRINTF(MiscRegs,
426 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
427 val, miscRegs[MISCREG_PAR]);
428 }
429 else {
430 // Set fault bit and FSR
431 FSR fsr = miscRegs[MISCREG_DFSR];
432 miscRegs[MISCREG_PAR] =
433 (fsr.ext << 6) |
434 (fsr.fsHigh << 5) |
435 (fsr.fsLow << 1) |
436 0x1; // F bit
437 }
438 return;
439 }
440 case MISCREG_CONTEXTIDR:
441 case MISCREG_PRRR:
442 case MISCREG_NMRR:
443 case MISCREG_DACR:
444 tc->getITBPtr()->invalidateMiscReg();
445 tc->getDTBPtr()->invalidateMiscReg();
446 break;
447
448 }
449 }
450 setMiscRegNoEffect(misc_reg, newVal);
451}
452
453}
| 322 case MISCREG_FPEXC:
323 {
324 const uint32_t fpexcMask = 0x60000000;
325 newVal = (newVal & fpexcMask) |
326 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
327 }
328 break;
329 case MISCREG_SCTLR:
330 {
331 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
332 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
333 SCTLR new_sctlr = newVal;
334 new_sctlr.nmfi = (bool)sctlr.nmfi;
335 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
336 tc->getITBPtr()->invalidateMiscReg();
337 tc->getDTBPtr()->invalidateMiscReg();
338 return;
339 }
340 case MISCREG_TLBTR:
341 case MISCREG_MVFR0:
342 case MISCREG_MVFR1:
343 case MISCREG_MPIDR:
344 case MISCREG_FPSID:
345 return;
346 case MISCREG_TLBIALLIS:
347 case MISCREG_TLBIALL:
348 warn_once("Need to flush all TLBs in MP\n");
349 tc->getITBPtr()->flushAll();
350 tc->getDTBPtr()->flushAll();
351 return;
352 case MISCREG_ITLBIALL:
353 tc->getITBPtr()->flushAll();
354 return;
355 case MISCREG_DTLBIALL:
356 tc->getDTBPtr()->flushAll();
357 return;
358 case MISCREG_TLBIMVAIS:
359 case MISCREG_TLBIMVA:
360 warn_once("Need to flush all TLBs in MP\n");
361 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
362 bits(newVal, 7,0));
363 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
364 bits(newVal, 7,0));
365 return;
366 case MISCREG_TLBIASIDIS:
367 case MISCREG_TLBIASID:
368 warn_once("Need to flush all TLBs in MP\n");
369 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
370 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
371 return;
372 case MISCREG_TLBIMVAAIS:
373 case MISCREG_TLBIMVAA:
374 warn_once("Need to flush all TLBs in MP\n");
375 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
376 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
377 return;
378 case MISCREG_ITLBIMVA:
379 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
380 bits(newVal, 7,0));
381 return;
382 case MISCREG_DTLBIMVA:
383 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
384 bits(newVal, 7,0));
385 return;
386 case MISCREG_ITLBIASID:
387 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
388 return;
389 case MISCREG_DTLBIASID:
390 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
391 return;
392 case MISCREG_ACTLR:
393 warn("Not doing anything for write of miscreg ACTLR\n");
394 break;
395 case MISCREG_PMCR:
396 case MISCREG_PMCCNTR:
397 case MISCREG_PMSELR:
398 warn("Not doing anything for write to miscreg %s\n",
399 miscRegName[misc_reg]);
400 break;
401 case MISCREG_V2PCWPR:
402 case MISCREG_V2PCWPW:
403 case MISCREG_V2PCWUR:
404 case MISCREG_V2PCWUW:
405 case MISCREG_V2POWPR:
406 case MISCREG_V2POWPW:
407 case MISCREG_V2POWUR:
408 case MISCREG_V2POWUW:
409 {
410 RequestPtr req = new Request;
411 unsigned flags;
412 BaseTLB::Mode mode;
413 Fault fault;
414 switch(misc_reg) {
415 case MISCREG_V2PCWPR:
416 flags = TLB::MustBeOne;
417 mode = BaseTLB::Read;
418 break;
419 case MISCREG_V2PCWPW:
420 flags = TLB::MustBeOne;
421 mode = BaseTLB::Write;
422 break;
423 case MISCREG_V2PCWUR:
424 flags = TLB::MustBeOne | TLB::UserMode;
425 mode = BaseTLB::Read;
426 break;
427 case MISCREG_V2PCWUW:
428 flags = TLB::MustBeOne | TLB::UserMode;
429 mode = BaseTLB::Write;
430 break;
431 default:
432 panic("Security Extensions not implemented!");
433 }
434 req->setVirt(0, val, 1, flags, tc->pcState().pc());
435 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
436 if (fault == NoFault) {
437 miscRegs[MISCREG_PAR] =
438 (req->getPaddr() & 0xfffff000) |
439 (tc->getDTBPtr()->getAttr() );
440 DPRINTF(MiscRegs,
441 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
442 val, miscRegs[MISCREG_PAR]);
443 }
444 else {
445 // Set fault bit and FSR
446 FSR fsr = miscRegs[MISCREG_DFSR];
447 miscRegs[MISCREG_PAR] =
448 (fsr.ext << 6) |
449 (fsr.fsHigh << 5) |
450 (fsr.fsLow << 1) |
451 0x1; // F bit
452 }
453 return;
454 }
455 case MISCREG_CONTEXTIDR:
456 case MISCREG_PRRR:
457 case MISCREG_NMRR:
458 case MISCREG_DACR:
459 tc->getITBPtr()->invalidateMiscReg();
460 tc->getDTBPtr()->invalidateMiscReg();
461 break;
462
463 }
464 }
465 setMiscRegNoEffect(misc_reg, newVal);
466}
467
468}
|