1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43namespace ArmISA
44{
45
46void
47ISA::clear()
48{
49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
50
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 updateRegMap(cpsr);
56
57 SCTLR sctlr = 0;
58 sctlr.te = (bool)sctlr_rst.te;
59 sctlr.nmfi = (bool)sctlr_rst.nmfi;
60 sctlr.v = (bool)sctlr_rst.v;
61 sctlr.u = 1;
62 sctlr.xp = 1;
63 sctlr.rao2 = 1;
64 sctlr.rao3 = 1;
65 sctlr.rao4 = 1;
66 miscRegs[MISCREG_SCTLR] = sctlr;
67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
68
69 /* Start with an event in the mailbox */
70 miscRegs[MISCREG_SEV_MAILBOX] = 1;
71
72 /*
73 * Implemented = '5' from "M5",
74 * Variant = 0,
75 */
76 miscRegs[MISCREG_MIDR] =
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43namespace ArmISA
44{
45
46void
47ISA::clear()
48{
49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
50
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 updateRegMap(cpsr);
56
57 SCTLR sctlr = 0;
58 sctlr.te = (bool)sctlr_rst.te;
59 sctlr.nmfi = (bool)sctlr_rst.nmfi;
60 sctlr.v = (bool)sctlr_rst.v;
61 sctlr.u = 1;
62 sctlr.xp = 1;
63 sctlr.rao2 = 1;
64 sctlr.rao3 = 1;
65 sctlr.rao4 = 1;
66 miscRegs[MISCREG_SCTLR] = sctlr;
67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
68
69 /* Start with an event in the mailbox */
70 miscRegs[MISCREG_SEV_MAILBOX] = 1;
71
72 /*
73 * Implemented = '5' from "M5",
74 * Variant = 0,
75 */
76 miscRegs[MISCREG_MIDR] =
|
82 0;
83
84 // Separate Instruction and Data TLBs.
85 miscRegs[MISCREG_TLBTR] = 1;
86
87 MVFR0 mvfr0 = 0;
88 mvfr0.advSimdRegisters = 2;
89 mvfr0.singlePrecision = 2;
90 mvfr0.doublePrecision = 2;
91 mvfr0.vfpExceptionTrapping = 0;
92 mvfr0.divide = 1;
93 mvfr0.squareRoot = 1;
94 mvfr0.shortVectors = 1;
95 mvfr0.roundingModes = 1;
96 miscRegs[MISCREG_MVFR0] = mvfr0;
97
98 MVFR1 mvfr1 = 0;
99 mvfr1.flushToZero = 1;
100 mvfr1.defaultNaN = 1;
101 mvfr1.advSimdLoadStore = 1;
102 mvfr1.advSimdInteger = 1;
103 mvfr1.advSimdSinglePrecision = 1;
104 mvfr1.advSimdHalfPrecision = 1;
105 mvfr1.vfpHalfPrecision = 1;
106 miscRegs[MISCREG_MVFR1] = mvfr1;
107
108 miscRegs[MISCREG_MPIDR] = 0;
109
110 // Reset values of PRRR and NMRR are implementation dependent
111
112 miscRegs[MISCREG_PRRR] =
113 (1 << 19) | // 19
114 (0 << 18) | // 18
115 (0 << 17) | // 17
116 (1 << 16) | // 16
117 (2 << 14) | // 15:14
118 (0 << 12) | // 13:12
119 (2 << 10) | // 11:10
120 (2 << 8) | // 9:8
121 (2 << 6) | // 7:6
122 (2 << 4) | // 5:4
123 (1 << 2) | // 3:2
124 0; // 1:0
125 miscRegs[MISCREG_NMRR] =
126 (1 << 30) | // 31:30
127 (0 << 26) | // 27:26
128 (0 << 24) | // 25:24
129 (3 << 22) | // 23:22
130 (2 << 20) | // 21:20
131 (0 << 18) | // 19:18
132 (0 << 16) | // 17:16
133 (1 << 14) | // 15:14
134 (0 << 12) | // 13:12
135 (2 << 10) | // 11:10
136 (0 << 8) | // 9:8
137 (3 << 6) | // 7:6
138 (2 << 4) | // 5:4
139 (0 << 2) | // 3:2
140 0; // 1:0
141
142 miscRegs[MISCREG_CPACR] = 0;
143 miscRegs[MISCREG_FPSID] = 0x410430A0;
144 //XXX We need to initialize the rest of the state.
145}
146
147MiscReg
148ISA::readMiscRegNoEffect(int misc_reg)
149{
150 assert(misc_reg < NumMiscRegs);
151
152 int flat_idx;
153 if (misc_reg == MISCREG_SPSR)
154 flat_idx = flattenMiscIndex(misc_reg);
155 else
156 flat_idx = misc_reg;
157 MiscReg val = miscRegs[flat_idx];
158
159 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
160 misc_reg, flat_idx, val);
161 return val;
162}
163
164
165MiscReg
166ISA::readMiscReg(int misc_reg, ThreadContext *tc)
167{
168 if (misc_reg == MISCREG_CPSR) {
169 CPSR cpsr = miscRegs[misc_reg];
170 Addr pc = tc->readPC();
171 if (pc & (ULL(1) << PcJBitShift))
172 cpsr.j = 1;
173 else
174 cpsr.j = 0;
175 if (pc & (ULL(1) << PcTBitShift))
176 cpsr.t = 1;
177 else
178 cpsr.t = 0;
179 return cpsr;
180 }
181 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
182 misc_reg < MISCREG_CP15_END) {
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
185 }
186 switch (misc_reg) {
187 case MISCREG_CLIDR:
188 warn("The clidr register always reports 0 caches.\n");
189 break;
190 case MISCREG_CCSIDR:
191 warn("The ccsidr register isn't implemented and "
192 "always reads as 0.\n");
193 break;
194 case MISCREG_ID_PFR0:
195 warn("Returning thumbEE disabled for now since we don't support CP14"
196 "config registers and jumping to ThumbEE vectors\n");
197 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
198 case MISCREG_ID_MMFR0:
199 return 0x03; //VMSAz7
200 case MISCREG_CTR:
201 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
202 case MISCREG_ACTLR:
203 warn("Not doing anything for miscreg ACTLR\n");
204 break;
205 case MISCREG_PMCR:
206 case MISCREG_PMCCNTR:
207 case MISCREG_PMSELR:
208 warn("Not doing anyhting for read to miscreg %s\n",
209 miscRegName[misc_reg]);
210 break;
211
212 }
213 return readMiscRegNoEffect(misc_reg);
214}
215
216void
217ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
218{
219 assert(misc_reg < NumMiscRegs);
220
221 int flat_idx;
222 if (misc_reg == MISCREG_SPSR)
223 flat_idx = flattenMiscIndex(misc_reg);
224 else
225 flat_idx = misc_reg;
226 miscRegs[flat_idx] = val;
227
228 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
229 flat_idx, val);
230}
231
232void
233ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
234{
235 MiscReg newVal = val;
236 if (misc_reg == MISCREG_CPSR) {
237 updateRegMap(val);
238 CPSR cpsr = val;
239 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
240 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
241 Addr npc = tc->readNextPC() & ~PcModeMask;
242 if (cpsr.j)
243 npc = npc | (ULL(1) << PcJBitShift);
244 if (cpsr.t)
245 npc = npc | (ULL(1) << PcTBitShift);
246
247 tc->setNextPC(npc);
248 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
249 misc_reg < MISCREG_CP15_END) {
250 panic("Unimplemented CP15 register %s wrote with %#x.\n",
251 miscRegName[misc_reg], val);
252 } else {
253 switch (misc_reg) {
254 case MISCREG_ITSTATE:
255 {
256 ITSTATE itstate = newVal;
257 CPSR cpsr = miscRegs[MISCREG_CPSR];
258 cpsr.it1 = itstate.bottom2;
259 cpsr.it2 = itstate.top6;
260 miscRegs[MISCREG_CPSR] = cpsr;
261 DPRINTF(MiscRegs,
262 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
263 (uint8_t)itstate, (uint32_t)cpsr);
264 }
265 break;
266 case MISCREG_CPACR:
267 {
268 CPACR newCpacr = 0;
269 CPACR valCpacr = val;
270 newCpacr.cp10 = valCpacr.cp10;
271 newCpacr.cp11 = valCpacr.cp11;
272 //XXX d32dis isn't implemented. The manual says whether or not
273 //it works is implementation defined.
274 newCpacr.asedis = valCpacr.asedis;
275 newVal = newCpacr;
276 }
277 break;
278 case MISCREG_CSSELR:
279 warn("The csselr register isn't implemented.\n");
280 break;
281 case MISCREG_FPSCR:
282 {
283 const uint32_t ones = (uint32_t)(-1);
284 FPSCR fpscrMask = 0;
285 fpscrMask.ioc = ones;
286 fpscrMask.dzc = ones;
287 fpscrMask.ofc = ones;
288 fpscrMask.ufc = ones;
289 fpscrMask.ixc = ones;
290 fpscrMask.idc = ones;
291 fpscrMask.len = ones;
292 fpscrMask.stride = ones;
293 fpscrMask.rMode = ones;
294 fpscrMask.fz = ones;
295 fpscrMask.dn = ones;
296 fpscrMask.ahp = ones;
297 fpscrMask.qc = ones;
298 fpscrMask.v = ones;
299 fpscrMask.c = ones;
300 fpscrMask.z = ones;
301 fpscrMask.n = ones;
302 newVal = (newVal & (uint32_t)fpscrMask) |
303 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
304 }
305 break;
306 case MISCREG_FPEXC:
307 {
308 const uint32_t fpexcMask = 0x60000000;
309 newVal = (newVal & fpexcMask) |
310 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
311 }
312 break;
313 case MISCREG_SCTLR:
314 {
315 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
316 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
317 SCTLR new_sctlr = newVal;
318 new_sctlr.nmfi = (bool)sctlr.nmfi;
319 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
320 return;
321 }
322 case MISCREG_TLBTR:
323 case MISCREG_MVFR0:
324 case MISCREG_MVFR1:
325 case MISCREG_MPIDR:
326 case MISCREG_FPSID:
327 return;
328 case MISCREG_TLBIALLIS:
329 case MISCREG_TLBIALL:
330 warn("Need to flush all TLBs in MP\n");
331 tc->getITBPtr()->flushAll();
332 tc->getDTBPtr()->flushAll();
333 return;
334 case MISCREG_ITLBIALL:
335 tc->getITBPtr()->flushAll();
336 return;
337 case MISCREG_DTLBIALL:
338 tc->getDTBPtr()->flushAll();
339 return;
340 case MISCREG_TLBIMVAIS:
341 case MISCREG_TLBIMVA:
342 warn("Need to flush all TLBs in MP\n");
343 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
344 bits(newVal, 7,0));
345 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
346 bits(newVal, 7,0));
347 return;
348 case MISCREG_TLBIASIDIS:
349 case MISCREG_TLBIASID:
350 warn("Need to flush all TLBs in MP\n");
351 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
352 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
353 return;
354 case MISCREG_TLBIMVAAIS:
355 case MISCREG_TLBIMVAA:
356 warn("Need to flush all TLBs in MP\n");
357 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
358 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
359 return;
360 case MISCREG_ITLBIMVA:
361 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
362 bits(newVal, 7,0));
363 return;
364 case MISCREG_DTLBIMVA:
365 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
366 bits(newVal, 7,0));
367 return;
368 case MISCREG_ITLBIASID:
369 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
370 return;
371 case MISCREG_DTLBIASID:
372 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
373 return;
374 case MISCREG_ACTLR:
375 warn("Not doing anything for write of miscreg ACTLR\n");
376 break;
377 case MISCREG_PMCR:
378 case MISCREG_PMCCNTR:
379 case MISCREG_PMSELR:
380 warn("Not doing anything for write to miscreg %s\n",
381 miscRegName[misc_reg]);
382 break;
383 case MISCREG_V2PCWPR:
384 case MISCREG_V2PCWPW:
385 case MISCREG_V2PCWUR:
386 case MISCREG_V2PCWUW:
387 case MISCREG_V2POWPR:
388 case MISCREG_V2POWPW:
389 case MISCREG_V2POWUR:
390 case MISCREG_V2POWUW:
391 {
392 RequestPtr req = new Request;
393 unsigned flags;
394 BaseTLB::Mode mode;
395 Fault fault;
396 switch(misc_reg) {
397 case MISCREG_V2PCWPR:
398 flags = TLB::MustBeOne;
399 mode = BaseTLB::Read;
400 break;
401 case MISCREG_V2PCWPW:
402 flags = TLB::MustBeOne;
403 mode = BaseTLB::Write;
404 break;
405 case MISCREG_V2PCWUR:
406 flags = TLB::MustBeOne | TLB::UserMode;
407 mode = BaseTLB::Read;
408 break;
409 case MISCREG_V2PCWUW:
410 flags = TLB::MustBeOne | TLB::UserMode;
411 mode = BaseTLB::Write;
412 break;
413 default:
414 panic("Security Extensions not implemented!");
415 }
416 req->setVirt(0, val, 1, flags, tc->readPC());
417 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
418 if (fault == NoFault) {
419 miscRegs[MISCREG_PAR] =
420 (req->getPaddr() & 0xfffff000) |
421 (tc->getDTBPtr()->getAttr() );
422 DPRINTF(MiscRegs,
423 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
424 val, miscRegs[MISCREG_PAR]);
425 }
426 else {
427 // Set fault bit and FSR
428 FSR fsr = miscRegs[MISCREG_DFSR];
429 miscRegs[MISCREG_PAR] =
430 (fsr.ext << 6) |
431 (fsr.fsHigh << 5) |
432 (fsr.fsLow << 1) |
433 0x1; // F bit
434 }
435 return;
436 }
437 }
438 }
439 setMiscRegNoEffect(misc_reg, newVal);
440}
441
442}
| 82 0;
83
84 // Separate Instruction and Data TLBs.
85 miscRegs[MISCREG_TLBTR] = 1;
86
87 MVFR0 mvfr0 = 0;
88 mvfr0.advSimdRegisters = 2;
89 mvfr0.singlePrecision = 2;
90 mvfr0.doublePrecision = 2;
91 mvfr0.vfpExceptionTrapping = 0;
92 mvfr0.divide = 1;
93 mvfr0.squareRoot = 1;
94 mvfr0.shortVectors = 1;
95 mvfr0.roundingModes = 1;
96 miscRegs[MISCREG_MVFR0] = mvfr0;
97
98 MVFR1 mvfr1 = 0;
99 mvfr1.flushToZero = 1;
100 mvfr1.defaultNaN = 1;
101 mvfr1.advSimdLoadStore = 1;
102 mvfr1.advSimdInteger = 1;
103 mvfr1.advSimdSinglePrecision = 1;
104 mvfr1.advSimdHalfPrecision = 1;
105 mvfr1.vfpHalfPrecision = 1;
106 miscRegs[MISCREG_MVFR1] = mvfr1;
107
108 miscRegs[MISCREG_MPIDR] = 0;
109
110 // Reset values of PRRR and NMRR are implementation dependent
111
112 miscRegs[MISCREG_PRRR] =
113 (1 << 19) | // 19
114 (0 << 18) | // 18
115 (0 << 17) | // 17
116 (1 << 16) | // 16
117 (2 << 14) | // 15:14
118 (0 << 12) | // 13:12
119 (2 << 10) | // 11:10
120 (2 << 8) | // 9:8
121 (2 << 6) | // 7:6
122 (2 << 4) | // 5:4
123 (1 << 2) | // 3:2
124 0; // 1:0
125 miscRegs[MISCREG_NMRR] =
126 (1 << 30) | // 31:30
127 (0 << 26) | // 27:26
128 (0 << 24) | // 25:24
129 (3 << 22) | // 23:22
130 (2 << 20) | // 21:20
131 (0 << 18) | // 19:18
132 (0 << 16) | // 17:16
133 (1 << 14) | // 15:14
134 (0 << 12) | // 13:12
135 (2 << 10) | // 11:10
136 (0 << 8) | // 9:8
137 (3 << 6) | // 7:6
138 (2 << 4) | // 5:4
139 (0 << 2) | // 3:2
140 0; // 1:0
141
142 miscRegs[MISCREG_CPACR] = 0;
143 miscRegs[MISCREG_FPSID] = 0x410430A0;
144 //XXX We need to initialize the rest of the state.
145}
146
147MiscReg
148ISA::readMiscRegNoEffect(int misc_reg)
149{
150 assert(misc_reg < NumMiscRegs);
151
152 int flat_idx;
153 if (misc_reg == MISCREG_SPSR)
154 flat_idx = flattenMiscIndex(misc_reg);
155 else
156 flat_idx = misc_reg;
157 MiscReg val = miscRegs[flat_idx];
158
159 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
160 misc_reg, flat_idx, val);
161 return val;
162}
163
164
165MiscReg
166ISA::readMiscReg(int misc_reg, ThreadContext *tc)
167{
168 if (misc_reg == MISCREG_CPSR) {
169 CPSR cpsr = miscRegs[misc_reg];
170 Addr pc = tc->readPC();
171 if (pc & (ULL(1) << PcJBitShift))
172 cpsr.j = 1;
173 else
174 cpsr.j = 0;
175 if (pc & (ULL(1) << PcTBitShift))
176 cpsr.t = 1;
177 else
178 cpsr.t = 0;
179 return cpsr;
180 }
181 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
182 misc_reg < MISCREG_CP15_END) {
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
185 }
186 switch (misc_reg) {
187 case MISCREG_CLIDR:
188 warn("The clidr register always reports 0 caches.\n");
189 break;
190 case MISCREG_CCSIDR:
191 warn("The ccsidr register isn't implemented and "
192 "always reads as 0.\n");
193 break;
194 case MISCREG_ID_PFR0:
195 warn("Returning thumbEE disabled for now since we don't support CP14"
196 "config registers and jumping to ThumbEE vectors\n");
197 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
198 case MISCREG_ID_MMFR0:
199 return 0x03; //VMSAz7
200 case MISCREG_CTR:
201 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
202 case MISCREG_ACTLR:
203 warn("Not doing anything for miscreg ACTLR\n");
204 break;
205 case MISCREG_PMCR:
206 case MISCREG_PMCCNTR:
207 case MISCREG_PMSELR:
208 warn("Not doing anyhting for read to miscreg %s\n",
209 miscRegName[misc_reg]);
210 break;
211
212 }
213 return readMiscRegNoEffect(misc_reg);
214}
215
216void
217ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
218{
219 assert(misc_reg < NumMiscRegs);
220
221 int flat_idx;
222 if (misc_reg == MISCREG_SPSR)
223 flat_idx = flattenMiscIndex(misc_reg);
224 else
225 flat_idx = misc_reg;
226 miscRegs[flat_idx] = val;
227
228 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
229 flat_idx, val);
230}
231
232void
233ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
234{
235 MiscReg newVal = val;
236 if (misc_reg == MISCREG_CPSR) {
237 updateRegMap(val);
238 CPSR cpsr = val;
239 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
240 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
241 Addr npc = tc->readNextPC() & ~PcModeMask;
242 if (cpsr.j)
243 npc = npc | (ULL(1) << PcJBitShift);
244 if (cpsr.t)
245 npc = npc | (ULL(1) << PcTBitShift);
246
247 tc->setNextPC(npc);
248 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
249 misc_reg < MISCREG_CP15_END) {
250 panic("Unimplemented CP15 register %s wrote with %#x.\n",
251 miscRegName[misc_reg], val);
252 } else {
253 switch (misc_reg) {
254 case MISCREG_ITSTATE:
255 {
256 ITSTATE itstate = newVal;
257 CPSR cpsr = miscRegs[MISCREG_CPSR];
258 cpsr.it1 = itstate.bottom2;
259 cpsr.it2 = itstate.top6;
260 miscRegs[MISCREG_CPSR] = cpsr;
261 DPRINTF(MiscRegs,
262 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
263 (uint8_t)itstate, (uint32_t)cpsr);
264 }
265 break;
266 case MISCREG_CPACR:
267 {
268 CPACR newCpacr = 0;
269 CPACR valCpacr = val;
270 newCpacr.cp10 = valCpacr.cp10;
271 newCpacr.cp11 = valCpacr.cp11;
272 //XXX d32dis isn't implemented. The manual says whether or not
273 //it works is implementation defined.
274 newCpacr.asedis = valCpacr.asedis;
275 newVal = newCpacr;
276 }
277 break;
278 case MISCREG_CSSELR:
279 warn("The csselr register isn't implemented.\n");
280 break;
281 case MISCREG_FPSCR:
282 {
283 const uint32_t ones = (uint32_t)(-1);
284 FPSCR fpscrMask = 0;
285 fpscrMask.ioc = ones;
286 fpscrMask.dzc = ones;
287 fpscrMask.ofc = ones;
288 fpscrMask.ufc = ones;
289 fpscrMask.ixc = ones;
290 fpscrMask.idc = ones;
291 fpscrMask.len = ones;
292 fpscrMask.stride = ones;
293 fpscrMask.rMode = ones;
294 fpscrMask.fz = ones;
295 fpscrMask.dn = ones;
296 fpscrMask.ahp = ones;
297 fpscrMask.qc = ones;
298 fpscrMask.v = ones;
299 fpscrMask.c = ones;
300 fpscrMask.z = ones;
301 fpscrMask.n = ones;
302 newVal = (newVal & (uint32_t)fpscrMask) |
303 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
304 }
305 break;
306 case MISCREG_FPEXC:
307 {
308 const uint32_t fpexcMask = 0x60000000;
309 newVal = (newVal & fpexcMask) |
310 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
311 }
312 break;
313 case MISCREG_SCTLR:
314 {
315 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
316 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
317 SCTLR new_sctlr = newVal;
318 new_sctlr.nmfi = (bool)sctlr.nmfi;
319 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
320 return;
321 }
322 case MISCREG_TLBTR:
323 case MISCREG_MVFR0:
324 case MISCREG_MVFR1:
325 case MISCREG_MPIDR:
326 case MISCREG_FPSID:
327 return;
328 case MISCREG_TLBIALLIS:
329 case MISCREG_TLBIALL:
330 warn("Need to flush all TLBs in MP\n");
331 tc->getITBPtr()->flushAll();
332 tc->getDTBPtr()->flushAll();
333 return;
334 case MISCREG_ITLBIALL:
335 tc->getITBPtr()->flushAll();
336 return;
337 case MISCREG_DTLBIALL:
338 tc->getDTBPtr()->flushAll();
339 return;
340 case MISCREG_TLBIMVAIS:
341 case MISCREG_TLBIMVA:
342 warn("Need to flush all TLBs in MP\n");
343 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
344 bits(newVal, 7,0));
345 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
346 bits(newVal, 7,0));
347 return;
348 case MISCREG_TLBIASIDIS:
349 case MISCREG_TLBIASID:
350 warn("Need to flush all TLBs in MP\n");
351 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
352 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
353 return;
354 case MISCREG_TLBIMVAAIS:
355 case MISCREG_TLBIMVAA:
356 warn("Need to flush all TLBs in MP\n");
357 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
358 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
359 return;
360 case MISCREG_ITLBIMVA:
361 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
362 bits(newVal, 7,0));
363 return;
364 case MISCREG_DTLBIMVA:
365 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
366 bits(newVal, 7,0));
367 return;
368 case MISCREG_ITLBIASID:
369 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
370 return;
371 case MISCREG_DTLBIASID:
372 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
373 return;
374 case MISCREG_ACTLR:
375 warn("Not doing anything for write of miscreg ACTLR\n");
376 break;
377 case MISCREG_PMCR:
378 case MISCREG_PMCCNTR:
379 case MISCREG_PMSELR:
380 warn("Not doing anything for write to miscreg %s\n",
381 miscRegName[misc_reg]);
382 break;
383 case MISCREG_V2PCWPR:
384 case MISCREG_V2PCWPW:
385 case MISCREG_V2PCWUR:
386 case MISCREG_V2PCWUW:
387 case MISCREG_V2POWPR:
388 case MISCREG_V2POWPW:
389 case MISCREG_V2POWUR:
390 case MISCREG_V2POWUW:
391 {
392 RequestPtr req = new Request;
393 unsigned flags;
394 BaseTLB::Mode mode;
395 Fault fault;
396 switch(misc_reg) {
397 case MISCREG_V2PCWPR:
398 flags = TLB::MustBeOne;
399 mode = BaseTLB::Read;
400 break;
401 case MISCREG_V2PCWPW:
402 flags = TLB::MustBeOne;
403 mode = BaseTLB::Write;
404 break;
405 case MISCREG_V2PCWUR:
406 flags = TLB::MustBeOne | TLB::UserMode;
407 mode = BaseTLB::Read;
408 break;
409 case MISCREG_V2PCWUW:
410 flags = TLB::MustBeOne | TLB::UserMode;
411 mode = BaseTLB::Write;
412 break;
413 default:
414 panic("Security Extensions not implemented!");
415 }
416 req->setVirt(0, val, 1, flags, tc->readPC());
417 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
418 if (fault == NoFault) {
419 miscRegs[MISCREG_PAR] =
420 (req->getPaddr() & 0xfffff000) |
421 (tc->getDTBPtr()->getAttr() );
422 DPRINTF(MiscRegs,
423 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
424 val, miscRegs[MISCREG_PAR]);
425 }
426 else {
427 // Set fault bit and FSR
428 FSR fsr = miscRegs[MISCREG_DFSR];
429 miscRegs[MISCREG_PAR] =
430 (fsr.ext << 6) |
431 (fsr.fsHigh << 5) |
432 (fsr.fsLow << 1) |
433 0x1; // F bit
434 }
435 return;
436 }
437 }
438 }
439 setMiscRegNoEffect(misc_reg, newVal);
440}
441
442}
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