1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43namespace ArmISA
44{
45
46void
47ISA::clear()
48{
49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
50
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 updateRegMap(cpsr);
56
57 SCTLR sctlr = 0;
58 sctlr.nmfi = (bool)sctlr_rst.nmfi;
59 sctlr.v = (bool)sctlr_rst.v;
60 sctlr.u = 1;
61 sctlr.xp = 1;
62 sctlr.rao2 = 1;
63 sctlr.rao3 = 1;
64 sctlr.rao4 = 1;
65 miscRegs[MISCREG_SCTLR] = sctlr;
66 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
67
68
69 /*
70 * Technically this should be 0, but we don't support those
71 * settings.
72 */
73 CPACR cpacr = 0;
74 // Enable CP 10, 11
75 cpacr.cp10 = 0x3;
76 cpacr.cp11 = 0x3;
77 miscRegs[MISCREG_CPACR] = cpacr;
78
79 /* Start with an event in the mailbox */
80 miscRegs[MISCREG_SEV_MAILBOX] = 1;
81
82 /*
83 * Implemented = '5' from "M5",
84 * Variant = 0,
85 */
86 miscRegs[MISCREG_MIDR] =
87 (0x35 << 24) | //Implementor is '5' from "M5"
88 (0 << 20) | //Variant
89 (0xf << 16) | //Architecture from CPUID scheme
90 (0 << 4) | //Primary part number
91 (0 << 0) | //Revision
92 0;
93
94 // Separate Instruction and Data TLBs.
95 miscRegs[MISCREG_TLBTR] = 1;
96
97 MVFR0 mvfr0 = 0;
98 mvfr0.advSimdRegisters = 2;
99 mvfr0.singlePrecision = 2;
100 mvfr0.doublePrecision = 2;
101 mvfr0.vfpExceptionTrapping = 0;
102 mvfr0.divide = 1;
103 mvfr0.squareRoot = 1;
104 mvfr0.shortVectors = 1;
105 mvfr0.roundingModes = 1;
106 miscRegs[MISCREG_MVFR0] = mvfr0;
107
108 MVFR1 mvfr1 = 0;
109 mvfr1.flushToZero = 1;
110 mvfr1.defaultNaN = 1;
111 mvfr1.advSimdLoadStore = 1;
112 mvfr1.advSimdInteger = 1;
113 mvfr1.advSimdSinglePrecision = 1;
114 mvfr1.advSimdHalfPrecision = 1;
115 mvfr1.vfpHalfPrecision = 1;
116 miscRegs[MISCREG_MVFR1] = mvfr1;
117
118 miscRegs[MISCREG_MPIDR] = 0;
119
120 // Reset values of PRRR and NMRR are implementation dependent
121
122 miscRegs[MISCREG_PRRR] =
123 (1 << 19) | // 19
124 (0 << 18) | // 18
125 (0 << 17) | // 17
126 (1 << 16) | // 16
127 (2 << 14) | // 15:14
128 (0 << 12) | // 13:12
129 (2 << 10) | // 11:10
130 (2 << 8) | // 9:8
131 (2 << 6) | // 7:6
132 (2 << 4) | // 5:4
133 (1 << 2) | // 3:2
134 0; // 1:0
135 miscRegs[MISCREG_NMRR] =
136 (1 << 30) | // 31:30
137 (0 << 26) | // 27:26
138 (0 << 24) | // 25:24
139 (3 << 22) | // 23:22
140 (2 << 20) | // 21:20
141 (0 << 18) | // 19:18
142 (0 << 16) | // 17:16
143 (1 << 14) | // 15:14
144 (0 << 12) | // 13:12
145 (2 << 10) | // 11:10
146 (0 << 8) | // 9:8
147 (3 << 6) | // 7:6
148 (2 << 4) | // 5:4
149 (0 << 2) | // 3:2
150 0; // 1:0
151
152 //XXX We need to initialize the rest of the state.
153}
154
155MiscReg
156ISA::readMiscRegNoEffect(int misc_reg)
157{
158 assert(misc_reg < NumMiscRegs);
159 if (misc_reg == MISCREG_SPSR) {
160 CPSR cpsr = miscRegs[MISCREG_CPSR];
161 switch (cpsr.mode) {
162 case MODE_USER:
163 return miscRegs[MISCREG_SPSR];
164 case MODE_FIQ:
165 return miscRegs[MISCREG_SPSR_FIQ];
166 case MODE_IRQ:
167 return miscRegs[MISCREG_SPSR_IRQ];
168 case MODE_SVC:
169 return miscRegs[MISCREG_SPSR_SVC];
170 case MODE_MON:
171 return miscRegs[MISCREG_SPSR_MON];
172 case MODE_ABORT:
173 return miscRegs[MISCREG_SPSR_ABT];
174 case MODE_UNDEFINED:
175 return miscRegs[MISCREG_SPSR_UND];
176 default:
177 return miscRegs[MISCREG_SPSR];
178 }
179 }
180 return miscRegs[misc_reg];
181}
182
183
184MiscReg
185ISA::readMiscReg(int misc_reg, ThreadContext *tc)
186{
187 if (misc_reg == MISCREG_CPSR) {
188 CPSR cpsr = miscRegs[misc_reg];
189 Addr pc = tc->readPC();
190 if (pc & (ULL(1) << PcJBitShift))
191 cpsr.j = 1;
192 else
193 cpsr.j = 0;
194 if (pc & (ULL(1) << PcTBitShift))
195 cpsr.t = 1;
196 else
197 cpsr.t = 0;
198 return cpsr;
199 }
200 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
201 misc_reg < MISCREG_CP15_END) {
202 panic("Unimplemented CP15 register %s read.\n",
203 miscRegName[misc_reg]);
204 }
205 switch (misc_reg) {
206 case MISCREG_CLIDR:
207 warn("The clidr register always reports 0 caches.\n");
208 break;
209 case MISCREG_CCSIDR:
210 warn("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43namespace ArmISA
44{
45
46void
47ISA::clear()
48{
49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
50
51 memset(miscRegs, 0, sizeof(miscRegs));
52 CPSR cpsr = 0;
53 cpsr.mode = MODE_USER;
54 miscRegs[MISCREG_CPSR] = cpsr;
55 updateRegMap(cpsr);
56
57 SCTLR sctlr = 0;
58 sctlr.nmfi = (bool)sctlr_rst.nmfi;
59 sctlr.v = (bool)sctlr_rst.v;
60 sctlr.u = 1;
61 sctlr.xp = 1;
62 sctlr.rao2 = 1;
63 sctlr.rao3 = 1;
64 sctlr.rao4 = 1;
65 miscRegs[MISCREG_SCTLR] = sctlr;
66 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
67
68
69 /*
70 * Technically this should be 0, but we don't support those
71 * settings.
72 */
73 CPACR cpacr = 0;
74 // Enable CP 10, 11
75 cpacr.cp10 = 0x3;
76 cpacr.cp11 = 0x3;
77 miscRegs[MISCREG_CPACR] = cpacr;
78
79 /* Start with an event in the mailbox */
80 miscRegs[MISCREG_SEV_MAILBOX] = 1;
81
82 /*
83 * Implemented = '5' from "M5",
84 * Variant = 0,
85 */
86 miscRegs[MISCREG_MIDR] =
87 (0x35 << 24) | //Implementor is '5' from "M5"
88 (0 << 20) | //Variant
89 (0xf << 16) | //Architecture from CPUID scheme
90 (0 << 4) | //Primary part number
91 (0 << 0) | //Revision
92 0;
93
94 // Separate Instruction and Data TLBs.
95 miscRegs[MISCREG_TLBTR] = 1;
96
97 MVFR0 mvfr0 = 0;
98 mvfr0.advSimdRegisters = 2;
99 mvfr0.singlePrecision = 2;
100 mvfr0.doublePrecision = 2;
101 mvfr0.vfpExceptionTrapping = 0;
102 mvfr0.divide = 1;
103 mvfr0.squareRoot = 1;
104 mvfr0.shortVectors = 1;
105 mvfr0.roundingModes = 1;
106 miscRegs[MISCREG_MVFR0] = mvfr0;
107
108 MVFR1 mvfr1 = 0;
109 mvfr1.flushToZero = 1;
110 mvfr1.defaultNaN = 1;
111 mvfr1.advSimdLoadStore = 1;
112 mvfr1.advSimdInteger = 1;
113 mvfr1.advSimdSinglePrecision = 1;
114 mvfr1.advSimdHalfPrecision = 1;
115 mvfr1.vfpHalfPrecision = 1;
116 miscRegs[MISCREG_MVFR1] = mvfr1;
117
118 miscRegs[MISCREG_MPIDR] = 0;
119
120 // Reset values of PRRR and NMRR are implementation dependent
121
122 miscRegs[MISCREG_PRRR] =
123 (1 << 19) | // 19
124 (0 << 18) | // 18
125 (0 << 17) | // 17
126 (1 << 16) | // 16
127 (2 << 14) | // 15:14
128 (0 << 12) | // 13:12
129 (2 << 10) | // 11:10
130 (2 << 8) | // 9:8
131 (2 << 6) | // 7:6
132 (2 << 4) | // 5:4
133 (1 << 2) | // 3:2
134 0; // 1:0
135 miscRegs[MISCREG_NMRR] =
136 (1 << 30) | // 31:30
137 (0 << 26) | // 27:26
138 (0 << 24) | // 25:24
139 (3 << 22) | // 23:22
140 (2 << 20) | // 21:20
141 (0 << 18) | // 19:18
142 (0 << 16) | // 17:16
143 (1 << 14) | // 15:14
144 (0 << 12) | // 13:12
145 (2 << 10) | // 11:10
146 (0 << 8) | // 9:8
147 (3 << 6) | // 7:6
148 (2 << 4) | // 5:4
149 (0 << 2) | // 3:2
150 0; // 1:0
151
152 //XXX We need to initialize the rest of the state.
153}
154
155MiscReg
156ISA::readMiscRegNoEffect(int misc_reg)
157{
158 assert(misc_reg < NumMiscRegs);
159 if (misc_reg == MISCREG_SPSR) {
160 CPSR cpsr = miscRegs[MISCREG_CPSR];
161 switch (cpsr.mode) {
162 case MODE_USER:
163 return miscRegs[MISCREG_SPSR];
164 case MODE_FIQ:
165 return miscRegs[MISCREG_SPSR_FIQ];
166 case MODE_IRQ:
167 return miscRegs[MISCREG_SPSR_IRQ];
168 case MODE_SVC:
169 return miscRegs[MISCREG_SPSR_SVC];
170 case MODE_MON:
171 return miscRegs[MISCREG_SPSR_MON];
172 case MODE_ABORT:
173 return miscRegs[MISCREG_SPSR_ABT];
174 case MODE_UNDEFINED:
175 return miscRegs[MISCREG_SPSR_UND];
176 default:
177 return miscRegs[MISCREG_SPSR];
178 }
179 }
180 return miscRegs[misc_reg];
181}
182
183
184MiscReg
185ISA::readMiscReg(int misc_reg, ThreadContext *tc)
186{
187 if (misc_reg == MISCREG_CPSR) {
188 CPSR cpsr = miscRegs[misc_reg];
189 Addr pc = tc->readPC();
190 if (pc & (ULL(1) << PcJBitShift))
191 cpsr.j = 1;
192 else
193 cpsr.j = 0;
194 if (pc & (ULL(1) << PcTBitShift))
195 cpsr.t = 1;
196 else
197 cpsr.t = 0;
198 return cpsr;
199 }
200 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
201 misc_reg < MISCREG_CP15_END) {
202 panic("Unimplemented CP15 register %s read.\n",
203 miscRegName[misc_reg]);
204 }
205 switch (misc_reg) {
206 case MISCREG_CLIDR:
207 warn("The clidr register always reports 0 caches.\n");
208 break;
209 case MISCREG_CCSIDR:
210 warn("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
|
215 case MISCREG_ID_MMFR0:
216 return 0x03; //VMSAz7
217 case MISCREG_CTR:
218 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
219 case MISCREG_ACTLR:
220 warn("Not doing anything for miscreg ACTLR\n");
221 break;
222 case MISCREG_PMCR:
223 case MISCREG_PMCCNTR:
224 case MISCREG_PMSELR:
225 warn("Not doing anyhting for read to miscreg %s\n",
226 miscRegName[misc_reg]);
227 break;
228
229 }
230 return readMiscRegNoEffect(misc_reg);
231}
232
233void
234ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
235{
236 assert(misc_reg < NumMiscRegs);
237 if (misc_reg == MISCREG_SPSR) {
238 CPSR cpsr = miscRegs[MISCREG_CPSR];
239 switch (cpsr.mode) {
240 case MODE_USER:
241 miscRegs[MISCREG_SPSR] = val;
242 return;
243 case MODE_FIQ:
244 miscRegs[MISCREG_SPSR_FIQ] = val;
245 return;
246 case MODE_IRQ:
247 miscRegs[MISCREG_SPSR_IRQ] = val;
248 return;
249 case MODE_SVC:
250 miscRegs[MISCREG_SPSR_SVC] = val;
251 return;
252 case MODE_MON:
253 miscRegs[MISCREG_SPSR_MON] = val;
254 return;
255 case MODE_ABORT:
256 miscRegs[MISCREG_SPSR_ABT] = val;
257 return;
258 case MODE_UNDEFINED:
259 miscRegs[MISCREG_SPSR_UND] = val;
260 return;
261 default:
262 miscRegs[MISCREG_SPSR] = val;
263 return;
264 }
265 }
266 miscRegs[misc_reg] = val;
267}
268
269void
270ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
271{
272 MiscReg newVal = val;
273 if (misc_reg == MISCREG_CPSR) {
274 updateRegMap(val);
275 CPSR cpsr = val;
276 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
277 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
278 Addr npc = tc->readNextPC() & ~PcModeMask;
279 if (cpsr.j)
280 npc = npc | (ULL(1) << PcJBitShift);
281 if (cpsr.t)
282 npc = npc | (ULL(1) << PcTBitShift);
283
284 tc->setNextPC(npc);
285 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
286 misc_reg < MISCREG_CP15_END) {
287 panic("Unimplemented CP15 register %s wrote with %#x.\n",
288 miscRegName[misc_reg], val);
289 } else {
290 switch (misc_reg) {
291 case MISCREG_ITSTATE:
292 {
293 ITSTATE itstate = newVal;
294 CPSR cpsr = miscRegs[MISCREG_CPSR];
295 cpsr.it1 = itstate.bottom2;
296 cpsr.it2 = itstate.top6;
297 miscRegs[MISCREG_CPSR] = cpsr;
298 DPRINTF(MiscRegs,
299 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
300 (uint8_t)itstate, (uint32_t)cpsr);
301 }
302 break;
303 case MISCREG_CPACR:
304 {
305 CPACR newCpacr = 0;
306 CPACR valCpacr = val;
307 newCpacr.cp10 = valCpacr.cp10;
308 newCpacr.cp11 = valCpacr.cp11;
309 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
310 panic("Disabling coprocessors isn't implemented.\n");
311 }
312 newVal = newCpacr;
313 }
314 break;
315 case MISCREG_CSSELR:
316 warn("The csselr register isn't implemented.\n");
317 break;
318 case MISCREG_FPSCR:
319 {
320 const uint32_t ones = (uint32_t)(-1);
321 FPSCR fpscrMask = 0;
322 fpscrMask.ioc = ones;
323 fpscrMask.dzc = ones;
324 fpscrMask.ofc = ones;
325 fpscrMask.ufc = ones;
326 fpscrMask.ixc = ones;
327 fpscrMask.idc = ones;
328 fpscrMask.len = ones;
329 fpscrMask.stride = ones;
330 fpscrMask.rMode = ones;
331 fpscrMask.fz = ones;
332 fpscrMask.dn = ones;
333 fpscrMask.ahp = ones;
334 fpscrMask.qc = ones;
335 fpscrMask.v = ones;
336 fpscrMask.c = ones;
337 fpscrMask.z = ones;
338 fpscrMask.n = ones;
339 newVal = (newVal & (uint32_t)fpscrMask) |
340 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
341 }
342 break;
343 case MISCREG_FPEXC:
344 {
345 const uint32_t fpexcMask = 0x60000000;
346 newVal = (newVal & fpexcMask) |
347 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
348 }
349 break;
350 case MISCREG_SCTLR:
351 {
352 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
353 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
354 SCTLR new_sctlr = newVal;
355 new_sctlr.nmfi = (bool)sctlr.nmfi;
356 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
357 return;
358 }
359 case MISCREG_TLBTR:
360 case MISCREG_MVFR0:
361 case MISCREG_MVFR1:
362 case MISCREG_MPIDR:
363 case MISCREG_FPSID:
364 return;
365 case MISCREG_TLBIALLIS:
366 case MISCREG_TLBIALL:
367 warn("Need to flush all TLBs in MP\n");
368 tc->getITBPtr()->flushAll();
369 tc->getDTBPtr()->flushAll();
370 return;
371 case MISCREG_ITLBIALL:
372 tc->getITBPtr()->flushAll();
373 return;
374 case MISCREG_DTLBIALL:
375 tc->getDTBPtr()->flushAll();
376 return;
377 case MISCREG_TLBIMVAIS:
378 case MISCREG_TLBIMVA:
379 warn("Need to flush all TLBs in MP\n");
380 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
381 bits(newVal, 7,0));
382 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
383 bits(newVal, 7,0));
384 return;
385 case MISCREG_TLBIASIDIS:
386 case MISCREG_TLBIASID:
387 warn("Need to flush all TLBs in MP\n");
388 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
389 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
390 return;
391 case MISCREG_TLBIMVAAIS:
392 case MISCREG_TLBIMVAA:
393 warn("Need to flush all TLBs in MP\n");
394 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
395 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
396 return;
397 case MISCREG_ITLBIMVA:
398 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
399 bits(newVal, 7,0));
400 return;
401 case MISCREG_DTLBIMVA:
402 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
403 bits(newVal, 7,0));
404 return;
405 case MISCREG_ITLBIASID:
406 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
407 return;
408 case MISCREG_DTLBIASID:
409 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
410 return;
411 case MISCREG_ACTLR:
412 warn("Not doing anything for write of miscreg ACTLR\n");
413 break;
414 case MISCREG_PMCR:
415 case MISCREG_PMCCNTR:
416 case MISCREG_PMSELR:
417 warn("Not doing anything for write to miscreg %s\n",
418 miscRegName[misc_reg]);
419 break;
420 case MISCREG_V2PCWPR:
421 case MISCREG_V2PCWPW:
422 case MISCREG_V2PCWUR:
423 case MISCREG_V2PCWUW:
424 case MISCREG_V2POWPR:
425 case MISCREG_V2POWPW:
426 case MISCREG_V2POWUR:
427 case MISCREG_V2POWUW:
428 {
429 RequestPtr req = new Request;
430 unsigned flags;
431 BaseTLB::Mode mode;
432 Fault fault;
433 switch(misc_reg) {
434 case MISCREG_V2PCWPR:
435 flags = TLB::MustBeOne;
436 mode = BaseTLB::Read;
437 break;
438 case MISCREG_V2PCWPW:
439 flags = TLB::MustBeOne;
440 mode = BaseTLB::Write;
441 break;
442 case MISCREG_V2PCWUR:
443 flags = TLB::MustBeOne | TLB::UserMode;
444 mode = BaseTLB::Read;
445 break;
446 case MISCREG_V2PCWUW:
447 flags = TLB::MustBeOne | TLB::UserMode;
448 mode = BaseTLB::Write;
449 break;
450 default:
451 panic("Security Extensions not implemented!");
452 }
453 req->setVirt(0, val, 1, flags, tc->readPC());
454 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
455 if (fault == NoFault) {
456 miscRegs[MISCREG_PAR] =
457 (req->getPaddr() & 0xfffff000) |
458 (tc->getDTBPtr()->getAttr() );
459 DPRINTF(MiscRegs,
460 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
461 val, miscRegs[MISCREG_PAR]);
462 }
463 else {
464 // Set fault bit and FSR
465 FSR fsr = miscRegs[MISCREG_DFSR];
466 miscRegs[MISCREG_PAR] =
467 (fsr.ext << 6) |
468 (fsr.fsHigh << 5) |
469 (fsr.fsLow << 1) |
470 0x1; // F bit
471 }
472 return;
473 }
474 }
475 }
476 setMiscRegNoEffect(misc_reg, newVal);
477}
478
479}
| 217 case MISCREG_ID_MMFR0:
218 return 0x03; //VMSAz7
219 case MISCREG_CTR:
220 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
221 case MISCREG_ACTLR:
222 warn("Not doing anything for miscreg ACTLR\n");
223 break;
224 case MISCREG_PMCR:
225 case MISCREG_PMCCNTR:
226 case MISCREG_PMSELR:
227 warn("Not doing anyhting for read to miscreg %s\n",
228 miscRegName[misc_reg]);
229 break;
230
231 }
232 return readMiscRegNoEffect(misc_reg);
233}
234
235void
236ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
237{
238 assert(misc_reg < NumMiscRegs);
239 if (misc_reg == MISCREG_SPSR) {
240 CPSR cpsr = miscRegs[MISCREG_CPSR];
241 switch (cpsr.mode) {
242 case MODE_USER:
243 miscRegs[MISCREG_SPSR] = val;
244 return;
245 case MODE_FIQ:
246 miscRegs[MISCREG_SPSR_FIQ] = val;
247 return;
248 case MODE_IRQ:
249 miscRegs[MISCREG_SPSR_IRQ] = val;
250 return;
251 case MODE_SVC:
252 miscRegs[MISCREG_SPSR_SVC] = val;
253 return;
254 case MODE_MON:
255 miscRegs[MISCREG_SPSR_MON] = val;
256 return;
257 case MODE_ABORT:
258 miscRegs[MISCREG_SPSR_ABT] = val;
259 return;
260 case MODE_UNDEFINED:
261 miscRegs[MISCREG_SPSR_UND] = val;
262 return;
263 default:
264 miscRegs[MISCREG_SPSR] = val;
265 return;
266 }
267 }
268 miscRegs[misc_reg] = val;
269}
270
271void
272ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
273{
274 MiscReg newVal = val;
275 if (misc_reg == MISCREG_CPSR) {
276 updateRegMap(val);
277 CPSR cpsr = val;
278 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
279 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
280 Addr npc = tc->readNextPC() & ~PcModeMask;
281 if (cpsr.j)
282 npc = npc | (ULL(1) << PcJBitShift);
283 if (cpsr.t)
284 npc = npc | (ULL(1) << PcTBitShift);
285
286 tc->setNextPC(npc);
287 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
288 misc_reg < MISCREG_CP15_END) {
289 panic("Unimplemented CP15 register %s wrote with %#x.\n",
290 miscRegName[misc_reg], val);
291 } else {
292 switch (misc_reg) {
293 case MISCREG_ITSTATE:
294 {
295 ITSTATE itstate = newVal;
296 CPSR cpsr = miscRegs[MISCREG_CPSR];
297 cpsr.it1 = itstate.bottom2;
298 cpsr.it2 = itstate.top6;
299 miscRegs[MISCREG_CPSR] = cpsr;
300 DPRINTF(MiscRegs,
301 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
302 (uint8_t)itstate, (uint32_t)cpsr);
303 }
304 break;
305 case MISCREG_CPACR:
306 {
307 CPACR newCpacr = 0;
308 CPACR valCpacr = val;
309 newCpacr.cp10 = valCpacr.cp10;
310 newCpacr.cp11 = valCpacr.cp11;
311 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
312 panic("Disabling coprocessors isn't implemented.\n");
313 }
314 newVal = newCpacr;
315 }
316 break;
317 case MISCREG_CSSELR:
318 warn("The csselr register isn't implemented.\n");
319 break;
320 case MISCREG_FPSCR:
321 {
322 const uint32_t ones = (uint32_t)(-1);
323 FPSCR fpscrMask = 0;
324 fpscrMask.ioc = ones;
325 fpscrMask.dzc = ones;
326 fpscrMask.ofc = ones;
327 fpscrMask.ufc = ones;
328 fpscrMask.ixc = ones;
329 fpscrMask.idc = ones;
330 fpscrMask.len = ones;
331 fpscrMask.stride = ones;
332 fpscrMask.rMode = ones;
333 fpscrMask.fz = ones;
334 fpscrMask.dn = ones;
335 fpscrMask.ahp = ones;
336 fpscrMask.qc = ones;
337 fpscrMask.v = ones;
338 fpscrMask.c = ones;
339 fpscrMask.z = ones;
340 fpscrMask.n = ones;
341 newVal = (newVal & (uint32_t)fpscrMask) |
342 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
343 }
344 break;
345 case MISCREG_FPEXC:
346 {
347 const uint32_t fpexcMask = 0x60000000;
348 newVal = (newVal & fpexcMask) |
349 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
350 }
351 break;
352 case MISCREG_SCTLR:
353 {
354 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
355 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
356 SCTLR new_sctlr = newVal;
357 new_sctlr.nmfi = (bool)sctlr.nmfi;
358 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
359 return;
360 }
361 case MISCREG_TLBTR:
362 case MISCREG_MVFR0:
363 case MISCREG_MVFR1:
364 case MISCREG_MPIDR:
365 case MISCREG_FPSID:
366 return;
367 case MISCREG_TLBIALLIS:
368 case MISCREG_TLBIALL:
369 warn("Need to flush all TLBs in MP\n");
370 tc->getITBPtr()->flushAll();
371 tc->getDTBPtr()->flushAll();
372 return;
373 case MISCREG_ITLBIALL:
374 tc->getITBPtr()->flushAll();
375 return;
376 case MISCREG_DTLBIALL:
377 tc->getDTBPtr()->flushAll();
378 return;
379 case MISCREG_TLBIMVAIS:
380 case MISCREG_TLBIMVA:
381 warn("Need to flush all TLBs in MP\n");
382 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
383 bits(newVal, 7,0));
384 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
385 bits(newVal, 7,0));
386 return;
387 case MISCREG_TLBIASIDIS:
388 case MISCREG_TLBIASID:
389 warn("Need to flush all TLBs in MP\n");
390 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
391 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
392 return;
393 case MISCREG_TLBIMVAAIS:
394 case MISCREG_TLBIMVAA:
395 warn("Need to flush all TLBs in MP\n");
396 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
397 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
398 return;
399 case MISCREG_ITLBIMVA:
400 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
401 bits(newVal, 7,0));
402 return;
403 case MISCREG_DTLBIMVA:
404 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
405 bits(newVal, 7,0));
406 return;
407 case MISCREG_ITLBIASID:
408 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
409 return;
410 case MISCREG_DTLBIASID:
411 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
412 return;
413 case MISCREG_ACTLR:
414 warn("Not doing anything for write of miscreg ACTLR\n");
415 break;
416 case MISCREG_PMCR:
417 case MISCREG_PMCCNTR:
418 case MISCREG_PMSELR:
419 warn("Not doing anything for write to miscreg %s\n",
420 miscRegName[misc_reg]);
421 break;
422 case MISCREG_V2PCWPR:
423 case MISCREG_V2PCWPW:
424 case MISCREG_V2PCWUR:
425 case MISCREG_V2PCWUW:
426 case MISCREG_V2POWPR:
427 case MISCREG_V2POWPW:
428 case MISCREG_V2POWUR:
429 case MISCREG_V2POWUW:
430 {
431 RequestPtr req = new Request;
432 unsigned flags;
433 BaseTLB::Mode mode;
434 Fault fault;
435 switch(misc_reg) {
436 case MISCREG_V2PCWPR:
437 flags = TLB::MustBeOne;
438 mode = BaseTLB::Read;
439 break;
440 case MISCREG_V2PCWPW:
441 flags = TLB::MustBeOne;
442 mode = BaseTLB::Write;
443 break;
444 case MISCREG_V2PCWUR:
445 flags = TLB::MustBeOne | TLB::UserMode;
446 mode = BaseTLB::Read;
447 break;
448 case MISCREG_V2PCWUW:
449 flags = TLB::MustBeOne | TLB::UserMode;
450 mode = BaseTLB::Write;
451 break;
452 default:
453 panic("Security Extensions not implemented!");
454 }
455 req->setVirt(0, val, 1, flags, tc->readPC());
456 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
457 if (fault == NoFault) {
458 miscRegs[MISCREG_PAR] =
459 (req->getPaddr() & 0xfffff000) |
460 (tc->getDTBPtr()->getAttr() );
461 DPRINTF(MiscRegs,
462 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
463 val, miscRegs[MISCREG_PAR]);
464 }
465 else {
466 // Set fault bit and FSR
467 FSR fsr = miscRegs[MISCREG_DFSR];
468 miscRegs[MISCREG_PAR] =
469 (fsr.ext << 6) |
470 (fsr.fsHigh << 5) |
471 (fsr.fsLow << 1) |
472 0x1; // F bit
473 }
474 return;
475 }
476 }
477 }
478 setMiscRegNoEffect(misc_reg, newVal);
479}
480
481}
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