692 default: 693 break; 694 695 } 696 return readMiscRegNoEffect(misc_reg); 697} 698 699void 700ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 701{ 702 assert(misc_reg < NumMiscRegs); 703 704 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 705 const auto &map = getMiscIndices(misc_reg); 706 int lower = map.first, upper = map.second; 707 708 auto v = (val & ~reg.wi()) | reg.rao(); 709 if (upper > 0) { 710 miscRegs[lower] = bits(v, 31, 0); 711 miscRegs[upper] = bits(v, 63, 32); 712 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 713 misc_reg, lower, upper, v); 714 } else { 715 miscRegs[lower] = v; 716 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 717 misc_reg, lower, v); 718 } 719} 720 721void 722ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 723{ 724 725 MiscReg newVal = val; 726 bool secure_lookup; 727 SCR scr; 728 729 if (misc_reg == MISCREG_CPSR) { 730 updateRegMap(val); 731 732 733 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 734 int old_mode = old_cpsr.mode; 735 CPSR cpsr = val; 736 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 737 getITBPtr(tc)->invalidateMiscReg(); 738 getDTBPtr(tc)->invalidateMiscReg(); 739 } 740 741 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 742 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 743 PCState pc = tc->pcState(); 744 pc.nextThumb(cpsr.t); 745 pc.nextJazelle(cpsr.j); 746 pc.illegalExec(cpsr.il == 1); 747 748 // Follow slightly different semantics if a CheckerCPU object 749 // is connected 750 CheckerCPU *checker = tc->getCheckerCpuPtr(); 751 if (checker) { 752 tc->pcStateNoRecord(pc); 753 } else { 754 tc->pcState(pc); 755 } 756 } else { 757#ifndef NDEBUG 758 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 759 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 760 warn("Unimplemented system register %s write with %#x.\n", 761 miscRegName[misc_reg], val); 762 else 763 panic("Unimplemented system register %s write with %#x.\n", 764 miscRegName[misc_reg], val); 765 } 766#endif 767 switch (unflattenMiscReg(misc_reg)) { 768 case MISCREG_CPACR: 769 { 770 771 const uint32_t ones = (uint32_t)(-1); 772 CPACR cpacrMask = 0; 773 // Only cp10, cp11, and ase are implemented, nothing else should 774 // be writable 775 cpacrMask.cp10 = ones; 776 cpacrMask.cp11 = ones; 777 cpacrMask.asedis = ones; 778 779 // Security Extensions may limit the writability of CPACR 780 if (haveSecurity) { 781 scr = readMiscRegNoEffect(MISCREG_SCR); 782 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 783 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 784 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 785 // NB: Skipping the full loop, here 786 if (!nsacr.cp10) cpacrMask.cp10 = 0; 787 if (!nsacr.cp11) cpacrMask.cp11 = 0; 788 } 789 } 790 791 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 792 newVal &= cpacrMask; 793 newVal |= old_val & ~cpacrMask; 794 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 795 miscRegName[misc_reg], newVal); 796 } 797 break; 798 case MISCREG_CPTR_EL2: 799 { 800 const uint32_t ones = (uint32_t)(-1); 801 CPTR cptrMask = 0; 802 cptrMask.tcpac = ones; 803 cptrMask.tta = ones; 804 cptrMask.tfp = ones; 805 newVal &= cptrMask; 806 cptrMask = 0; 807 cptrMask.res1_13_12_el2 = ones; 808 cptrMask.res1_9_0_el2 = ones; 809 newVal |= cptrMask; 810 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 811 miscRegName[misc_reg], newVal); 812 } 813 break; 814 case MISCREG_CPTR_EL3: 815 { 816 const uint32_t ones = (uint32_t)(-1); 817 CPTR cptrMask = 0; 818 cptrMask.tcpac = ones; 819 cptrMask.tta = ones; 820 cptrMask.tfp = ones; 821 newVal &= cptrMask; 822 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 823 miscRegName[misc_reg], newVal); 824 } 825 break; 826 case MISCREG_CSSELR: 827 warn_once("The csselr register isn't implemented.\n"); 828 return; 829 830 case MISCREG_DC_ZVA_Xt: 831 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 832 return; 833 834 case MISCREG_FPSCR: 835 { 836 const uint32_t ones = (uint32_t)(-1); 837 FPSCR fpscrMask = 0; 838 fpscrMask.ioc = ones; 839 fpscrMask.dzc = ones; 840 fpscrMask.ofc = ones; 841 fpscrMask.ufc = ones; 842 fpscrMask.ixc = ones; 843 fpscrMask.idc = ones; 844 fpscrMask.ioe = ones; 845 fpscrMask.dze = ones; 846 fpscrMask.ofe = ones; 847 fpscrMask.ufe = ones; 848 fpscrMask.ixe = ones; 849 fpscrMask.ide = ones; 850 fpscrMask.len = ones; 851 fpscrMask.stride = ones; 852 fpscrMask.rMode = ones; 853 fpscrMask.fz = ones; 854 fpscrMask.dn = ones; 855 fpscrMask.ahp = ones; 856 fpscrMask.qc = ones; 857 fpscrMask.v = ones; 858 fpscrMask.c = ones; 859 fpscrMask.z = ones; 860 fpscrMask.n = ones; 861 newVal = (newVal & (uint32_t)fpscrMask) | 862 (readMiscRegNoEffect(MISCREG_FPSCR) & 863 ~(uint32_t)fpscrMask); 864 tc->getDecoderPtr()->setContext(newVal); 865 } 866 break; 867 case MISCREG_FPSR: 868 { 869 const uint32_t ones = (uint32_t)(-1); 870 FPSCR fpscrMask = 0; 871 fpscrMask.ioc = ones; 872 fpscrMask.dzc = ones; 873 fpscrMask.ofc = ones; 874 fpscrMask.ufc = ones; 875 fpscrMask.ixc = ones; 876 fpscrMask.idc = ones; 877 fpscrMask.qc = ones; 878 fpscrMask.v = ones; 879 fpscrMask.c = ones; 880 fpscrMask.z = ones; 881 fpscrMask.n = ones; 882 newVal = (newVal & (uint32_t)fpscrMask) | 883 (readMiscRegNoEffect(MISCREG_FPSCR) & 884 ~(uint32_t)fpscrMask); 885 misc_reg = MISCREG_FPSCR; 886 } 887 break; 888 case MISCREG_FPCR: 889 { 890 const uint32_t ones = (uint32_t)(-1); 891 FPSCR fpscrMask = 0; 892 fpscrMask.len = ones; 893 fpscrMask.stride = ones; 894 fpscrMask.rMode = ones; 895 fpscrMask.fz = ones; 896 fpscrMask.dn = ones; 897 fpscrMask.ahp = ones; 898 newVal = (newVal & (uint32_t)fpscrMask) | 899 (readMiscRegNoEffect(MISCREG_FPSCR) & 900 ~(uint32_t)fpscrMask); 901 misc_reg = MISCREG_FPSCR; 902 } 903 break; 904 case MISCREG_CPSR_Q: 905 { 906 assert(!(newVal & ~CpsrMaskQ)); 907 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 908 misc_reg = MISCREG_CPSR; 909 } 910 break; 911 case MISCREG_FPSCR_QC: 912 { 913 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 914 (newVal & FpscrQcMask); 915 misc_reg = MISCREG_FPSCR; 916 } 917 break; 918 case MISCREG_FPSCR_EXC: 919 { 920 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 921 (newVal & FpscrExcMask); 922 misc_reg = MISCREG_FPSCR; 923 } 924 break; 925 case MISCREG_FPEXC: 926 { 927 // vfpv3 architecture, section B.6.1 of DDI04068 928 // bit 29 - valid only if fpexc[31] is 0 929 const uint32_t fpexcMask = 0x60000000; 930 newVal = (newVal & fpexcMask) | 931 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 932 } 933 break; 934 case MISCREG_HCR: 935 { 936 if (!haveVirtualization) 937 return; 938 } 939 break; 940 case MISCREG_IFSR: 941 { 942 // ARM ARM (ARM DDI 0406C.b) B4.1.96 943 const uint32_t ifsrMask = 944 mask(31, 13) | mask(11, 11) | mask(8, 6); 945 newVal = newVal & ~ifsrMask; 946 } 947 break; 948 case MISCREG_DFSR: 949 { 950 // ARM ARM (ARM DDI 0406C.b) B4.1.52 951 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 952 newVal = newVal & ~dfsrMask; 953 } 954 break; 955 case MISCREG_AMAIR0: 956 case MISCREG_AMAIR1: 957 { 958 // ARM ARM (ARM DDI 0406C.b) B4.1.5 959 // Valid only with LPAE 960 if (!haveLPAE) 961 return; 962 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 963 } 964 break; 965 case MISCREG_SCR: 966 getITBPtr(tc)->invalidateMiscReg(); 967 getDTBPtr(tc)->invalidateMiscReg(); 968 break; 969 case MISCREG_SCTLR: 970 { 971 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 972 scr = readMiscRegNoEffect(MISCREG_SCR); 973 974 MiscRegIndex sctlr_idx; 975 if (haveSecurity && !highestELIs64 && !scr.ns) { 976 sctlr_idx = MISCREG_SCTLR_S; 977 } else { 978 sctlr_idx = MISCREG_SCTLR_NS; 979 } 980 981 SCTLR sctlr = miscRegs[sctlr_idx]; 982 SCTLR new_sctlr = newVal; 983 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 984 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 985 getITBPtr(tc)->invalidateMiscReg(); 986 getDTBPtr(tc)->invalidateMiscReg(); 987 } 988 case MISCREG_MIDR: 989 case MISCREG_ID_PFR0: 990 case MISCREG_ID_PFR1: 991 case MISCREG_ID_DFR0: 992 case MISCREG_ID_MMFR0: 993 case MISCREG_ID_MMFR1: 994 case MISCREG_ID_MMFR2: 995 case MISCREG_ID_MMFR3: 996 case MISCREG_ID_ISAR0: 997 case MISCREG_ID_ISAR1: 998 case MISCREG_ID_ISAR2: 999 case MISCREG_ID_ISAR3: 1000 case MISCREG_ID_ISAR4: 1001 case MISCREG_ID_ISAR5: 1002 1003 case MISCREG_MPIDR: 1004 case MISCREG_FPSID: 1005 case MISCREG_TLBTR: 1006 case MISCREG_MVFR0: 1007 case MISCREG_MVFR1: 1008 1009 case MISCREG_ID_AA64AFR0_EL1: 1010 case MISCREG_ID_AA64AFR1_EL1: 1011 case MISCREG_ID_AA64DFR0_EL1: 1012 case MISCREG_ID_AA64DFR1_EL1: 1013 case MISCREG_ID_AA64ISAR0_EL1: 1014 case MISCREG_ID_AA64ISAR1_EL1: 1015 case MISCREG_ID_AA64MMFR0_EL1: 1016 case MISCREG_ID_AA64MMFR1_EL1: 1017 case MISCREG_ID_AA64MMFR2_EL1: 1018 case MISCREG_ID_AA64PFR0_EL1: 1019 case MISCREG_ID_AA64PFR1_EL1: 1020 // ID registers are constants. 1021 return; 1022 1023 // TLB Invalidate All 1024 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1025 { 1026 assert32(tc); 1027 scr = readMiscReg(MISCREG_SCR, tc); 1028 1029 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1030 tlbiOp(tc); 1031 return; 1032 } 1033 // TLB Invalidate All, Inner Shareable 1034 case MISCREG_TLBIALLIS: 1035 { 1036 assert32(tc); 1037 scr = readMiscReg(MISCREG_SCR, tc); 1038 1039 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1040 tlbiOp.broadcast(tc); 1041 return; 1042 } 1043 // Instruction TLB Invalidate All 1044 case MISCREG_ITLBIALL: 1045 { 1046 assert32(tc); 1047 scr = readMiscReg(MISCREG_SCR, tc); 1048 1049 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1050 tlbiOp(tc); 1051 return; 1052 } 1053 // Data TLB Invalidate All 1054 case MISCREG_DTLBIALL: 1055 { 1056 assert32(tc); 1057 scr = readMiscReg(MISCREG_SCR, tc); 1058 1059 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1060 tlbiOp(tc); 1061 return; 1062 } 1063 // TLB Invalidate by VA 1064 // mcr tlbimval(is) is invalidating all matching entries 1065 // regardless of the level of lookup, since in gem5 we cache 1066 // in the tlb the last level of lookup only. 1067 case MISCREG_TLBIMVA: 1068 case MISCREG_TLBIMVAL: 1069 { 1070 assert32(tc); 1071 scr = readMiscReg(MISCREG_SCR, tc); 1072 1073 TLBIMVA tlbiOp(EL1, 1074 haveSecurity && !scr.ns, 1075 mbits(newVal, 31, 12), 1076 bits(newVal, 7,0)); 1077 1078 tlbiOp(tc); 1079 return; 1080 } 1081 // TLB Invalidate by VA, Inner Shareable 1082 case MISCREG_TLBIMVAIS: 1083 case MISCREG_TLBIMVALIS: 1084 { 1085 assert32(tc); 1086 scr = readMiscReg(MISCREG_SCR, tc); 1087 1088 TLBIMVA tlbiOp(EL1, 1089 haveSecurity && !scr.ns, 1090 mbits(newVal, 31, 12), 1091 bits(newVal, 7,0)); 1092 1093 tlbiOp.broadcast(tc); 1094 return; 1095 } 1096 // TLB Invalidate by ASID match 1097 case MISCREG_TLBIASID: 1098 { 1099 assert32(tc); 1100 scr = readMiscReg(MISCREG_SCR, tc); 1101 1102 TLBIASID tlbiOp(EL1, 1103 haveSecurity && !scr.ns, 1104 bits(newVal, 7,0)); 1105 1106 tlbiOp(tc); 1107 return; 1108 } 1109 // TLB Invalidate by ASID match, Inner Shareable 1110 case MISCREG_TLBIASIDIS: 1111 { 1112 assert32(tc); 1113 scr = readMiscReg(MISCREG_SCR, tc); 1114 1115 TLBIASID tlbiOp(EL1, 1116 haveSecurity && !scr.ns, 1117 bits(newVal, 7,0)); 1118 1119 tlbiOp.broadcast(tc); 1120 return; 1121 } 1122 // mcr tlbimvaal(is) is invalidating all matching entries 1123 // regardless of the level of lookup, since in gem5 we cache 1124 // in the tlb the last level of lookup only. 1125 // TLB Invalidate by VA, All ASID 1126 case MISCREG_TLBIMVAA: 1127 case MISCREG_TLBIMVAAL: 1128 { 1129 assert32(tc); 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 1132 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1133 mbits(newVal, 31,12), false); 1134 1135 tlbiOp(tc); 1136 return; 1137 } 1138 // TLB Invalidate by VA, All ASID, Inner Shareable 1139 case MISCREG_TLBIMVAAIS: 1140 case MISCREG_TLBIMVAALIS: 1141 { 1142 assert32(tc); 1143 scr = readMiscReg(MISCREG_SCR, tc); 1144 1145 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1146 mbits(newVal, 31,12), false); 1147 1148 tlbiOp.broadcast(tc); 1149 return; 1150 } 1151 // mcr tlbimvalh(is) is invalidating all matching entries 1152 // regardless of the level of lookup, since in gem5 we cache 1153 // in the tlb the last level of lookup only. 1154 // TLB Invalidate by VA, Hyp mode 1155 case MISCREG_TLBIMVAH: 1156 case MISCREG_TLBIMVALH: 1157 { 1158 assert32(tc); 1159 scr = readMiscReg(MISCREG_SCR, tc); 1160 1161 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1162 mbits(newVal, 31,12), true); 1163 1164 tlbiOp(tc); 1165 return; 1166 } 1167 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1168 case MISCREG_TLBIMVAHIS: 1169 case MISCREG_TLBIMVALHIS: 1170 { 1171 assert32(tc); 1172 scr = readMiscReg(MISCREG_SCR, tc); 1173 1174 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1175 mbits(newVal, 31,12), true); 1176 1177 tlbiOp.broadcast(tc); 1178 return; 1179 } 1180 // mcr tlbiipas2l(is) is invalidating all matching entries 1181 // regardless of the level of lookup, since in gem5 we cache 1182 // in the tlb the last level of lookup only. 1183 // TLB Invalidate by Intermediate Physical Address, Stage 2 1184 case MISCREG_TLBIIPAS2: 1185 case MISCREG_TLBIIPAS2L: 1186 { 1187 assert32(tc); 1188 scr = readMiscReg(MISCREG_SCR, tc); 1189 1190 TLBIIPA tlbiOp(EL1, 1191 haveSecurity && !scr.ns, 1192 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1193 1194 tlbiOp(tc); 1195 return; 1196 } 1197 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1198 // Inner Shareable 1199 case MISCREG_TLBIIPAS2IS: 1200 case MISCREG_TLBIIPAS2LIS: 1201 { 1202 assert32(tc); 1203 scr = readMiscReg(MISCREG_SCR, tc); 1204 1205 TLBIIPA tlbiOp(EL1, 1206 haveSecurity && !scr.ns, 1207 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1208 1209 tlbiOp.broadcast(tc); 1210 return; 1211 } 1212 // Instruction TLB Invalidate by VA 1213 case MISCREG_ITLBIMVA: 1214 { 1215 assert32(tc); 1216 scr = readMiscReg(MISCREG_SCR, tc); 1217 1218 ITLBIMVA tlbiOp(EL1, 1219 haveSecurity && !scr.ns, 1220 mbits(newVal, 31, 12), 1221 bits(newVal, 7,0)); 1222 1223 tlbiOp(tc); 1224 return; 1225 } 1226 // Data TLB Invalidate by VA 1227 case MISCREG_DTLBIMVA: 1228 { 1229 assert32(tc); 1230 scr = readMiscReg(MISCREG_SCR, tc); 1231 1232 DTLBIMVA tlbiOp(EL1, 1233 haveSecurity && !scr.ns, 1234 mbits(newVal, 31, 12), 1235 bits(newVal, 7,0)); 1236 1237 tlbiOp(tc); 1238 return; 1239 } 1240 // Instruction TLB Invalidate by ASID match 1241 case MISCREG_ITLBIASID: 1242 { 1243 assert32(tc); 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 1246 ITLBIASID tlbiOp(EL1, 1247 haveSecurity && !scr.ns, 1248 bits(newVal, 7,0)); 1249 1250 tlbiOp(tc); 1251 return; 1252 } 1253 // Data TLB Invalidate by ASID match 1254 case MISCREG_DTLBIASID: 1255 { 1256 assert32(tc); 1257 scr = readMiscReg(MISCREG_SCR, tc); 1258 1259 DTLBIASID tlbiOp(EL1, 1260 haveSecurity && !scr.ns, 1261 bits(newVal, 7,0)); 1262 1263 tlbiOp(tc); 1264 return; 1265 } 1266 // TLB Invalidate All, Non-Secure Non-Hyp 1267 case MISCREG_TLBIALLNSNH: 1268 { 1269 assert32(tc); 1270 1271 TLBIALLN tlbiOp(EL1, false); 1272 tlbiOp(tc); 1273 return; 1274 } 1275 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1276 case MISCREG_TLBIALLNSNHIS: 1277 { 1278 assert32(tc); 1279 1280 TLBIALLN tlbiOp(EL1, false); 1281 tlbiOp.broadcast(tc); 1282 return; 1283 } 1284 // TLB Invalidate All, Hyp mode 1285 case MISCREG_TLBIALLH: 1286 { 1287 assert32(tc); 1288 1289 TLBIALLN tlbiOp(EL1, true); 1290 tlbiOp(tc); 1291 return; 1292 } 1293 // TLB Invalidate All, Hyp mode, Inner Shareable 1294 case MISCREG_TLBIALLHIS: 1295 { 1296 assert32(tc); 1297 1298 TLBIALLN tlbiOp(EL1, true); 1299 tlbiOp.broadcast(tc); 1300 return; 1301 } 1302 // AArch64 TLB Invalidate All, EL3 1303 case MISCREG_TLBI_ALLE3: 1304 { 1305 assert64(tc); 1306 1307 TLBIALL tlbiOp(EL3, true); 1308 tlbiOp(tc); 1309 return; 1310 } 1311 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1312 case MISCREG_TLBI_ALLE3IS: 1313 { 1314 assert64(tc); 1315 1316 TLBIALL tlbiOp(EL3, true); 1317 tlbiOp.broadcast(tc); 1318 return; 1319 } 1320 // @todo: uncomment this to enable Virtualization 1321 // case MISCREG_TLBI_ALLE2IS: 1322 // case MISCREG_TLBI_ALLE2: 1323 // AArch64 TLB Invalidate All, EL1 1324 case MISCREG_TLBI_ALLE1: 1325 case MISCREG_TLBI_VMALLE1: 1326 case MISCREG_TLBI_VMALLS12E1: 1327 // @todo: handle VMID and stage 2 to enable Virtualization 1328 { 1329 assert64(tc); 1330 scr = readMiscReg(MISCREG_SCR, tc); 1331 1332 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1333 tlbiOp(tc); 1334 return; 1335 } 1336 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1337 case MISCREG_TLBI_ALLE1IS: 1338 case MISCREG_TLBI_VMALLE1IS: 1339 case MISCREG_TLBI_VMALLS12E1IS: 1340 // @todo: handle VMID and stage 2 to enable Virtualization 1341 { 1342 assert64(tc); 1343 scr = readMiscReg(MISCREG_SCR, tc); 1344 1345 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1346 tlbiOp.broadcast(tc); 1347 return; 1348 } 1349 // VAEx(IS) and VALEx(IS) are the same because TLBs 1350 // only store entries 1351 // from the last level of translation table walks 1352 // @todo: handle VMID to enable Virtualization 1353 // AArch64 TLB Invalidate by VA, EL3 1354 case MISCREG_TLBI_VAE3_Xt: 1355 case MISCREG_TLBI_VALE3_Xt: 1356 { 1357 assert64(tc); 1358 1359 TLBIMVA tlbiOp(EL3, true, 1360 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1361 0xbeef); 1362 tlbiOp(tc); 1363 return; 1364 } 1365 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1366 case MISCREG_TLBI_VAE3IS_Xt: 1367 case MISCREG_TLBI_VALE3IS_Xt: 1368 { 1369 assert64(tc); 1370 1371 TLBIMVA tlbiOp(EL3, true, 1372 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1373 0xbeef); 1374 1375 tlbiOp.broadcast(tc); 1376 return; 1377 } 1378 // AArch64 TLB Invalidate by VA, EL2 1379 case MISCREG_TLBI_VAE2_Xt: 1380 case MISCREG_TLBI_VALE2_Xt: 1381 { 1382 assert64(tc); 1383 scr = readMiscReg(MISCREG_SCR, tc); 1384 1385 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1386 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1387 0xbeef); 1388 tlbiOp(tc); 1389 return; 1390 } 1391 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1392 case MISCREG_TLBI_VAE2IS_Xt: 1393 case MISCREG_TLBI_VALE2IS_Xt: 1394 { 1395 assert64(tc); 1396 scr = readMiscReg(MISCREG_SCR, tc); 1397 1398 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1399 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1400 0xbeef); 1401 1402 tlbiOp.broadcast(tc); 1403 return; 1404 } 1405 // AArch64 TLB Invalidate by VA, EL1 1406 case MISCREG_TLBI_VAE1_Xt: 1407 case MISCREG_TLBI_VALE1_Xt: 1408 { 1409 assert64(tc); 1410 scr = readMiscReg(MISCREG_SCR, tc); 1411 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1412 bits(newVal, 55, 48); 1413 1414 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1415 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1416 asid); 1417 1418 tlbiOp(tc); 1419 return; 1420 } 1421 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1422 case MISCREG_TLBI_VAE1IS_Xt: 1423 case MISCREG_TLBI_VALE1IS_Xt: 1424 { 1425 assert64(tc); 1426 scr = readMiscReg(MISCREG_SCR, tc); 1427 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1428 bits(newVal, 55, 48); 1429 1430 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1431 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1432 asid); 1433 1434 tlbiOp.broadcast(tc); 1435 return; 1436 } 1437 // AArch64 TLB Invalidate by ASID, EL1 1438 // @todo: handle VMID to enable Virtualization 1439 case MISCREG_TLBI_ASIDE1_Xt: 1440 { 1441 assert64(tc); 1442 scr = readMiscReg(MISCREG_SCR, tc); 1443 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1444 bits(newVal, 55, 48); 1445 1446 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1447 tlbiOp(tc); 1448 return; 1449 } 1450 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1451 case MISCREG_TLBI_ASIDE1IS_Xt: 1452 { 1453 assert64(tc); 1454 scr = readMiscReg(MISCREG_SCR, tc); 1455 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1456 bits(newVal, 55, 48); 1457 1458 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1459 tlbiOp.broadcast(tc); 1460 return; 1461 } 1462 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1463 // entries from the last level of translation table walks 1464 // AArch64 TLB Invalidate by VA, All ASID, EL1 1465 case MISCREG_TLBI_VAAE1_Xt: 1466 case MISCREG_TLBI_VAALE1_Xt: 1467 { 1468 assert64(tc); 1469 scr = readMiscReg(MISCREG_SCR, tc); 1470 1471 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1472 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1473 1474 tlbiOp(tc); 1475 return; 1476 } 1477 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1478 case MISCREG_TLBI_VAAE1IS_Xt: 1479 case MISCREG_TLBI_VAALE1IS_Xt: 1480 { 1481 assert64(tc); 1482 scr = readMiscReg(MISCREG_SCR, tc); 1483 1484 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1485 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1486 1487 tlbiOp.broadcast(tc); 1488 return; 1489 } 1490 // AArch64 TLB Invalidate by Intermediate Physical Address, 1491 // Stage 2, EL1 1492 case MISCREG_TLBI_IPAS2E1_Xt: 1493 case MISCREG_TLBI_IPAS2LE1_Xt: 1494 { 1495 assert64(tc); 1496 scr = readMiscReg(MISCREG_SCR, tc); 1497 1498 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1499 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1500 1501 tlbiOp(tc); 1502 return; 1503 } 1504 // AArch64 TLB Invalidate by Intermediate Physical Address, 1505 // Stage 2, EL1, Inner Shareable 1506 case MISCREG_TLBI_IPAS2E1IS_Xt: 1507 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1508 { 1509 assert64(tc); 1510 scr = readMiscReg(MISCREG_SCR, tc); 1511 1512 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1513 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1514 1515 tlbiOp.broadcast(tc); 1516 return; 1517 } 1518 case MISCREG_ACTLR: 1519 warn("Not doing anything for write of miscreg ACTLR\n"); 1520 break; 1521 1522 case MISCREG_PMXEVTYPER_PMCCFILTR: 1523 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1524 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1525 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1526 pmu->setMiscReg(misc_reg, newVal); 1527 break; 1528 1529 1530 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1531 { 1532 HSTR hstrMask = 0; 1533 hstrMask.tjdbx = 1; 1534 newVal &= ~((uint32_t) hstrMask); 1535 break; 1536 } 1537 case MISCREG_HCPTR: 1538 { 1539 // If a CP bit in NSACR is 0 then the corresponding bit in 1540 // HCPTR is RAO/WI. Same applies to NSASEDIS 1541 secure_lookup = haveSecurity && 1542 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1543 readMiscRegNoEffect(MISCREG_CPSR)); 1544 if (!secure_lookup) { 1545 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1546 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1547 newVal = (newVal & ~mask) | (oldValue & mask); 1548 } 1549 break; 1550 } 1551 case MISCREG_HDFAR: // alias for secure DFAR 1552 misc_reg = MISCREG_DFAR_S; 1553 break; 1554 case MISCREG_HIFAR: // alias for secure IFAR 1555 misc_reg = MISCREG_IFAR_S; 1556 break; 1557 case MISCREG_ATS1CPR: 1558 case MISCREG_ATS1CPW: 1559 case MISCREG_ATS1CUR: 1560 case MISCREG_ATS1CUW: 1561 case MISCREG_ATS12NSOPR: 1562 case MISCREG_ATS12NSOPW: 1563 case MISCREG_ATS12NSOUR: 1564 case MISCREG_ATS12NSOUW: 1565 case MISCREG_ATS1HR: 1566 case MISCREG_ATS1HW: 1567 { 1568 Request::Flags flags = 0; 1569 BaseTLB::Mode mode = BaseTLB::Read; 1570 TLB::ArmTranslationType tranType = TLB::NormalTran; 1571 Fault fault; 1572 switch(misc_reg) { 1573 case MISCREG_ATS1CPR: 1574 flags = TLB::MustBeOne; 1575 tranType = TLB::S1CTran; 1576 mode = BaseTLB::Read; 1577 break; 1578 case MISCREG_ATS1CPW: 1579 flags = TLB::MustBeOne; 1580 tranType = TLB::S1CTran; 1581 mode = BaseTLB::Write; 1582 break; 1583 case MISCREG_ATS1CUR: 1584 flags = TLB::MustBeOne | TLB::UserMode; 1585 tranType = TLB::S1CTran; 1586 mode = BaseTLB::Read; 1587 break; 1588 case MISCREG_ATS1CUW: 1589 flags = TLB::MustBeOne | TLB::UserMode; 1590 tranType = TLB::S1CTran; 1591 mode = BaseTLB::Write; 1592 break; 1593 case MISCREG_ATS12NSOPR: 1594 if (!haveSecurity) 1595 panic("Security Extensions required for ATS12NSOPR"); 1596 flags = TLB::MustBeOne; 1597 tranType = TLB::S1S2NsTran; 1598 mode = BaseTLB::Read; 1599 break; 1600 case MISCREG_ATS12NSOPW: 1601 if (!haveSecurity) 1602 panic("Security Extensions required for ATS12NSOPW"); 1603 flags = TLB::MustBeOne; 1604 tranType = TLB::S1S2NsTran; 1605 mode = BaseTLB::Write; 1606 break; 1607 case MISCREG_ATS12NSOUR: 1608 if (!haveSecurity) 1609 panic("Security Extensions required for ATS12NSOUR"); 1610 flags = TLB::MustBeOne | TLB::UserMode; 1611 tranType = TLB::S1S2NsTran; 1612 mode = BaseTLB::Read; 1613 break; 1614 case MISCREG_ATS12NSOUW: 1615 if (!haveSecurity) 1616 panic("Security Extensions required for ATS12NSOUW"); 1617 flags = TLB::MustBeOne | TLB::UserMode; 1618 tranType = TLB::S1S2NsTran; 1619 mode = BaseTLB::Write; 1620 break; 1621 case MISCREG_ATS1HR: // only really useful from secure mode. 1622 flags = TLB::MustBeOne; 1623 tranType = TLB::HypMode; 1624 mode = BaseTLB::Read; 1625 break; 1626 case MISCREG_ATS1HW: 1627 flags = TLB::MustBeOne; 1628 tranType = TLB::HypMode; 1629 mode = BaseTLB::Write; 1630 break; 1631 } 1632 // If we're in timing mode then doing the translation in 1633 // functional mode then we're slightly distorting performance 1634 // results obtained from simulations. The translation should be 1635 // done in the same mode the core is running in. NOTE: This 1636 // can't be an atomic translation because that causes problems 1637 // with unexpected atomic snoop requests. 1638 warn("Translating via %s in functional mode! Fix Me!\n", 1639 miscRegName[misc_reg]); 1640 1641 auto req = std::make_shared<Request>( 1642 0, val, 0, flags, Request::funcMasterId, 1643 tc->pcState().pc(), tc->contextId()); 1644 1645 fault = getDTBPtr(tc)->translateFunctional( 1646 req, tc, mode, tranType); 1647 1648 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1649 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1650 1651 MiscReg newVal; 1652 if (fault == NoFault) { 1653 Addr paddr = req->getPaddr(); 1654 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1655 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1656 newVal = (paddr & mask(39, 12)) | 1657 (getDTBPtr(tc)->getAttr()); 1658 } else { 1659 newVal = (paddr & 0xfffff000) | 1660 (getDTBPtr(tc)->getAttr()); 1661 } 1662 DPRINTF(MiscRegs, 1663 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1664 val, newVal); 1665 } else { 1666 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1667 armFault->update(tc); 1668 // Set fault bit and FSR 1669 FSR fsr = armFault->getFsr(tc); 1670 1671 newVal = ((fsr >> 9) & 1) << 11; 1672 if (newVal) { 1673 // LPAE - rearange fault status 1674 newVal |= ((fsr >> 0) & 0x3f) << 1; 1675 } else { 1676 // VMSA - rearange fault status 1677 newVal |= ((fsr >> 0) & 0xf) << 1; 1678 newVal |= ((fsr >> 10) & 0x1) << 5; 1679 newVal |= ((fsr >> 12) & 0x1) << 6; 1680 } 1681 newVal |= 0x1; // F bit 1682 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1683 newVal |= armFault->isStage2() ? 0x200 : 0; 1684 DPRINTF(MiscRegs, 1685 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1686 val, fsr, newVal); 1687 } 1688 setMiscRegNoEffect(MISCREG_PAR, newVal); 1689 return; 1690 } 1691 case MISCREG_TTBCR: 1692 { 1693 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1694 const uint32_t ones = (uint32_t)(-1); 1695 TTBCR ttbcrMask = 0; 1696 TTBCR ttbcrNew = newVal; 1697 1698 // ARM DDI 0406C.b, ARMv7-32 1699 ttbcrMask.n = ones; // T0SZ 1700 if (haveSecurity) { 1701 ttbcrMask.pd0 = ones; 1702 ttbcrMask.pd1 = ones; 1703 } 1704 ttbcrMask.epd0 = ones; 1705 ttbcrMask.irgn0 = ones; 1706 ttbcrMask.orgn0 = ones; 1707 ttbcrMask.sh0 = ones; 1708 ttbcrMask.ps = ones; // T1SZ 1709 ttbcrMask.a1 = ones; 1710 ttbcrMask.epd1 = ones; 1711 ttbcrMask.irgn1 = ones; 1712 ttbcrMask.orgn1 = ones; 1713 ttbcrMask.sh1 = ones; 1714 if (haveLPAE) 1715 ttbcrMask.eae = ones; 1716 1717 if (haveLPAE && ttbcrNew.eae) { 1718 newVal = newVal & ttbcrMask; 1719 } else { 1720 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1721 } 1722 // Invalidate TLB MiscReg 1723 getITBPtr(tc)->invalidateMiscReg(); 1724 getDTBPtr(tc)->invalidateMiscReg(); 1725 break; 1726 } 1727 case MISCREG_TTBR0: 1728 case MISCREG_TTBR1: 1729 { 1730 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1731 if (haveLPAE) { 1732 if (ttbcr.eae) { 1733 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1734 // ARMv8 AArch32 bit 63-56 only 1735 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1736 newVal = (newVal & (~ttbrMask)); 1737 } 1738 } 1739 // Invalidate TLB MiscReg 1740 getITBPtr(tc)->invalidateMiscReg(); 1741 getDTBPtr(tc)->invalidateMiscReg(); 1742 break; 1743 } 1744 case MISCREG_SCTLR_EL1: 1745 case MISCREG_CONTEXTIDR: 1746 case MISCREG_PRRR: 1747 case MISCREG_NMRR: 1748 case MISCREG_MAIR0: 1749 case MISCREG_MAIR1: 1750 case MISCREG_DACR: 1751 case MISCREG_VTTBR: 1752 case MISCREG_SCR_EL3: 1753 case MISCREG_HCR_EL2: 1754 case MISCREG_TCR_EL1: 1755 case MISCREG_TCR_EL2: 1756 case MISCREG_TCR_EL3: 1757 case MISCREG_SCTLR_EL2: 1758 case MISCREG_SCTLR_EL3: 1759 case MISCREG_HSCTLR: 1760 case MISCREG_TTBR0_EL1: 1761 case MISCREG_TTBR1_EL1: 1762 case MISCREG_TTBR0_EL2: 1763 case MISCREG_TTBR1_EL2: 1764 case MISCREG_TTBR0_EL3: 1765 getITBPtr(tc)->invalidateMiscReg(); 1766 getDTBPtr(tc)->invalidateMiscReg(); 1767 break; 1768 case MISCREG_NZCV: 1769 { 1770 CPSR cpsr = val; 1771 1772 tc->setCCReg(CCREG_NZ, cpsr.nz); 1773 tc->setCCReg(CCREG_C, cpsr.c); 1774 tc->setCCReg(CCREG_V, cpsr.v); 1775 } 1776 break; 1777 case MISCREG_DAIF: 1778 { 1779 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1780 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1781 newVal = cpsr; 1782 misc_reg = MISCREG_CPSR; 1783 } 1784 break; 1785 case MISCREG_SP_EL0: 1786 tc->setIntReg(INTREG_SP0, newVal); 1787 break; 1788 case MISCREG_SP_EL1: 1789 tc->setIntReg(INTREG_SP1, newVal); 1790 break; 1791 case MISCREG_SP_EL2: 1792 tc->setIntReg(INTREG_SP2, newVal); 1793 break; 1794 case MISCREG_SPSEL: 1795 { 1796 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1797 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1798 newVal = cpsr; 1799 misc_reg = MISCREG_CPSR; 1800 } 1801 break; 1802 case MISCREG_CURRENTEL: 1803 { 1804 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1805 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1806 newVal = cpsr; 1807 misc_reg = MISCREG_CPSR; 1808 } 1809 break; 1810 case MISCREG_AT_S1E1R_Xt: 1811 case MISCREG_AT_S1E1W_Xt: 1812 case MISCREG_AT_S1E0R_Xt: 1813 case MISCREG_AT_S1E0W_Xt: 1814 case MISCREG_AT_S1E2R_Xt: 1815 case MISCREG_AT_S1E2W_Xt: 1816 case MISCREG_AT_S12E1R_Xt: 1817 case MISCREG_AT_S12E1W_Xt: 1818 case MISCREG_AT_S12E0R_Xt: 1819 case MISCREG_AT_S12E0W_Xt: 1820 case MISCREG_AT_S1E3R_Xt: 1821 case MISCREG_AT_S1E3W_Xt: 1822 { 1823 RequestPtr req = std::make_shared<Request>(); 1824 Request::Flags flags = 0; 1825 BaseTLB::Mode mode = BaseTLB::Read; 1826 TLB::ArmTranslationType tranType = TLB::NormalTran; 1827 Fault fault; 1828 switch(misc_reg) { 1829 case MISCREG_AT_S1E1R_Xt: 1830 flags = TLB::MustBeOne; 1831 tranType = TLB::S1E1Tran; 1832 mode = BaseTLB::Read; 1833 break; 1834 case MISCREG_AT_S1E1W_Xt: 1835 flags = TLB::MustBeOne; 1836 tranType = TLB::S1E1Tran; 1837 mode = BaseTLB::Write; 1838 break; 1839 case MISCREG_AT_S1E0R_Xt: 1840 flags = TLB::MustBeOne | TLB::UserMode; 1841 tranType = TLB::S1E0Tran; 1842 mode = BaseTLB::Read; 1843 break; 1844 case MISCREG_AT_S1E0W_Xt: 1845 flags = TLB::MustBeOne | TLB::UserMode; 1846 tranType = TLB::S1E0Tran; 1847 mode = BaseTLB::Write; 1848 break; 1849 case MISCREG_AT_S1E2R_Xt: 1850 flags = TLB::MustBeOne; 1851 tranType = TLB::S1E2Tran; 1852 mode = BaseTLB::Read; 1853 break; 1854 case MISCREG_AT_S1E2W_Xt: 1855 flags = TLB::MustBeOne; 1856 tranType = TLB::S1E2Tran; 1857 mode = BaseTLB::Write; 1858 break; 1859 case MISCREG_AT_S12E0R_Xt: 1860 flags = TLB::MustBeOne | TLB::UserMode; 1861 tranType = TLB::S12E0Tran; 1862 mode = BaseTLB::Read; 1863 break; 1864 case MISCREG_AT_S12E0W_Xt: 1865 flags = TLB::MustBeOne | TLB::UserMode; 1866 tranType = TLB::S12E0Tran; 1867 mode = BaseTLB::Write; 1868 break; 1869 case MISCREG_AT_S12E1R_Xt: 1870 flags = TLB::MustBeOne; 1871 tranType = TLB::S12E1Tran; 1872 mode = BaseTLB::Read; 1873 break; 1874 case MISCREG_AT_S12E1W_Xt: 1875 flags = TLB::MustBeOne; 1876 tranType = TLB::S12E1Tran; 1877 mode = BaseTLB::Write; 1878 break; 1879 case MISCREG_AT_S1E3R_Xt: 1880 flags = TLB::MustBeOne; 1881 tranType = TLB::S1E3Tran; 1882 mode = BaseTLB::Read; 1883 break; 1884 case MISCREG_AT_S1E3W_Xt: 1885 flags = TLB::MustBeOne; 1886 tranType = TLB::S1E3Tran; 1887 mode = BaseTLB::Write; 1888 break; 1889 } 1890 // If we're in timing mode then doing the translation in 1891 // functional mode then we're slightly distorting performance 1892 // results obtained from simulations. The translation should be 1893 // done in the same mode the core is running in. NOTE: This 1894 // can't be an atomic translation because that causes problems 1895 // with unexpected atomic snoop requests. 1896 warn("Translating via %s in functional mode! Fix Me!\n", 1897 miscRegName[misc_reg]); 1898 1899 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1900 tc->pcState().pc()); 1901 req->setContext(tc->contextId()); 1902 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1903 tranType); 1904 1905 MiscReg newVal; 1906 if (fault == NoFault) { 1907 Addr paddr = req->getPaddr(); 1908 uint64_t attr = getDTBPtr(tc)->getAttr(); 1909 uint64_t attr1 = attr >> 56; 1910 if (!attr1 || attr1 ==0x44) { 1911 attr |= 0x100; 1912 attr &= ~ uint64_t(0x80); 1913 } 1914 newVal = (paddr & mask(47, 12)) | attr; 1915 DPRINTF(MiscRegs, 1916 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1917 val, newVal); 1918 } else { 1919 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1920 armFault->update(tc); 1921 // Set fault bit and FSR 1922 FSR fsr = armFault->getFsr(tc); 1923 1924 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1925 if (cpsr.width) { // AArch32 1926 newVal = ((fsr >> 9) & 1) << 11; 1927 // rearrange fault status 1928 newVal |= ((fsr >> 0) & 0x3f) << 1; 1929 newVal |= 0x1; // F bit 1930 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1931 newVal |= armFault->isStage2() ? 0x200 : 0; 1932 } else { // AArch64 1933 newVal = 1; // F bit 1934 newVal |= fsr << 1; // FST 1935 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1936 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1937 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1938 newVal |= 1 << 11; // RES1 1939 } 1940 DPRINTF(MiscRegs, 1941 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1942 val, fsr, newVal); 1943 } 1944 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1945 return; 1946 } 1947 case MISCREG_SPSR_EL3: 1948 case MISCREG_SPSR_EL2: 1949 case MISCREG_SPSR_EL1: 1950 // Force bits 23:21 to 0 1951 newVal = val & ~(0x7 << 21); 1952 break; 1953 case MISCREG_L2CTLR: 1954 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1955 miscRegName[misc_reg], uint32_t(val)); 1956 break; 1957 1958 // Generic Timer registers 1959 case MISCREG_CNTHV_CTL_EL2: 1960 case MISCREG_CNTHV_CVAL_EL2: 1961 case MISCREG_CNTHV_TVAL_EL2: 1962 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1963 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1964 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1965 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1966 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1967 break;
| 713 default: 714 break; 715 716 } 717 return readMiscRegNoEffect(misc_reg); 718} 719 720void 721ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 722{ 723 assert(misc_reg < NumMiscRegs); 724 725 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 726 const auto &map = getMiscIndices(misc_reg); 727 int lower = map.first, upper = map.second; 728 729 auto v = (val & ~reg.wi()) | reg.rao(); 730 if (upper > 0) { 731 miscRegs[lower] = bits(v, 31, 0); 732 miscRegs[upper] = bits(v, 63, 32); 733 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 734 misc_reg, lower, upper, v); 735 } else { 736 miscRegs[lower] = v; 737 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 738 misc_reg, lower, v); 739 } 740} 741 742void 743ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 744{ 745 746 MiscReg newVal = val; 747 bool secure_lookup; 748 SCR scr; 749 750 if (misc_reg == MISCREG_CPSR) { 751 updateRegMap(val); 752 753 754 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 755 int old_mode = old_cpsr.mode; 756 CPSR cpsr = val; 757 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 758 getITBPtr(tc)->invalidateMiscReg(); 759 getDTBPtr(tc)->invalidateMiscReg(); 760 } 761 762 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 763 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 764 PCState pc = tc->pcState(); 765 pc.nextThumb(cpsr.t); 766 pc.nextJazelle(cpsr.j); 767 pc.illegalExec(cpsr.il == 1); 768 769 // Follow slightly different semantics if a CheckerCPU object 770 // is connected 771 CheckerCPU *checker = tc->getCheckerCpuPtr(); 772 if (checker) { 773 tc->pcStateNoRecord(pc); 774 } else { 775 tc->pcState(pc); 776 } 777 } else { 778#ifndef NDEBUG 779 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 780 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 781 warn("Unimplemented system register %s write with %#x.\n", 782 miscRegName[misc_reg], val); 783 else 784 panic("Unimplemented system register %s write with %#x.\n", 785 miscRegName[misc_reg], val); 786 } 787#endif 788 switch (unflattenMiscReg(misc_reg)) { 789 case MISCREG_CPACR: 790 { 791 792 const uint32_t ones = (uint32_t)(-1); 793 CPACR cpacrMask = 0; 794 // Only cp10, cp11, and ase are implemented, nothing else should 795 // be writable 796 cpacrMask.cp10 = ones; 797 cpacrMask.cp11 = ones; 798 cpacrMask.asedis = ones; 799 800 // Security Extensions may limit the writability of CPACR 801 if (haveSecurity) { 802 scr = readMiscRegNoEffect(MISCREG_SCR); 803 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 804 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 805 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 806 // NB: Skipping the full loop, here 807 if (!nsacr.cp10) cpacrMask.cp10 = 0; 808 if (!nsacr.cp11) cpacrMask.cp11 = 0; 809 } 810 } 811 812 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 813 newVal &= cpacrMask; 814 newVal |= old_val & ~cpacrMask; 815 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 816 miscRegName[misc_reg], newVal); 817 } 818 break; 819 case MISCREG_CPTR_EL2: 820 { 821 const uint32_t ones = (uint32_t)(-1); 822 CPTR cptrMask = 0; 823 cptrMask.tcpac = ones; 824 cptrMask.tta = ones; 825 cptrMask.tfp = ones; 826 newVal &= cptrMask; 827 cptrMask = 0; 828 cptrMask.res1_13_12_el2 = ones; 829 cptrMask.res1_9_0_el2 = ones; 830 newVal |= cptrMask; 831 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 832 miscRegName[misc_reg], newVal); 833 } 834 break; 835 case MISCREG_CPTR_EL3: 836 { 837 const uint32_t ones = (uint32_t)(-1); 838 CPTR cptrMask = 0; 839 cptrMask.tcpac = ones; 840 cptrMask.tta = ones; 841 cptrMask.tfp = ones; 842 newVal &= cptrMask; 843 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 844 miscRegName[misc_reg], newVal); 845 } 846 break; 847 case MISCREG_CSSELR: 848 warn_once("The csselr register isn't implemented.\n"); 849 return; 850 851 case MISCREG_DC_ZVA_Xt: 852 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 853 return; 854 855 case MISCREG_FPSCR: 856 { 857 const uint32_t ones = (uint32_t)(-1); 858 FPSCR fpscrMask = 0; 859 fpscrMask.ioc = ones; 860 fpscrMask.dzc = ones; 861 fpscrMask.ofc = ones; 862 fpscrMask.ufc = ones; 863 fpscrMask.ixc = ones; 864 fpscrMask.idc = ones; 865 fpscrMask.ioe = ones; 866 fpscrMask.dze = ones; 867 fpscrMask.ofe = ones; 868 fpscrMask.ufe = ones; 869 fpscrMask.ixe = ones; 870 fpscrMask.ide = ones; 871 fpscrMask.len = ones; 872 fpscrMask.stride = ones; 873 fpscrMask.rMode = ones; 874 fpscrMask.fz = ones; 875 fpscrMask.dn = ones; 876 fpscrMask.ahp = ones; 877 fpscrMask.qc = ones; 878 fpscrMask.v = ones; 879 fpscrMask.c = ones; 880 fpscrMask.z = ones; 881 fpscrMask.n = ones; 882 newVal = (newVal & (uint32_t)fpscrMask) | 883 (readMiscRegNoEffect(MISCREG_FPSCR) & 884 ~(uint32_t)fpscrMask); 885 tc->getDecoderPtr()->setContext(newVal); 886 } 887 break; 888 case MISCREG_FPSR: 889 { 890 const uint32_t ones = (uint32_t)(-1); 891 FPSCR fpscrMask = 0; 892 fpscrMask.ioc = ones; 893 fpscrMask.dzc = ones; 894 fpscrMask.ofc = ones; 895 fpscrMask.ufc = ones; 896 fpscrMask.ixc = ones; 897 fpscrMask.idc = ones; 898 fpscrMask.qc = ones; 899 fpscrMask.v = ones; 900 fpscrMask.c = ones; 901 fpscrMask.z = ones; 902 fpscrMask.n = ones; 903 newVal = (newVal & (uint32_t)fpscrMask) | 904 (readMiscRegNoEffect(MISCREG_FPSCR) & 905 ~(uint32_t)fpscrMask); 906 misc_reg = MISCREG_FPSCR; 907 } 908 break; 909 case MISCREG_FPCR: 910 { 911 const uint32_t ones = (uint32_t)(-1); 912 FPSCR fpscrMask = 0; 913 fpscrMask.len = ones; 914 fpscrMask.stride = ones; 915 fpscrMask.rMode = ones; 916 fpscrMask.fz = ones; 917 fpscrMask.dn = ones; 918 fpscrMask.ahp = ones; 919 newVal = (newVal & (uint32_t)fpscrMask) | 920 (readMiscRegNoEffect(MISCREG_FPSCR) & 921 ~(uint32_t)fpscrMask); 922 misc_reg = MISCREG_FPSCR; 923 } 924 break; 925 case MISCREG_CPSR_Q: 926 { 927 assert(!(newVal & ~CpsrMaskQ)); 928 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 929 misc_reg = MISCREG_CPSR; 930 } 931 break; 932 case MISCREG_FPSCR_QC: 933 { 934 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 935 (newVal & FpscrQcMask); 936 misc_reg = MISCREG_FPSCR; 937 } 938 break; 939 case MISCREG_FPSCR_EXC: 940 { 941 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 942 (newVal & FpscrExcMask); 943 misc_reg = MISCREG_FPSCR; 944 } 945 break; 946 case MISCREG_FPEXC: 947 { 948 // vfpv3 architecture, section B.6.1 of DDI04068 949 // bit 29 - valid only if fpexc[31] is 0 950 const uint32_t fpexcMask = 0x60000000; 951 newVal = (newVal & fpexcMask) | 952 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 953 } 954 break; 955 case MISCREG_HCR: 956 { 957 if (!haveVirtualization) 958 return; 959 } 960 break; 961 case MISCREG_IFSR: 962 { 963 // ARM ARM (ARM DDI 0406C.b) B4.1.96 964 const uint32_t ifsrMask = 965 mask(31, 13) | mask(11, 11) | mask(8, 6); 966 newVal = newVal & ~ifsrMask; 967 } 968 break; 969 case MISCREG_DFSR: 970 { 971 // ARM ARM (ARM DDI 0406C.b) B4.1.52 972 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 973 newVal = newVal & ~dfsrMask; 974 } 975 break; 976 case MISCREG_AMAIR0: 977 case MISCREG_AMAIR1: 978 { 979 // ARM ARM (ARM DDI 0406C.b) B4.1.5 980 // Valid only with LPAE 981 if (!haveLPAE) 982 return; 983 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 984 } 985 break; 986 case MISCREG_SCR: 987 getITBPtr(tc)->invalidateMiscReg(); 988 getDTBPtr(tc)->invalidateMiscReg(); 989 break; 990 case MISCREG_SCTLR: 991 { 992 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 993 scr = readMiscRegNoEffect(MISCREG_SCR); 994 995 MiscRegIndex sctlr_idx; 996 if (haveSecurity && !highestELIs64 && !scr.ns) { 997 sctlr_idx = MISCREG_SCTLR_S; 998 } else { 999 sctlr_idx = MISCREG_SCTLR_NS; 1000 } 1001 1002 SCTLR sctlr = miscRegs[sctlr_idx]; 1003 SCTLR new_sctlr = newVal; 1004 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1005 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1006 getITBPtr(tc)->invalidateMiscReg(); 1007 getDTBPtr(tc)->invalidateMiscReg(); 1008 } 1009 case MISCREG_MIDR: 1010 case MISCREG_ID_PFR0: 1011 case MISCREG_ID_PFR1: 1012 case MISCREG_ID_DFR0: 1013 case MISCREG_ID_MMFR0: 1014 case MISCREG_ID_MMFR1: 1015 case MISCREG_ID_MMFR2: 1016 case MISCREG_ID_MMFR3: 1017 case MISCREG_ID_ISAR0: 1018 case MISCREG_ID_ISAR1: 1019 case MISCREG_ID_ISAR2: 1020 case MISCREG_ID_ISAR3: 1021 case MISCREG_ID_ISAR4: 1022 case MISCREG_ID_ISAR5: 1023 1024 case MISCREG_MPIDR: 1025 case MISCREG_FPSID: 1026 case MISCREG_TLBTR: 1027 case MISCREG_MVFR0: 1028 case MISCREG_MVFR1: 1029 1030 case MISCREG_ID_AA64AFR0_EL1: 1031 case MISCREG_ID_AA64AFR1_EL1: 1032 case MISCREG_ID_AA64DFR0_EL1: 1033 case MISCREG_ID_AA64DFR1_EL1: 1034 case MISCREG_ID_AA64ISAR0_EL1: 1035 case MISCREG_ID_AA64ISAR1_EL1: 1036 case MISCREG_ID_AA64MMFR0_EL1: 1037 case MISCREG_ID_AA64MMFR1_EL1: 1038 case MISCREG_ID_AA64MMFR2_EL1: 1039 case MISCREG_ID_AA64PFR0_EL1: 1040 case MISCREG_ID_AA64PFR1_EL1: 1041 // ID registers are constants. 1042 return; 1043 1044 // TLB Invalidate All 1045 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1046 { 1047 assert32(tc); 1048 scr = readMiscReg(MISCREG_SCR, tc); 1049 1050 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1051 tlbiOp(tc); 1052 return; 1053 } 1054 // TLB Invalidate All, Inner Shareable 1055 case MISCREG_TLBIALLIS: 1056 { 1057 assert32(tc); 1058 scr = readMiscReg(MISCREG_SCR, tc); 1059 1060 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1061 tlbiOp.broadcast(tc); 1062 return; 1063 } 1064 // Instruction TLB Invalidate All 1065 case MISCREG_ITLBIALL: 1066 { 1067 assert32(tc); 1068 scr = readMiscReg(MISCREG_SCR, tc); 1069 1070 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1071 tlbiOp(tc); 1072 return; 1073 } 1074 // Data TLB Invalidate All 1075 case MISCREG_DTLBIALL: 1076 { 1077 assert32(tc); 1078 scr = readMiscReg(MISCREG_SCR, tc); 1079 1080 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1081 tlbiOp(tc); 1082 return; 1083 } 1084 // TLB Invalidate by VA 1085 // mcr tlbimval(is) is invalidating all matching entries 1086 // regardless of the level of lookup, since in gem5 we cache 1087 // in the tlb the last level of lookup only. 1088 case MISCREG_TLBIMVA: 1089 case MISCREG_TLBIMVAL: 1090 { 1091 assert32(tc); 1092 scr = readMiscReg(MISCREG_SCR, tc); 1093 1094 TLBIMVA tlbiOp(EL1, 1095 haveSecurity && !scr.ns, 1096 mbits(newVal, 31, 12), 1097 bits(newVal, 7,0)); 1098 1099 tlbiOp(tc); 1100 return; 1101 } 1102 // TLB Invalidate by VA, Inner Shareable 1103 case MISCREG_TLBIMVAIS: 1104 case MISCREG_TLBIMVALIS: 1105 { 1106 assert32(tc); 1107 scr = readMiscReg(MISCREG_SCR, tc); 1108 1109 TLBIMVA tlbiOp(EL1, 1110 haveSecurity && !scr.ns, 1111 mbits(newVal, 31, 12), 1112 bits(newVal, 7,0)); 1113 1114 tlbiOp.broadcast(tc); 1115 return; 1116 } 1117 // TLB Invalidate by ASID match 1118 case MISCREG_TLBIASID: 1119 { 1120 assert32(tc); 1121 scr = readMiscReg(MISCREG_SCR, tc); 1122 1123 TLBIASID tlbiOp(EL1, 1124 haveSecurity && !scr.ns, 1125 bits(newVal, 7,0)); 1126 1127 tlbiOp(tc); 1128 return; 1129 } 1130 // TLB Invalidate by ASID match, Inner Shareable 1131 case MISCREG_TLBIASIDIS: 1132 { 1133 assert32(tc); 1134 scr = readMiscReg(MISCREG_SCR, tc); 1135 1136 TLBIASID tlbiOp(EL1, 1137 haveSecurity && !scr.ns, 1138 bits(newVal, 7,0)); 1139 1140 tlbiOp.broadcast(tc); 1141 return; 1142 } 1143 // mcr tlbimvaal(is) is invalidating all matching entries 1144 // regardless of the level of lookup, since in gem5 we cache 1145 // in the tlb the last level of lookup only. 1146 // TLB Invalidate by VA, All ASID 1147 case MISCREG_TLBIMVAA: 1148 case MISCREG_TLBIMVAAL: 1149 { 1150 assert32(tc); 1151 scr = readMiscReg(MISCREG_SCR, tc); 1152 1153 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1154 mbits(newVal, 31,12), false); 1155 1156 tlbiOp(tc); 1157 return; 1158 } 1159 // TLB Invalidate by VA, All ASID, Inner Shareable 1160 case MISCREG_TLBIMVAAIS: 1161 case MISCREG_TLBIMVAALIS: 1162 { 1163 assert32(tc); 1164 scr = readMiscReg(MISCREG_SCR, tc); 1165 1166 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1167 mbits(newVal, 31,12), false); 1168 1169 tlbiOp.broadcast(tc); 1170 return; 1171 } 1172 // mcr tlbimvalh(is) is invalidating all matching entries 1173 // regardless of the level of lookup, since in gem5 we cache 1174 // in the tlb the last level of lookup only. 1175 // TLB Invalidate by VA, Hyp mode 1176 case MISCREG_TLBIMVAH: 1177 case MISCREG_TLBIMVALH: 1178 { 1179 assert32(tc); 1180 scr = readMiscReg(MISCREG_SCR, tc); 1181 1182 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1183 mbits(newVal, 31,12), true); 1184 1185 tlbiOp(tc); 1186 return; 1187 } 1188 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1189 case MISCREG_TLBIMVAHIS: 1190 case MISCREG_TLBIMVALHIS: 1191 { 1192 assert32(tc); 1193 scr = readMiscReg(MISCREG_SCR, tc); 1194 1195 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1196 mbits(newVal, 31,12), true); 1197 1198 tlbiOp.broadcast(tc); 1199 return; 1200 } 1201 // mcr tlbiipas2l(is) is invalidating all matching entries 1202 // regardless of the level of lookup, since in gem5 we cache 1203 // in the tlb the last level of lookup only. 1204 // TLB Invalidate by Intermediate Physical Address, Stage 2 1205 case MISCREG_TLBIIPAS2: 1206 case MISCREG_TLBIIPAS2L: 1207 { 1208 assert32(tc); 1209 scr = readMiscReg(MISCREG_SCR, tc); 1210 1211 TLBIIPA tlbiOp(EL1, 1212 haveSecurity && !scr.ns, 1213 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1214 1215 tlbiOp(tc); 1216 return; 1217 } 1218 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1219 // Inner Shareable 1220 case MISCREG_TLBIIPAS2IS: 1221 case MISCREG_TLBIIPAS2LIS: 1222 { 1223 assert32(tc); 1224 scr = readMiscReg(MISCREG_SCR, tc); 1225 1226 TLBIIPA tlbiOp(EL1, 1227 haveSecurity && !scr.ns, 1228 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1229 1230 tlbiOp.broadcast(tc); 1231 return; 1232 } 1233 // Instruction TLB Invalidate by VA 1234 case MISCREG_ITLBIMVA: 1235 { 1236 assert32(tc); 1237 scr = readMiscReg(MISCREG_SCR, tc); 1238 1239 ITLBIMVA tlbiOp(EL1, 1240 haveSecurity && !scr.ns, 1241 mbits(newVal, 31, 12), 1242 bits(newVal, 7,0)); 1243 1244 tlbiOp(tc); 1245 return; 1246 } 1247 // Data TLB Invalidate by VA 1248 case MISCREG_DTLBIMVA: 1249 { 1250 assert32(tc); 1251 scr = readMiscReg(MISCREG_SCR, tc); 1252 1253 DTLBIMVA tlbiOp(EL1, 1254 haveSecurity && !scr.ns, 1255 mbits(newVal, 31, 12), 1256 bits(newVal, 7,0)); 1257 1258 tlbiOp(tc); 1259 return; 1260 } 1261 // Instruction TLB Invalidate by ASID match 1262 case MISCREG_ITLBIASID: 1263 { 1264 assert32(tc); 1265 scr = readMiscReg(MISCREG_SCR, tc); 1266 1267 ITLBIASID tlbiOp(EL1, 1268 haveSecurity && !scr.ns, 1269 bits(newVal, 7,0)); 1270 1271 tlbiOp(tc); 1272 return; 1273 } 1274 // Data TLB Invalidate by ASID match 1275 case MISCREG_DTLBIASID: 1276 { 1277 assert32(tc); 1278 scr = readMiscReg(MISCREG_SCR, tc); 1279 1280 DTLBIASID tlbiOp(EL1, 1281 haveSecurity && !scr.ns, 1282 bits(newVal, 7,0)); 1283 1284 tlbiOp(tc); 1285 return; 1286 } 1287 // TLB Invalidate All, Non-Secure Non-Hyp 1288 case MISCREG_TLBIALLNSNH: 1289 { 1290 assert32(tc); 1291 1292 TLBIALLN tlbiOp(EL1, false); 1293 tlbiOp(tc); 1294 return; 1295 } 1296 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1297 case MISCREG_TLBIALLNSNHIS: 1298 { 1299 assert32(tc); 1300 1301 TLBIALLN tlbiOp(EL1, false); 1302 tlbiOp.broadcast(tc); 1303 return; 1304 } 1305 // TLB Invalidate All, Hyp mode 1306 case MISCREG_TLBIALLH: 1307 { 1308 assert32(tc); 1309 1310 TLBIALLN tlbiOp(EL1, true); 1311 tlbiOp(tc); 1312 return; 1313 } 1314 // TLB Invalidate All, Hyp mode, Inner Shareable 1315 case MISCREG_TLBIALLHIS: 1316 { 1317 assert32(tc); 1318 1319 TLBIALLN tlbiOp(EL1, true); 1320 tlbiOp.broadcast(tc); 1321 return; 1322 } 1323 // AArch64 TLB Invalidate All, EL3 1324 case MISCREG_TLBI_ALLE3: 1325 { 1326 assert64(tc); 1327 1328 TLBIALL tlbiOp(EL3, true); 1329 tlbiOp(tc); 1330 return; 1331 } 1332 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1333 case MISCREG_TLBI_ALLE3IS: 1334 { 1335 assert64(tc); 1336 1337 TLBIALL tlbiOp(EL3, true); 1338 tlbiOp.broadcast(tc); 1339 return; 1340 } 1341 // @todo: uncomment this to enable Virtualization 1342 // case MISCREG_TLBI_ALLE2IS: 1343 // case MISCREG_TLBI_ALLE2: 1344 // AArch64 TLB Invalidate All, EL1 1345 case MISCREG_TLBI_ALLE1: 1346 case MISCREG_TLBI_VMALLE1: 1347 case MISCREG_TLBI_VMALLS12E1: 1348 // @todo: handle VMID and stage 2 to enable Virtualization 1349 { 1350 assert64(tc); 1351 scr = readMiscReg(MISCREG_SCR, tc); 1352 1353 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1354 tlbiOp(tc); 1355 return; 1356 } 1357 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1358 case MISCREG_TLBI_ALLE1IS: 1359 case MISCREG_TLBI_VMALLE1IS: 1360 case MISCREG_TLBI_VMALLS12E1IS: 1361 // @todo: handle VMID and stage 2 to enable Virtualization 1362 { 1363 assert64(tc); 1364 scr = readMiscReg(MISCREG_SCR, tc); 1365 1366 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1367 tlbiOp.broadcast(tc); 1368 return; 1369 } 1370 // VAEx(IS) and VALEx(IS) are the same because TLBs 1371 // only store entries 1372 // from the last level of translation table walks 1373 // @todo: handle VMID to enable Virtualization 1374 // AArch64 TLB Invalidate by VA, EL3 1375 case MISCREG_TLBI_VAE3_Xt: 1376 case MISCREG_TLBI_VALE3_Xt: 1377 { 1378 assert64(tc); 1379 1380 TLBIMVA tlbiOp(EL3, true, 1381 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1382 0xbeef); 1383 tlbiOp(tc); 1384 return; 1385 } 1386 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1387 case MISCREG_TLBI_VAE3IS_Xt: 1388 case MISCREG_TLBI_VALE3IS_Xt: 1389 { 1390 assert64(tc); 1391 1392 TLBIMVA tlbiOp(EL3, true, 1393 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1394 0xbeef); 1395 1396 tlbiOp.broadcast(tc); 1397 return; 1398 } 1399 // AArch64 TLB Invalidate by VA, EL2 1400 case MISCREG_TLBI_VAE2_Xt: 1401 case MISCREG_TLBI_VALE2_Xt: 1402 { 1403 assert64(tc); 1404 scr = readMiscReg(MISCREG_SCR, tc); 1405 1406 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1407 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1408 0xbeef); 1409 tlbiOp(tc); 1410 return; 1411 } 1412 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1413 case MISCREG_TLBI_VAE2IS_Xt: 1414 case MISCREG_TLBI_VALE2IS_Xt: 1415 { 1416 assert64(tc); 1417 scr = readMiscReg(MISCREG_SCR, tc); 1418 1419 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1420 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1421 0xbeef); 1422 1423 tlbiOp.broadcast(tc); 1424 return; 1425 } 1426 // AArch64 TLB Invalidate by VA, EL1 1427 case MISCREG_TLBI_VAE1_Xt: 1428 case MISCREG_TLBI_VALE1_Xt: 1429 { 1430 assert64(tc); 1431 scr = readMiscReg(MISCREG_SCR, tc); 1432 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1433 bits(newVal, 55, 48); 1434 1435 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1436 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1437 asid); 1438 1439 tlbiOp(tc); 1440 return; 1441 } 1442 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1443 case MISCREG_TLBI_VAE1IS_Xt: 1444 case MISCREG_TLBI_VALE1IS_Xt: 1445 { 1446 assert64(tc); 1447 scr = readMiscReg(MISCREG_SCR, tc); 1448 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1449 bits(newVal, 55, 48); 1450 1451 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1452 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1453 asid); 1454 1455 tlbiOp.broadcast(tc); 1456 return; 1457 } 1458 // AArch64 TLB Invalidate by ASID, EL1 1459 // @todo: handle VMID to enable Virtualization 1460 case MISCREG_TLBI_ASIDE1_Xt: 1461 { 1462 assert64(tc); 1463 scr = readMiscReg(MISCREG_SCR, tc); 1464 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1465 bits(newVal, 55, 48); 1466 1467 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1468 tlbiOp(tc); 1469 return; 1470 } 1471 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1472 case MISCREG_TLBI_ASIDE1IS_Xt: 1473 { 1474 assert64(tc); 1475 scr = readMiscReg(MISCREG_SCR, tc); 1476 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1477 bits(newVal, 55, 48); 1478 1479 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1480 tlbiOp.broadcast(tc); 1481 return; 1482 } 1483 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1484 // entries from the last level of translation table walks 1485 // AArch64 TLB Invalidate by VA, All ASID, EL1 1486 case MISCREG_TLBI_VAAE1_Xt: 1487 case MISCREG_TLBI_VAALE1_Xt: 1488 { 1489 assert64(tc); 1490 scr = readMiscReg(MISCREG_SCR, tc); 1491 1492 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1493 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1494 1495 tlbiOp(tc); 1496 return; 1497 } 1498 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1499 case MISCREG_TLBI_VAAE1IS_Xt: 1500 case MISCREG_TLBI_VAALE1IS_Xt: 1501 { 1502 assert64(tc); 1503 scr = readMiscReg(MISCREG_SCR, tc); 1504 1505 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1506 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1507 1508 tlbiOp.broadcast(tc); 1509 return; 1510 } 1511 // AArch64 TLB Invalidate by Intermediate Physical Address, 1512 // Stage 2, EL1 1513 case MISCREG_TLBI_IPAS2E1_Xt: 1514 case MISCREG_TLBI_IPAS2LE1_Xt: 1515 { 1516 assert64(tc); 1517 scr = readMiscReg(MISCREG_SCR, tc); 1518 1519 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1520 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1521 1522 tlbiOp(tc); 1523 return; 1524 } 1525 // AArch64 TLB Invalidate by Intermediate Physical Address, 1526 // Stage 2, EL1, Inner Shareable 1527 case MISCREG_TLBI_IPAS2E1IS_Xt: 1528 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1529 { 1530 assert64(tc); 1531 scr = readMiscReg(MISCREG_SCR, tc); 1532 1533 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1534 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1535 1536 tlbiOp.broadcast(tc); 1537 return; 1538 } 1539 case MISCREG_ACTLR: 1540 warn("Not doing anything for write of miscreg ACTLR\n"); 1541 break; 1542 1543 case MISCREG_PMXEVTYPER_PMCCFILTR: 1544 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1545 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1546 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1547 pmu->setMiscReg(misc_reg, newVal); 1548 break; 1549 1550 1551 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1552 { 1553 HSTR hstrMask = 0; 1554 hstrMask.tjdbx = 1; 1555 newVal &= ~((uint32_t) hstrMask); 1556 break; 1557 } 1558 case MISCREG_HCPTR: 1559 { 1560 // If a CP bit in NSACR is 0 then the corresponding bit in 1561 // HCPTR is RAO/WI. Same applies to NSASEDIS 1562 secure_lookup = haveSecurity && 1563 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1564 readMiscRegNoEffect(MISCREG_CPSR)); 1565 if (!secure_lookup) { 1566 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1567 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1568 newVal = (newVal & ~mask) | (oldValue & mask); 1569 } 1570 break; 1571 } 1572 case MISCREG_HDFAR: // alias for secure DFAR 1573 misc_reg = MISCREG_DFAR_S; 1574 break; 1575 case MISCREG_HIFAR: // alias for secure IFAR 1576 misc_reg = MISCREG_IFAR_S; 1577 break; 1578 case MISCREG_ATS1CPR: 1579 case MISCREG_ATS1CPW: 1580 case MISCREG_ATS1CUR: 1581 case MISCREG_ATS1CUW: 1582 case MISCREG_ATS12NSOPR: 1583 case MISCREG_ATS12NSOPW: 1584 case MISCREG_ATS12NSOUR: 1585 case MISCREG_ATS12NSOUW: 1586 case MISCREG_ATS1HR: 1587 case MISCREG_ATS1HW: 1588 { 1589 Request::Flags flags = 0; 1590 BaseTLB::Mode mode = BaseTLB::Read; 1591 TLB::ArmTranslationType tranType = TLB::NormalTran; 1592 Fault fault; 1593 switch(misc_reg) { 1594 case MISCREG_ATS1CPR: 1595 flags = TLB::MustBeOne; 1596 tranType = TLB::S1CTran; 1597 mode = BaseTLB::Read; 1598 break; 1599 case MISCREG_ATS1CPW: 1600 flags = TLB::MustBeOne; 1601 tranType = TLB::S1CTran; 1602 mode = BaseTLB::Write; 1603 break; 1604 case MISCREG_ATS1CUR: 1605 flags = TLB::MustBeOne | TLB::UserMode; 1606 tranType = TLB::S1CTran; 1607 mode = BaseTLB::Read; 1608 break; 1609 case MISCREG_ATS1CUW: 1610 flags = TLB::MustBeOne | TLB::UserMode; 1611 tranType = TLB::S1CTran; 1612 mode = BaseTLB::Write; 1613 break; 1614 case MISCREG_ATS12NSOPR: 1615 if (!haveSecurity) 1616 panic("Security Extensions required for ATS12NSOPR"); 1617 flags = TLB::MustBeOne; 1618 tranType = TLB::S1S2NsTran; 1619 mode = BaseTLB::Read; 1620 break; 1621 case MISCREG_ATS12NSOPW: 1622 if (!haveSecurity) 1623 panic("Security Extensions required for ATS12NSOPW"); 1624 flags = TLB::MustBeOne; 1625 tranType = TLB::S1S2NsTran; 1626 mode = BaseTLB::Write; 1627 break; 1628 case MISCREG_ATS12NSOUR: 1629 if (!haveSecurity) 1630 panic("Security Extensions required for ATS12NSOUR"); 1631 flags = TLB::MustBeOne | TLB::UserMode; 1632 tranType = TLB::S1S2NsTran; 1633 mode = BaseTLB::Read; 1634 break; 1635 case MISCREG_ATS12NSOUW: 1636 if (!haveSecurity) 1637 panic("Security Extensions required for ATS12NSOUW"); 1638 flags = TLB::MustBeOne | TLB::UserMode; 1639 tranType = TLB::S1S2NsTran; 1640 mode = BaseTLB::Write; 1641 break; 1642 case MISCREG_ATS1HR: // only really useful from secure mode. 1643 flags = TLB::MustBeOne; 1644 tranType = TLB::HypMode; 1645 mode = BaseTLB::Read; 1646 break; 1647 case MISCREG_ATS1HW: 1648 flags = TLB::MustBeOne; 1649 tranType = TLB::HypMode; 1650 mode = BaseTLB::Write; 1651 break; 1652 } 1653 // If we're in timing mode then doing the translation in 1654 // functional mode then we're slightly distorting performance 1655 // results obtained from simulations. The translation should be 1656 // done in the same mode the core is running in. NOTE: This 1657 // can't be an atomic translation because that causes problems 1658 // with unexpected atomic snoop requests. 1659 warn("Translating via %s in functional mode! Fix Me!\n", 1660 miscRegName[misc_reg]); 1661 1662 auto req = std::make_shared<Request>( 1663 0, val, 0, flags, Request::funcMasterId, 1664 tc->pcState().pc(), tc->contextId()); 1665 1666 fault = getDTBPtr(tc)->translateFunctional( 1667 req, tc, mode, tranType); 1668 1669 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1670 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1671 1672 MiscReg newVal; 1673 if (fault == NoFault) { 1674 Addr paddr = req->getPaddr(); 1675 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1676 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1677 newVal = (paddr & mask(39, 12)) | 1678 (getDTBPtr(tc)->getAttr()); 1679 } else { 1680 newVal = (paddr & 0xfffff000) | 1681 (getDTBPtr(tc)->getAttr()); 1682 } 1683 DPRINTF(MiscRegs, 1684 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1685 val, newVal); 1686 } else { 1687 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1688 armFault->update(tc); 1689 // Set fault bit and FSR 1690 FSR fsr = armFault->getFsr(tc); 1691 1692 newVal = ((fsr >> 9) & 1) << 11; 1693 if (newVal) { 1694 // LPAE - rearange fault status 1695 newVal |= ((fsr >> 0) & 0x3f) << 1; 1696 } else { 1697 // VMSA - rearange fault status 1698 newVal |= ((fsr >> 0) & 0xf) << 1; 1699 newVal |= ((fsr >> 10) & 0x1) << 5; 1700 newVal |= ((fsr >> 12) & 0x1) << 6; 1701 } 1702 newVal |= 0x1; // F bit 1703 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1704 newVal |= armFault->isStage2() ? 0x200 : 0; 1705 DPRINTF(MiscRegs, 1706 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1707 val, fsr, newVal); 1708 } 1709 setMiscRegNoEffect(MISCREG_PAR, newVal); 1710 return; 1711 } 1712 case MISCREG_TTBCR: 1713 { 1714 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1715 const uint32_t ones = (uint32_t)(-1); 1716 TTBCR ttbcrMask = 0; 1717 TTBCR ttbcrNew = newVal; 1718 1719 // ARM DDI 0406C.b, ARMv7-32 1720 ttbcrMask.n = ones; // T0SZ 1721 if (haveSecurity) { 1722 ttbcrMask.pd0 = ones; 1723 ttbcrMask.pd1 = ones; 1724 } 1725 ttbcrMask.epd0 = ones; 1726 ttbcrMask.irgn0 = ones; 1727 ttbcrMask.orgn0 = ones; 1728 ttbcrMask.sh0 = ones; 1729 ttbcrMask.ps = ones; // T1SZ 1730 ttbcrMask.a1 = ones; 1731 ttbcrMask.epd1 = ones; 1732 ttbcrMask.irgn1 = ones; 1733 ttbcrMask.orgn1 = ones; 1734 ttbcrMask.sh1 = ones; 1735 if (haveLPAE) 1736 ttbcrMask.eae = ones; 1737 1738 if (haveLPAE && ttbcrNew.eae) { 1739 newVal = newVal & ttbcrMask; 1740 } else { 1741 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1742 } 1743 // Invalidate TLB MiscReg 1744 getITBPtr(tc)->invalidateMiscReg(); 1745 getDTBPtr(tc)->invalidateMiscReg(); 1746 break; 1747 } 1748 case MISCREG_TTBR0: 1749 case MISCREG_TTBR1: 1750 { 1751 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1752 if (haveLPAE) { 1753 if (ttbcr.eae) { 1754 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1755 // ARMv8 AArch32 bit 63-56 only 1756 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1757 newVal = (newVal & (~ttbrMask)); 1758 } 1759 } 1760 // Invalidate TLB MiscReg 1761 getITBPtr(tc)->invalidateMiscReg(); 1762 getDTBPtr(tc)->invalidateMiscReg(); 1763 break; 1764 } 1765 case MISCREG_SCTLR_EL1: 1766 case MISCREG_CONTEXTIDR: 1767 case MISCREG_PRRR: 1768 case MISCREG_NMRR: 1769 case MISCREG_MAIR0: 1770 case MISCREG_MAIR1: 1771 case MISCREG_DACR: 1772 case MISCREG_VTTBR: 1773 case MISCREG_SCR_EL3: 1774 case MISCREG_HCR_EL2: 1775 case MISCREG_TCR_EL1: 1776 case MISCREG_TCR_EL2: 1777 case MISCREG_TCR_EL3: 1778 case MISCREG_SCTLR_EL2: 1779 case MISCREG_SCTLR_EL3: 1780 case MISCREG_HSCTLR: 1781 case MISCREG_TTBR0_EL1: 1782 case MISCREG_TTBR1_EL1: 1783 case MISCREG_TTBR0_EL2: 1784 case MISCREG_TTBR1_EL2: 1785 case MISCREG_TTBR0_EL3: 1786 getITBPtr(tc)->invalidateMiscReg(); 1787 getDTBPtr(tc)->invalidateMiscReg(); 1788 break; 1789 case MISCREG_NZCV: 1790 { 1791 CPSR cpsr = val; 1792 1793 tc->setCCReg(CCREG_NZ, cpsr.nz); 1794 tc->setCCReg(CCREG_C, cpsr.c); 1795 tc->setCCReg(CCREG_V, cpsr.v); 1796 } 1797 break; 1798 case MISCREG_DAIF: 1799 { 1800 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1801 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1802 newVal = cpsr; 1803 misc_reg = MISCREG_CPSR; 1804 } 1805 break; 1806 case MISCREG_SP_EL0: 1807 tc->setIntReg(INTREG_SP0, newVal); 1808 break; 1809 case MISCREG_SP_EL1: 1810 tc->setIntReg(INTREG_SP1, newVal); 1811 break; 1812 case MISCREG_SP_EL2: 1813 tc->setIntReg(INTREG_SP2, newVal); 1814 break; 1815 case MISCREG_SPSEL: 1816 { 1817 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1818 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1819 newVal = cpsr; 1820 misc_reg = MISCREG_CPSR; 1821 } 1822 break; 1823 case MISCREG_CURRENTEL: 1824 { 1825 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1826 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1827 newVal = cpsr; 1828 misc_reg = MISCREG_CPSR; 1829 } 1830 break; 1831 case MISCREG_AT_S1E1R_Xt: 1832 case MISCREG_AT_S1E1W_Xt: 1833 case MISCREG_AT_S1E0R_Xt: 1834 case MISCREG_AT_S1E0W_Xt: 1835 case MISCREG_AT_S1E2R_Xt: 1836 case MISCREG_AT_S1E2W_Xt: 1837 case MISCREG_AT_S12E1R_Xt: 1838 case MISCREG_AT_S12E1W_Xt: 1839 case MISCREG_AT_S12E0R_Xt: 1840 case MISCREG_AT_S12E0W_Xt: 1841 case MISCREG_AT_S1E3R_Xt: 1842 case MISCREG_AT_S1E3W_Xt: 1843 { 1844 RequestPtr req = std::make_shared<Request>(); 1845 Request::Flags flags = 0; 1846 BaseTLB::Mode mode = BaseTLB::Read; 1847 TLB::ArmTranslationType tranType = TLB::NormalTran; 1848 Fault fault; 1849 switch(misc_reg) { 1850 case MISCREG_AT_S1E1R_Xt: 1851 flags = TLB::MustBeOne; 1852 tranType = TLB::S1E1Tran; 1853 mode = BaseTLB::Read; 1854 break; 1855 case MISCREG_AT_S1E1W_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S1E1Tran; 1858 mode = BaseTLB::Write; 1859 break; 1860 case MISCREG_AT_S1E0R_Xt: 1861 flags = TLB::MustBeOne | TLB::UserMode; 1862 tranType = TLB::S1E0Tran; 1863 mode = BaseTLB::Read; 1864 break; 1865 case MISCREG_AT_S1E0W_Xt: 1866 flags = TLB::MustBeOne | TLB::UserMode; 1867 tranType = TLB::S1E0Tran; 1868 mode = BaseTLB::Write; 1869 break; 1870 case MISCREG_AT_S1E2R_Xt: 1871 flags = TLB::MustBeOne; 1872 tranType = TLB::S1E2Tran; 1873 mode = BaseTLB::Read; 1874 break; 1875 case MISCREG_AT_S1E2W_Xt: 1876 flags = TLB::MustBeOne; 1877 tranType = TLB::S1E2Tran; 1878 mode = BaseTLB::Write; 1879 break; 1880 case MISCREG_AT_S12E0R_Xt: 1881 flags = TLB::MustBeOne | TLB::UserMode; 1882 tranType = TLB::S12E0Tran; 1883 mode = BaseTLB::Read; 1884 break; 1885 case MISCREG_AT_S12E0W_Xt: 1886 flags = TLB::MustBeOne | TLB::UserMode; 1887 tranType = TLB::S12E0Tran; 1888 mode = BaseTLB::Write; 1889 break; 1890 case MISCREG_AT_S12E1R_Xt: 1891 flags = TLB::MustBeOne; 1892 tranType = TLB::S12E1Tran; 1893 mode = BaseTLB::Read; 1894 break; 1895 case MISCREG_AT_S12E1W_Xt: 1896 flags = TLB::MustBeOne; 1897 tranType = TLB::S12E1Tran; 1898 mode = BaseTLB::Write; 1899 break; 1900 case MISCREG_AT_S1E3R_Xt: 1901 flags = TLB::MustBeOne; 1902 tranType = TLB::S1E3Tran; 1903 mode = BaseTLB::Read; 1904 break; 1905 case MISCREG_AT_S1E3W_Xt: 1906 flags = TLB::MustBeOne; 1907 tranType = TLB::S1E3Tran; 1908 mode = BaseTLB::Write; 1909 break; 1910 } 1911 // If we're in timing mode then doing the translation in 1912 // functional mode then we're slightly distorting performance 1913 // results obtained from simulations. The translation should be 1914 // done in the same mode the core is running in. NOTE: This 1915 // can't be an atomic translation because that causes problems 1916 // with unexpected atomic snoop requests. 1917 warn("Translating via %s in functional mode! Fix Me!\n", 1918 miscRegName[misc_reg]); 1919 1920 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1921 tc->pcState().pc()); 1922 req->setContext(tc->contextId()); 1923 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1924 tranType); 1925 1926 MiscReg newVal; 1927 if (fault == NoFault) { 1928 Addr paddr = req->getPaddr(); 1929 uint64_t attr = getDTBPtr(tc)->getAttr(); 1930 uint64_t attr1 = attr >> 56; 1931 if (!attr1 || attr1 ==0x44) { 1932 attr |= 0x100; 1933 attr &= ~ uint64_t(0x80); 1934 } 1935 newVal = (paddr & mask(47, 12)) | attr; 1936 DPRINTF(MiscRegs, 1937 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1938 val, newVal); 1939 } else { 1940 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1941 armFault->update(tc); 1942 // Set fault bit and FSR 1943 FSR fsr = armFault->getFsr(tc); 1944 1945 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1946 if (cpsr.width) { // AArch32 1947 newVal = ((fsr >> 9) & 1) << 11; 1948 // rearrange fault status 1949 newVal |= ((fsr >> 0) & 0x3f) << 1; 1950 newVal |= 0x1; // F bit 1951 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1952 newVal |= armFault->isStage2() ? 0x200 : 0; 1953 } else { // AArch64 1954 newVal = 1; // F bit 1955 newVal |= fsr << 1; // FST 1956 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1957 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1958 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1959 newVal |= 1 << 11; // RES1 1960 } 1961 DPRINTF(MiscRegs, 1962 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1963 val, fsr, newVal); 1964 } 1965 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1966 return; 1967 } 1968 case MISCREG_SPSR_EL3: 1969 case MISCREG_SPSR_EL2: 1970 case MISCREG_SPSR_EL1: 1971 // Force bits 23:21 to 0 1972 newVal = val & ~(0x7 << 21); 1973 break; 1974 case MISCREG_L2CTLR: 1975 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1976 miscRegName[misc_reg], uint32_t(val)); 1977 break; 1978 1979 // Generic Timer registers 1980 case MISCREG_CNTHV_CTL_EL2: 1981 case MISCREG_CNTHV_CVAL_EL2: 1982 case MISCREG_CNTHV_TVAL_EL2: 1983 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1984 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1985 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1986 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1987 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1988 break;
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