1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58
59ISA::ISA(Params *p)
60 : SimObject(p),
61 system(NULL),
62 _decoderFlavour(p->decoderFlavour),
63 _vecRegRenameMode(p->vecRegRenameMode),
64 pmu(p->pmu)
65{
66 miscRegs[MISCREG_SCTLR_RST] = 0;
67
68 // Hook up a dummy device if we haven't been configured with a
69 // real PMU. By using a dummy device, we don't need to check that
70 // the PMU exist every time we try to access a PMU register.
71 if (!pmu)
72 pmu = &dummyDevice;
73
74 // Give all ISA devices a pointer to this ISA
75 pmu->setISA(this);
76
77 system = dynamic_cast<ArmSystem *>(p->system);
78
79 // Cache system-level properties
80 if (FullSystem && system) {
81 highestELIs64 = system->highestELIs64();
82 haveSecurity = system->haveSecurity();
83 haveLPAE = system->haveLPAE();
84 haveVirtualization = system->haveVirtualization();
85 haveLargeAsid64 = system->haveLargeAsid64();
86 physAddrRange64 = system->physAddrRange64();
87 } else {
88 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
89 haveSecurity = haveLPAE = haveVirtualization = false;
90 haveLargeAsid64 = false;
91 physAddrRange64 = 32; // dummy value
92 }
93
94 initializeMiscRegMetadata();
95 preUnflattenMiscReg();
96
97 clear();
98}
99
100std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
101
102const ArmISAParams *
103ISA::params() const
104{
105 return dynamic_cast<const Params *>(_params);
106}
107
108void
109ISA::clear()
110{
111 const Params *p(params());
112
113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
114 memset(miscRegs, 0, sizeof(miscRegs));
115
116 // Initialize configurable default values
117 miscRegs[MISCREG_MIDR] = p->midr;
118 miscRegs[MISCREG_MIDR_EL1] = p->midr;
119 miscRegs[MISCREG_VPIDR] = p->midr;
120
121 if (FullSystem && system->highestELIs64()) {
122 // Initialize AArch64 state
123 clear64(p);
124 return;
125 }
126
127 // Initialize AArch32 state...
128
129 CPSR cpsr = 0;
130 cpsr.mode = MODE_USER;
131 miscRegs[MISCREG_CPSR] = cpsr;
132 updateRegMap(cpsr);
133
134 SCTLR sctlr = 0;
135 sctlr.te = (bool) sctlr_rst.te;
136 sctlr.nmfi = (bool) sctlr_rst.nmfi;
137 sctlr.v = (bool) sctlr_rst.v;
138 sctlr.u = 1;
139 sctlr.xp = 1;
140 sctlr.rao2 = 1;
141 sctlr.rao3 = 1;
142 sctlr.rao4 = 0xf; // SCTLR[6:3]
143 sctlr.uci = 1;
144 sctlr.dze = 1;
145 miscRegs[MISCREG_SCTLR_NS] = sctlr;
146 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
147 miscRegs[MISCREG_HCPTR] = 0;
148
149 // Start with an event in the mailbox
150 miscRegs[MISCREG_SEV_MAILBOX] = 1;
151
152 // Separate Instruction and Data TLBs
153 miscRegs[MISCREG_TLBTR] = 1;
154
155 MVFR0 mvfr0 = 0;
156 mvfr0.advSimdRegisters = 2;
157 mvfr0.singlePrecision = 2;
158 mvfr0.doublePrecision = 2;
159 mvfr0.vfpExceptionTrapping = 0;
160 mvfr0.divide = 1;
161 mvfr0.squareRoot = 1;
162 mvfr0.shortVectors = 1;
163 mvfr0.roundingModes = 1;
164 miscRegs[MISCREG_MVFR0] = mvfr0;
165
166 MVFR1 mvfr1 = 0;
167 mvfr1.flushToZero = 1;
168 mvfr1.defaultNaN = 1;
169 mvfr1.advSimdLoadStore = 1;
170 mvfr1.advSimdInteger = 1;
171 mvfr1.advSimdSinglePrecision = 1;
172 mvfr1.advSimdHalfPrecision = 1;
173 mvfr1.vfpHalfPrecision = 1;
174 miscRegs[MISCREG_MVFR1] = mvfr1;
175
176 // Reset values of PRRR and NMRR are implementation dependent
177
178 // @todo: PRRR and NMRR in secure state?
179 miscRegs[MISCREG_PRRR_NS] =
180 (1 << 19) | // 19
181 (0 << 18) | // 18
182 (0 << 17) | // 17
183 (1 << 16) | // 16
184 (2 << 14) | // 15:14
185 (0 << 12) | // 13:12
186 (2 << 10) | // 11:10
187 (2 << 8) | // 9:8
188 (2 << 6) | // 7:6
189 (2 << 4) | // 5:4
190 (1 << 2) | // 3:2
191 0; // 1:0
192 miscRegs[MISCREG_NMRR_NS] =
193 (1 << 30) | // 31:30
194 (0 << 26) | // 27:26
195 (0 << 24) | // 25:24
196 (3 << 22) | // 23:22
197 (2 << 20) | // 21:20
198 (0 << 18) | // 19:18
199 (0 << 16) | // 17:16
200 (1 << 14) | // 15:14
201 (0 << 12) | // 13:12
202 (2 << 10) | // 11:10
203 (0 << 8) | // 9:8
204 (3 << 6) | // 7:6
205 (2 << 4) | // 5:4
206 (0 << 2) | // 3:2
207 0; // 1:0
208
209 miscRegs[MISCREG_CPACR] = 0;
210
211 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
212 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
213 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
214 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
215
216 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
217 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
218 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
219 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
220 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
221 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
222
223 miscRegs[MISCREG_FPSID] = p->fpsid;
224
225 if (haveLPAE) {
226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
227 ttbcr.eae = 0;
228 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
229 // Enforce consistency with system-level settings
230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
231 }
232
233 if (haveSecurity) {
234 miscRegs[MISCREG_SCTLR_S] = sctlr;
235 miscRegs[MISCREG_SCR] = 0;
236 miscRegs[MISCREG_VBAR_S] = 0;
237 } else {
238 // we're always non-secure
239 miscRegs[MISCREG_SCR] = 1;
240 }
241
242 //XXX We need to initialize the rest of the state.
243}
244
245void
246ISA::clear64(const ArmISAParams *p)
247{
248 CPSR cpsr = 0;
249 Addr rvbar = system->resetAddr64();
250 switch (system->highestEL()) {
251 // Set initial EL to highest implemented EL using associated stack
252 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
253 // value
254 case EL3:
255 cpsr.mode = MODE_EL3H;
256 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
257 break;
258 case EL2:
259 cpsr.mode = MODE_EL2H;
260 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
261 break;
262 case EL1:
263 cpsr.mode = MODE_EL1H;
264 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
265 break;
266 default:
267 panic("Invalid highest implemented exception level");
268 break;
269 }
270
271 // Initialize rest of CPSR
272 cpsr.daif = 0xf; // Mask all interrupts
273 cpsr.ss = 0;
274 cpsr.il = 0;
275 miscRegs[MISCREG_CPSR] = cpsr;
276 updateRegMap(cpsr);
277
278 // Initialize other control registers
279 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
280 if (haveSecurity) {
281 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
282 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
283 } else if (haveVirtualization) {
284 // also MISCREG_SCTLR_EL2 (by mapping)
285 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
286 } else {
287 // also MISCREG_SCTLR_EL1 (by mapping)
288 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
289 // Always non-secure
290 miscRegs[MISCREG_SCR_EL3] = 1;
291 }
292
293 // Initialize configurable id registers
294 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
295 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
296 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
297 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
298 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
299
300 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
301 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
302 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
303 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
304 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
305
306 miscRegs[MISCREG_ID_DFR0_EL1] =
307 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
308
309 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
310
311 // Enforce consistency with system-level settings...
312
313 // EL3
314 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
315 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
316 haveSecurity ? 0x2 : 0x0);
317 // EL2
318 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
319 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
320 haveVirtualization ? 0x2 : 0x0);
321 // Large ASID support
322 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
323 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
324 haveLargeAsid64 ? 0x2 : 0x0);
325 // Physical address size
326 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
327 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
328 encodePhysAddrRange64(physAddrRange64));
329}
330
331MiscReg
332ISA::readMiscRegNoEffect(int misc_reg) const
333{
334 assert(misc_reg < NumMiscRegs);
335
336 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
337 const auto &map = getMiscIndices(misc_reg);
338 int lower = map.first, upper = map.second;
339 // NB!: apply architectural masks according to desired register,
340 // despite possibly getting value from different (mapped) register.
341 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
342 |(miscRegs[upper] << 32));
343 if (val & reg.res0()) {
344 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
345 miscRegName[misc_reg], val & reg.res0());
346 }
347 if ((val & reg.res1()) != reg.res1()) {
348 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
349 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
350 }
351 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
352}
353
354
355MiscReg
356ISA::readMiscReg(int misc_reg, ThreadContext *tc)
357{
358 CPSR cpsr = 0;
359 PCState pc = 0;
360 SCR scr = 0;
361
362 if (misc_reg == MISCREG_CPSR) {
363 cpsr = miscRegs[misc_reg];
364 pc = tc->pcState();
365 cpsr.j = pc.jazelle() ? 1 : 0;
366 cpsr.t = pc.thumb() ? 1 : 0;
367 return cpsr;
368 }
369
370#ifndef NDEBUG
371 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
372 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
373 warn("Unimplemented system register %s read.\n",
374 miscRegName[misc_reg]);
375 else
376 panic("Unimplemented system register %s read.\n",
377 miscRegName[misc_reg]);
378 }
379#endif
380
381 switch (unflattenMiscReg(misc_reg)) {
382 case MISCREG_HCR:
383 {
384 if (!haveVirtualization)
385 return 0;
386 else
387 return readMiscRegNoEffect(MISCREG_HCR);
388 }
389 case MISCREG_CPACR:
390 {
391 const uint32_t ones = (uint32_t)(-1);
392 CPACR cpacrMask = 0;
393 // Only cp10, cp11, and ase are implemented, nothing else should
394 // be readable? (straight copy from the write code)
395 cpacrMask.cp10 = ones;
396 cpacrMask.cp11 = ones;
397 cpacrMask.asedis = ones;
398
399 // Security Extensions may limit the readability of CPACR
400 if (haveSecurity) {
401 scr = readMiscRegNoEffect(MISCREG_SCR);
402 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
403 if (scr.ns && (cpsr.mode != MODE_MON)) {
404 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
405 // NB: Skipping the full loop, here
406 if (!nsacr.cp10) cpacrMask.cp10 = 0;
407 if (!nsacr.cp11) cpacrMask.cp11 = 0;
408 }
409 }
410 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
411 val &= cpacrMask;
412 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
413 miscRegName[misc_reg], val);
414 return val;
415 }
416 case MISCREG_MPIDR:
417 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
418 scr = readMiscRegNoEffect(MISCREG_SCR);
419 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
420 return getMPIDR(system, tc);
421 } else {
422 return readMiscReg(MISCREG_VMPIDR, tc);
423 }
424 break;
425 case MISCREG_MPIDR_EL1:
426 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
427 return getMPIDR(system, tc) & 0xffffffff;
428 case MISCREG_VMPIDR:
429 // top bit defined as RES1
430 return readMiscRegNoEffect(misc_reg) | 0x80000000;
431 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
432 case MISCREG_REVIDR: // not implemented, so alias MIDR
433 case MISCREG_MIDR:
434 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
435 scr = readMiscRegNoEffect(MISCREG_SCR);
436 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
437 return readMiscRegNoEffect(misc_reg);
438 } else {
439 return readMiscRegNoEffect(MISCREG_VPIDR);
440 }
441 break;
442 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
445 case MISCREG_AIDR: // AUX ID set to 0
446 case MISCREG_TCMTR: // No TCM's
447 return 0;
448
449 case MISCREG_CLIDR:
450 warn_once("The clidr register always reports 0 caches.\n");
451 warn_once("clidr LoUIS field of 0b001 to match current "
452 "ARM implementations.\n");
453 return 0x00200000;
454 case MISCREG_CCSIDR:
455 warn_once("The ccsidr register isn't implemented and "
456 "always reads as 0.\n");
457 break;
458 case MISCREG_CTR: // AArch32, ARMv7, top bit set
459 case MISCREG_CTR_EL0: // AArch64
460 {
461 //all caches have the same line size in gem5
462 //4 byte words in ARM
463 unsigned lineSizeWords =
464 tc->getSystemPtr()->cacheLineSize() / 4;
465 unsigned log2LineSizeWords = 0;
466
467 while (lineSizeWords >>= 1) {
468 ++log2LineSizeWords;
469 }
470
471 CTR ctr = 0;
472 //log2 of minimun i-cache line size (words)
473 ctr.iCacheLineSize = log2LineSizeWords;
474 //b11 - gem5 uses pipt
475 ctr.l1IndexPolicy = 0x3;
476 //log2 of minimum d-cache line size (words)
477 ctr.dCacheLineSize = log2LineSizeWords;
478 //log2 of max reservation size (words)
479 ctr.erg = log2LineSizeWords;
480 //log2 of max writeback size (words)
481 ctr.cwg = log2LineSizeWords;
482 //b100 - gem5 format is ARMv7
483 ctr.format = 0x4;
484
485 return ctr;
486 }
487 case MISCREG_ACTLR:
488 warn("Not doing anything for miscreg ACTLR\n");
489 break;
490
491 case MISCREG_PMXEVTYPER_PMCCFILTR:
492 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
493 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
494 case MISCREG_PMCR ... MISCREG_PMOVSSET:
495 return pmu->readMiscReg(misc_reg);
496
497 case MISCREG_CPSR_Q:
498 panic("shouldn't be reading this register seperately\n");
499 case MISCREG_FPSCR_QC:
500 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
501 case MISCREG_FPSCR_EXC:
502 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
503 case MISCREG_FPSR:
504 {
505 const uint32_t ones = (uint32_t)(-1);
506 FPSCR fpscrMask = 0;
507 fpscrMask.ioc = ones;
508 fpscrMask.dzc = ones;
509 fpscrMask.ofc = ones;
510 fpscrMask.ufc = ones;
511 fpscrMask.ixc = ones;
512 fpscrMask.idc = ones;
513 fpscrMask.qc = ones;
514 fpscrMask.v = ones;
515 fpscrMask.c = ones;
516 fpscrMask.z = ones;
517 fpscrMask.n = ones;
518 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
519 }
520 case MISCREG_FPCR:
521 {
522 const uint32_t ones = (uint32_t)(-1);
523 FPSCR fpscrMask = 0;
524 fpscrMask.ioe = ones;
525 fpscrMask.dze = ones;
526 fpscrMask.ofe = ones;
527 fpscrMask.ufe = ones;
528 fpscrMask.ixe = ones;
529 fpscrMask.ide = ones;
530 fpscrMask.len = ones;
531 fpscrMask.stride = ones;
532 fpscrMask.rMode = ones;
533 fpscrMask.fz = ones;
534 fpscrMask.dn = ones;
535 fpscrMask.ahp = ones;
536 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
537 }
538 case MISCREG_NZCV:
539 {
540 CPSR cpsr = 0;
541 cpsr.nz = tc->readCCReg(CCREG_NZ);
542 cpsr.c = tc->readCCReg(CCREG_C);
543 cpsr.v = tc->readCCReg(CCREG_V);
544 return cpsr;
545 }
546 case MISCREG_DAIF:
547 {
548 CPSR cpsr = 0;
549 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
550 return cpsr;
551 }
552 case MISCREG_SP_EL0:
553 {
554 return tc->readIntReg(INTREG_SP0);
555 }
556 case MISCREG_SP_EL1:
557 {
558 return tc->readIntReg(INTREG_SP1);
559 }
560 case MISCREG_SP_EL2:
561 {
562 return tc->readIntReg(INTREG_SP2);
563 }
564 case MISCREG_SPSEL:
565 {
566 return miscRegs[MISCREG_CPSR] & 0x1;
567 }
568 case MISCREG_CURRENTEL:
569 {
570 return miscRegs[MISCREG_CPSR] & 0xc;
571 }
572 case MISCREG_L2CTLR:
573 {
574 // mostly unimplemented, just set NumCPUs field from sim and return
575 L2CTLR l2ctlr = 0;
576 // b00:1CPU to b11:4CPUs
577 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
578 return l2ctlr;
579 }
580 case MISCREG_DBGDIDR:
581 /* For now just implement the version number.
582 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
583 */
584 return 0x5 << 16;
585 case MISCREG_DBGDSCRint:
586 return 0;
587 case MISCREG_ISR:
588 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
589 readMiscRegNoEffect(MISCREG_HCR),
590 readMiscRegNoEffect(MISCREG_CPSR),
591 readMiscRegNoEffect(MISCREG_SCR));
592 case MISCREG_ISR_EL1:
593 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
594 readMiscRegNoEffect(MISCREG_HCR_EL2),
595 readMiscRegNoEffect(MISCREG_CPSR),
596 readMiscRegNoEffect(MISCREG_SCR_EL3));
597 case MISCREG_DCZID_EL0:
598 return 0x04; // DC ZVA clear 64-byte chunks
599 case MISCREG_HCPTR:
600 {
601 MiscReg val = readMiscRegNoEffect(misc_reg);
602 // The trap bit associated with CP14 is defined as RAZ
603 val &= ~(1 << 14);
604 // If a CP bit in NSACR is 0 then the corresponding bit in
605 // HCPTR is RAO/WI
606 bool secure_lookup = haveSecurity &&
607 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
608 readMiscRegNoEffect(MISCREG_CPSR));
609 if (!secure_lookup) {
610 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
611 val |= (mask ^ 0x7FFF) & 0xBFFF;
612 }
613 // Set the bits for unimplemented coprocessors to RAO/WI
614 val |= 0x33FF;
615 return (val);
616 }
617 case MISCREG_HDFAR: // alias for secure DFAR
618 return readMiscRegNoEffect(MISCREG_DFAR_S);
619 case MISCREG_HIFAR: // alias for secure IFAR
620 return readMiscRegNoEffect(MISCREG_IFAR_S);
621 case MISCREG_HVBAR: // bottom bits reserved
622 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
623 case MISCREG_SCTLR:
624 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
625 case MISCREG_SCTLR_EL1:
626 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
627 case MISCREG_SCTLR_EL2:
628 case MISCREG_SCTLR_EL3:
629 case MISCREG_HSCTLR:
630 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
631
632 case MISCREG_ID_PFR0:
633 // !ThumbEE | !Jazelle | Thumb | ARM
634 return 0x00000031;
635 case MISCREG_ID_PFR1:
636 { // Timer | Virti | !M Profile | TrustZone | ARMv4
637 bool haveTimer = (system->getGenericTimer() != NULL);
638 return 0x00000001
639 | (haveSecurity ? 0x00000010 : 0x0)
640 | (haveVirtualization ? 0x00001000 : 0x0)
641 | (haveTimer ? 0x00010000 : 0x0);
642 }
643 case MISCREG_ID_AA64PFR0_EL1:
644 return 0x0000000000000002 // AArch{64,32} supported at EL0
645 | 0x0000000000000020 // EL1
646 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
647 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
648 case MISCREG_ID_AA64PFR1_EL1:
649 return 0; // bits [63:0] RES0 (reserved for future use)
650
651 // Generic Timer registers
652 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
653 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
654 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
655 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
656 return getGenericTimer(tc).readMiscReg(misc_reg);
657
658 default:
659 break;
660
661 }
662 return readMiscRegNoEffect(misc_reg);
663}
664
665void
666ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
667{
668 assert(misc_reg < NumMiscRegs);
669
670 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
671 const auto &map = getMiscIndices(misc_reg);
672 int lower = map.first, upper = map.second;
673
674 auto v = (val & ~reg.wi()) | reg.rao();
675 if (upper > 0) {
676 miscRegs[lower] = bits(v, 31, 0);
677 miscRegs[upper] = bits(v, 63, 32);
678 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
679 misc_reg, lower, upper, v);
680 } else {
681 miscRegs[lower] = v;
682 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
683 misc_reg, lower, v);
684 }
685}
686
687void
688ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
689{
690
691 MiscReg newVal = val;
692 bool secure_lookup;
693 SCR scr;
694
695 if (misc_reg == MISCREG_CPSR) {
696 updateRegMap(val);
697
698
699 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
700 int old_mode = old_cpsr.mode;
701 CPSR cpsr = val;
702 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
703 getITBPtr(tc)->invalidateMiscReg();
704 getDTBPtr(tc)->invalidateMiscReg();
705 }
706
707 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
708 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
709 PCState pc = tc->pcState();
710 pc.nextThumb(cpsr.t);
711 pc.nextJazelle(cpsr.j);
712
713 // Follow slightly different semantics if a CheckerCPU object
714 // is connected
715 CheckerCPU *checker = tc->getCheckerCpuPtr();
716 if (checker) {
717 tc->pcStateNoRecord(pc);
718 } else {
719 tc->pcState(pc);
720 }
721 } else {
722#ifndef NDEBUG
723 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
724 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
725 warn("Unimplemented system register %s write with %#x.\n",
726 miscRegName[misc_reg], val);
727 else
728 panic("Unimplemented system register %s write with %#x.\n",
729 miscRegName[misc_reg], val);
730 }
731#endif
732 switch (unflattenMiscReg(misc_reg)) {
733 case MISCREG_CPACR:
734 {
735
736 const uint32_t ones = (uint32_t)(-1);
737 CPACR cpacrMask = 0;
738 // Only cp10, cp11, and ase are implemented, nothing else should
739 // be writable
740 cpacrMask.cp10 = ones;
741 cpacrMask.cp11 = ones;
742 cpacrMask.asedis = ones;
743
744 // Security Extensions may limit the writability of CPACR
745 if (haveSecurity) {
746 scr = readMiscRegNoEffect(MISCREG_SCR);
747 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
748 if (scr.ns && (cpsr.mode != MODE_MON)) {
749 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
750 // NB: Skipping the full loop, here
751 if (!nsacr.cp10) cpacrMask.cp10 = 0;
752 if (!nsacr.cp11) cpacrMask.cp11 = 0;
753 }
754 }
755
756 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
757 newVal &= cpacrMask;
758 newVal |= old_val & ~cpacrMask;
759 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
760 miscRegName[misc_reg], newVal);
761 }
762 break;
763 case MISCREG_CPACR_EL1:
764 {
765 const uint32_t ones = (uint32_t)(-1);
766 CPACR cpacrMask = 0;
767 cpacrMask.tta = ones;
768 cpacrMask.fpen = ones;
769 newVal &= cpacrMask;
770 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
771 miscRegName[misc_reg], newVal);
772 }
773 break;
774 case MISCREG_CPTR_EL2:
775 {
776 const uint32_t ones = (uint32_t)(-1);
777 CPTR cptrMask = 0;
778 cptrMask.tcpac = ones;
779 cptrMask.tta = ones;
780 cptrMask.tfp = ones;
781 newVal &= cptrMask;
782 cptrMask = 0;
783 cptrMask.res1_13_12_el2 = ones;
784 cptrMask.res1_9_0_el2 = ones;
785 newVal |= cptrMask;
786 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
787 miscRegName[misc_reg], newVal);
788 }
789 break;
790 case MISCREG_CPTR_EL3:
791 {
792 const uint32_t ones = (uint32_t)(-1);
793 CPTR cptrMask = 0;
794 cptrMask.tcpac = ones;
795 cptrMask.tta = ones;
796 cptrMask.tfp = ones;
797 newVal &= cptrMask;
798 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
799 miscRegName[misc_reg], newVal);
800 }
801 break;
802 case MISCREG_CSSELR:
803 warn_once("The csselr register isn't implemented.\n");
804 return;
805
806 case MISCREG_DC_ZVA_Xt:
807 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
808 return;
809
810 case MISCREG_FPSCR:
811 {
812 const uint32_t ones = (uint32_t)(-1);
813 FPSCR fpscrMask = 0;
814 fpscrMask.ioc = ones;
815 fpscrMask.dzc = ones;
816 fpscrMask.ofc = ones;
817 fpscrMask.ufc = ones;
818 fpscrMask.ixc = ones;
819 fpscrMask.idc = ones;
820 fpscrMask.ioe = ones;
821 fpscrMask.dze = ones;
822 fpscrMask.ofe = ones;
823 fpscrMask.ufe = ones;
824 fpscrMask.ixe = ones;
825 fpscrMask.ide = ones;
826 fpscrMask.len = ones;
827 fpscrMask.stride = ones;
828 fpscrMask.rMode = ones;
829 fpscrMask.fz = ones;
830 fpscrMask.dn = ones;
831 fpscrMask.ahp = ones;
832 fpscrMask.qc = ones;
833 fpscrMask.v = ones;
834 fpscrMask.c = ones;
835 fpscrMask.z = ones;
836 fpscrMask.n = ones;
837 newVal = (newVal & (uint32_t)fpscrMask) |
838 (readMiscRegNoEffect(MISCREG_FPSCR) &
839 ~(uint32_t)fpscrMask);
840 tc->getDecoderPtr()->setContext(newVal);
841 }
842 break;
843 case MISCREG_FPSR:
844 {
845 const uint32_t ones = (uint32_t)(-1);
846 FPSCR fpscrMask = 0;
847 fpscrMask.ioc = ones;
848 fpscrMask.dzc = ones;
849 fpscrMask.ofc = ones;
850 fpscrMask.ufc = ones;
851 fpscrMask.ixc = ones;
852 fpscrMask.idc = ones;
853 fpscrMask.qc = ones;
854 fpscrMask.v = ones;
855 fpscrMask.c = ones;
856 fpscrMask.z = ones;
857 fpscrMask.n = ones;
858 newVal = (newVal & (uint32_t)fpscrMask) |
859 (readMiscRegNoEffect(MISCREG_FPSCR) &
860 ~(uint32_t)fpscrMask);
861 misc_reg = MISCREG_FPSCR;
862 }
863 break;
864 case MISCREG_FPCR:
865 {
866 const uint32_t ones = (uint32_t)(-1);
867 FPSCR fpscrMask = 0;
868 fpscrMask.ioe = ones;
869 fpscrMask.dze = ones;
870 fpscrMask.ofe = ones;
871 fpscrMask.ufe = ones;
872 fpscrMask.ixe = ones;
873 fpscrMask.ide = ones;
874 fpscrMask.len = ones;
875 fpscrMask.stride = ones;
876 fpscrMask.rMode = ones;
877 fpscrMask.fz = ones;
878 fpscrMask.dn = ones;
879 fpscrMask.ahp = ones;
880 newVal = (newVal & (uint32_t)fpscrMask) |
881 (readMiscRegNoEffect(MISCREG_FPSCR) &
882 ~(uint32_t)fpscrMask);
883 misc_reg = MISCREG_FPSCR;
884 }
885 break;
886 case MISCREG_CPSR_Q:
887 {
888 assert(!(newVal & ~CpsrMaskQ));
889 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
890 misc_reg = MISCREG_CPSR;
891 }
892 break;
893 case MISCREG_FPSCR_QC:
894 {
895 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
896 (newVal & FpscrQcMask);
897 misc_reg = MISCREG_FPSCR;
898 }
899 break;
900 case MISCREG_FPSCR_EXC:
901 {
902 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
903 (newVal & FpscrExcMask);
904 misc_reg = MISCREG_FPSCR;
905 }
906 break;
907 case MISCREG_FPEXC:
908 {
909 // vfpv3 architecture, section B.6.1 of DDI04068
910 // bit 29 - valid only if fpexc[31] is 0
911 const uint32_t fpexcMask = 0x60000000;
912 newVal = (newVal & fpexcMask) |
913 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
914 }
915 break;
916 case MISCREG_HCR:
917 {
918 if (!haveVirtualization)
919 return;
920 }
921 break;
922 case MISCREG_IFSR:
923 {
924 // ARM ARM (ARM DDI 0406C.b) B4.1.96
925 const uint32_t ifsrMask =
926 mask(31, 13) | mask(11, 11) | mask(8, 6);
927 newVal = newVal & ~ifsrMask;
928 }
929 break;
930 case MISCREG_DFSR:
931 {
932 // ARM ARM (ARM DDI 0406C.b) B4.1.52
933 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
934 newVal = newVal & ~dfsrMask;
935 }
936 break;
937 case MISCREG_AMAIR0:
938 case MISCREG_AMAIR1:
939 {
940 // ARM ARM (ARM DDI 0406C.b) B4.1.5
941 // Valid only with LPAE
942 if (!haveLPAE)
943 return;
944 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
945 }
946 break;
947 case MISCREG_SCR:
948 getITBPtr(tc)->invalidateMiscReg();
949 getDTBPtr(tc)->invalidateMiscReg();
950 break;
951 case MISCREG_SCTLR:
952 {
953 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
954 scr = readMiscRegNoEffect(MISCREG_SCR);
| 1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58
59ISA::ISA(Params *p)
60 : SimObject(p),
61 system(NULL),
62 _decoderFlavour(p->decoderFlavour),
63 _vecRegRenameMode(p->vecRegRenameMode),
64 pmu(p->pmu)
65{
66 miscRegs[MISCREG_SCTLR_RST] = 0;
67
68 // Hook up a dummy device if we haven't been configured with a
69 // real PMU. By using a dummy device, we don't need to check that
70 // the PMU exist every time we try to access a PMU register.
71 if (!pmu)
72 pmu = &dummyDevice;
73
74 // Give all ISA devices a pointer to this ISA
75 pmu->setISA(this);
76
77 system = dynamic_cast<ArmSystem *>(p->system);
78
79 // Cache system-level properties
80 if (FullSystem && system) {
81 highestELIs64 = system->highestELIs64();
82 haveSecurity = system->haveSecurity();
83 haveLPAE = system->haveLPAE();
84 haveVirtualization = system->haveVirtualization();
85 haveLargeAsid64 = system->haveLargeAsid64();
86 physAddrRange64 = system->physAddrRange64();
87 } else {
88 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
89 haveSecurity = haveLPAE = haveVirtualization = false;
90 haveLargeAsid64 = false;
91 physAddrRange64 = 32; // dummy value
92 }
93
94 initializeMiscRegMetadata();
95 preUnflattenMiscReg();
96
97 clear();
98}
99
100std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
101
102const ArmISAParams *
103ISA::params() const
104{
105 return dynamic_cast<const Params *>(_params);
106}
107
108void
109ISA::clear()
110{
111 const Params *p(params());
112
113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
114 memset(miscRegs, 0, sizeof(miscRegs));
115
116 // Initialize configurable default values
117 miscRegs[MISCREG_MIDR] = p->midr;
118 miscRegs[MISCREG_MIDR_EL1] = p->midr;
119 miscRegs[MISCREG_VPIDR] = p->midr;
120
121 if (FullSystem && system->highestELIs64()) {
122 // Initialize AArch64 state
123 clear64(p);
124 return;
125 }
126
127 // Initialize AArch32 state...
128
129 CPSR cpsr = 0;
130 cpsr.mode = MODE_USER;
131 miscRegs[MISCREG_CPSR] = cpsr;
132 updateRegMap(cpsr);
133
134 SCTLR sctlr = 0;
135 sctlr.te = (bool) sctlr_rst.te;
136 sctlr.nmfi = (bool) sctlr_rst.nmfi;
137 sctlr.v = (bool) sctlr_rst.v;
138 sctlr.u = 1;
139 sctlr.xp = 1;
140 sctlr.rao2 = 1;
141 sctlr.rao3 = 1;
142 sctlr.rao4 = 0xf; // SCTLR[6:3]
143 sctlr.uci = 1;
144 sctlr.dze = 1;
145 miscRegs[MISCREG_SCTLR_NS] = sctlr;
146 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
147 miscRegs[MISCREG_HCPTR] = 0;
148
149 // Start with an event in the mailbox
150 miscRegs[MISCREG_SEV_MAILBOX] = 1;
151
152 // Separate Instruction and Data TLBs
153 miscRegs[MISCREG_TLBTR] = 1;
154
155 MVFR0 mvfr0 = 0;
156 mvfr0.advSimdRegisters = 2;
157 mvfr0.singlePrecision = 2;
158 mvfr0.doublePrecision = 2;
159 mvfr0.vfpExceptionTrapping = 0;
160 mvfr0.divide = 1;
161 mvfr0.squareRoot = 1;
162 mvfr0.shortVectors = 1;
163 mvfr0.roundingModes = 1;
164 miscRegs[MISCREG_MVFR0] = mvfr0;
165
166 MVFR1 mvfr1 = 0;
167 mvfr1.flushToZero = 1;
168 mvfr1.defaultNaN = 1;
169 mvfr1.advSimdLoadStore = 1;
170 mvfr1.advSimdInteger = 1;
171 mvfr1.advSimdSinglePrecision = 1;
172 mvfr1.advSimdHalfPrecision = 1;
173 mvfr1.vfpHalfPrecision = 1;
174 miscRegs[MISCREG_MVFR1] = mvfr1;
175
176 // Reset values of PRRR and NMRR are implementation dependent
177
178 // @todo: PRRR and NMRR in secure state?
179 miscRegs[MISCREG_PRRR_NS] =
180 (1 << 19) | // 19
181 (0 << 18) | // 18
182 (0 << 17) | // 17
183 (1 << 16) | // 16
184 (2 << 14) | // 15:14
185 (0 << 12) | // 13:12
186 (2 << 10) | // 11:10
187 (2 << 8) | // 9:8
188 (2 << 6) | // 7:6
189 (2 << 4) | // 5:4
190 (1 << 2) | // 3:2
191 0; // 1:0
192 miscRegs[MISCREG_NMRR_NS] =
193 (1 << 30) | // 31:30
194 (0 << 26) | // 27:26
195 (0 << 24) | // 25:24
196 (3 << 22) | // 23:22
197 (2 << 20) | // 21:20
198 (0 << 18) | // 19:18
199 (0 << 16) | // 17:16
200 (1 << 14) | // 15:14
201 (0 << 12) | // 13:12
202 (2 << 10) | // 11:10
203 (0 << 8) | // 9:8
204 (3 << 6) | // 7:6
205 (2 << 4) | // 5:4
206 (0 << 2) | // 3:2
207 0; // 1:0
208
209 miscRegs[MISCREG_CPACR] = 0;
210
211 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
212 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
213 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
214 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
215
216 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
217 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
218 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
219 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
220 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
221 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
222
223 miscRegs[MISCREG_FPSID] = p->fpsid;
224
225 if (haveLPAE) {
226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
227 ttbcr.eae = 0;
228 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
229 // Enforce consistency with system-level settings
230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
231 }
232
233 if (haveSecurity) {
234 miscRegs[MISCREG_SCTLR_S] = sctlr;
235 miscRegs[MISCREG_SCR] = 0;
236 miscRegs[MISCREG_VBAR_S] = 0;
237 } else {
238 // we're always non-secure
239 miscRegs[MISCREG_SCR] = 1;
240 }
241
242 //XXX We need to initialize the rest of the state.
243}
244
245void
246ISA::clear64(const ArmISAParams *p)
247{
248 CPSR cpsr = 0;
249 Addr rvbar = system->resetAddr64();
250 switch (system->highestEL()) {
251 // Set initial EL to highest implemented EL using associated stack
252 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
253 // value
254 case EL3:
255 cpsr.mode = MODE_EL3H;
256 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
257 break;
258 case EL2:
259 cpsr.mode = MODE_EL2H;
260 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
261 break;
262 case EL1:
263 cpsr.mode = MODE_EL1H;
264 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
265 break;
266 default:
267 panic("Invalid highest implemented exception level");
268 break;
269 }
270
271 // Initialize rest of CPSR
272 cpsr.daif = 0xf; // Mask all interrupts
273 cpsr.ss = 0;
274 cpsr.il = 0;
275 miscRegs[MISCREG_CPSR] = cpsr;
276 updateRegMap(cpsr);
277
278 // Initialize other control registers
279 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
280 if (haveSecurity) {
281 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
282 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
283 } else if (haveVirtualization) {
284 // also MISCREG_SCTLR_EL2 (by mapping)
285 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
286 } else {
287 // also MISCREG_SCTLR_EL1 (by mapping)
288 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
289 // Always non-secure
290 miscRegs[MISCREG_SCR_EL3] = 1;
291 }
292
293 // Initialize configurable id registers
294 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
295 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
296 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
297 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
298 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
299
300 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
301 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
302 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
303 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
304 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
305
306 miscRegs[MISCREG_ID_DFR0_EL1] =
307 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
308
309 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
310
311 // Enforce consistency with system-level settings...
312
313 // EL3
314 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
315 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
316 haveSecurity ? 0x2 : 0x0);
317 // EL2
318 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
319 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
320 haveVirtualization ? 0x2 : 0x0);
321 // Large ASID support
322 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
323 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
324 haveLargeAsid64 ? 0x2 : 0x0);
325 // Physical address size
326 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
327 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
328 encodePhysAddrRange64(physAddrRange64));
329}
330
331MiscReg
332ISA::readMiscRegNoEffect(int misc_reg) const
333{
334 assert(misc_reg < NumMiscRegs);
335
336 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
337 const auto &map = getMiscIndices(misc_reg);
338 int lower = map.first, upper = map.second;
339 // NB!: apply architectural masks according to desired register,
340 // despite possibly getting value from different (mapped) register.
341 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
342 |(miscRegs[upper] << 32));
343 if (val & reg.res0()) {
344 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
345 miscRegName[misc_reg], val & reg.res0());
346 }
347 if ((val & reg.res1()) != reg.res1()) {
348 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
349 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
350 }
351 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
352}
353
354
355MiscReg
356ISA::readMiscReg(int misc_reg, ThreadContext *tc)
357{
358 CPSR cpsr = 0;
359 PCState pc = 0;
360 SCR scr = 0;
361
362 if (misc_reg == MISCREG_CPSR) {
363 cpsr = miscRegs[misc_reg];
364 pc = tc->pcState();
365 cpsr.j = pc.jazelle() ? 1 : 0;
366 cpsr.t = pc.thumb() ? 1 : 0;
367 return cpsr;
368 }
369
370#ifndef NDEBUG
371 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
372 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
373 warn("Unimplemented system register %s read.\n",
374 miscRegName[misc_reg]);
375 else
376 panic("Unimplemented system register %s read.\n",
377 miscRegName[misc_reg]);
378 }
379#endif
380
381 switch (unflattenMiscReg(misc_reg)) {
382 case MISCREG_HCR:
383 {
384 if (!haveVirtualization)
385 return 0;
386 else
387 return readMiscRegNoEffect(MISCREG_HCR);
388 }
389 case MISCREG_CPACR:
390 {
391 const uint32_t ones = (uint32_t)(-1);
392 CPACR cpacrMask = 0;
393 // Only cp10, cp11, and ase are implemented, nothing else should
394 // be readable? (straight copy from the write code)
395 cpacrMask.cp10 = ones;
396 cpacrMask.cp11 = ones;
397 cpacrMask.asedis = ones;
398
399 // Security Extensions may limit the readability of CPACR
400 if (haveSecurity) {
401 scr = readMiscRegNoEffect(MISCREG_SCR);
402 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
403 if (scr.ns && (cpsr.mode != MODE_MON)) {
404 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
405 // NB: Skipping the full loop, here
406 if (!nsacr.cp10) cpacrMask.cp10 = 0;
407 if (!nsacr.cp11) cpacrMask.cp11 = 0;
408 }
409 }
410 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
411 val &= cpacrMask;
412 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
413 miscRegName[misc_reg], val);
414 return val;
415 }
416 case MISCREG_MPIDR:
417 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
418 scr = readMiscRegNoEffect(MISCREG_SCR);
419 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
420 return getMPIDR(system, tc);
421 } else {
422 return readMiscReg(MISCREG_VMPIDR, tc);
423 }
424 break;
425 case MISCREG_MPIDR_EL1:
426 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
427 return getMPIDR(system, tc) & 0xffffffff;
428 case MISCREG_VMPIDR:
429 // top bit defined as RES1
430 return readMiscRegNoEffect(misc_reg) | 0x80000000;
431 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
432 case MISCREG_REVIDR: // not implemented, so alias MIDR
433 case MISCREG_MIDR:
434 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
435 scr = readMiscRegNoEffect(MISCREG_SCR);
436 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
437 return readMiscRegNoEffect(misc_reg);
438 } else {
439 return readMiscRegNoEffect(MISCREG_VPIDR);
440 }
441 break;
442 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
445 case MISCREG_AIDR: // AUX ID set to 0
446 case MISCREG_TCMTR: // No TCM's
447 return 0;
448
449 case MISCREG_CLIDR:
450 warn_once("The clidr register always reports 0 caches.\n");
451 warn_once("clidr LoUIS field of 0b001 to match current "
452 "ARM implementations.\n");
453 return 0x00200000;
454 case MISCREG_CCSIDR:
455 warn_once("The ccsidr register isn't implemented and "
456 "always reads as 0.\n");
457 break;
458 case MISCREG_CTR: // AArch32, ARMv7, top bit set
459 case MISCREG_CTR_EL0: // AArch64
460 {
461 //all caches have the same line size in gem5
462 //4 byte words in ARM
463 unsigned lineSizeWords =
464 tc->getSystemPtr()->cacheLineSize() / 4;
465 unsigned log2LineSizeWords = 0;
466
467 while (lineSizeWords >>= 1) {
468 ++log2LineSizeWords;
469 }
470
471 CTR ctr = 0;
472 //log2 of minimun i-cache line size (words)
473 ctr.iCacheLineSize = log2LineSizeWords;
474 //b11 - gem5 uses pipt
475 ctr.l1IndexPolicy = 0x3;
476 //log2 of minimum d-cache line size (words)
477 ctr.dCacheLineSize = log2LineSizeWords;
478 //log2 of max reservation size (words)
479 ctr.erg = log2LineSizeWords;
480 //log2 of max writeback size (words)
481 ctr.cwg = log2LineSizeWords;
482 //b100 - gem5 format is ARMv7
483 ctr.format = 0x4;
484
485 return ctr;
486 }
487 case MISCREG_ACTLR:
488 warn("Not doing anything for miscreg ACTLR\n");
489 break;
490
491 case MISCREG_PMXEVTYPER_PMCCFILTR:
492 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
493 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
494 case MISCREG_PMCR ... MISCREG_PMOVSSET:
495 return pmu->readMiscReg(misc_reg);
496
497 case MISCREG_CPSR_Q:
498 panic("shouldn't be reading this register seperately\n");
499 case MISCREG_FPSCR_QC:
500 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
501 case MISCREG_FPSCR_EXC:
502 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
503 case MISCREG_FPSR:
504 {
505 const uint32_t ones = (uint32_t)(-1);
506 FPSCR fpscrMask = 0;
507 fpscrMask.ioc = ones;
508 fpscrMask.dzc = ones;
509 fpscrMask.ofc = ones;
510 fpscrMask.ufc = ones;
511 fpscrMask.ixc = ones;
512 fpscrMask.idc = ones;
513 fpscrMask.qc = ones;
514 fpscrMask.v = ones;
515 fpscrMask.c = ones;
516 fpscrMask.z = ones;
517 fpscrMask.n = ones;
518 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
519 }
520 case MISCREG_FPCR:
521 {
522 const uint32_t ones = (uint32_t)(-1);
523 FPSCR fpscrMask = 0;
524 fpscrMask.ioe = ones;
525 fpscrMask.dze = ones;
526 fpscrMask.ofe = ones;
527 fpscrMask.ufe = ones;
528 fpscrMask.ixe = ones;
529 fpscrMask.ide = ones;
530 fpscrMask.len = ones;
531 fpscrMask.stride = ones;
532 fpscrMask.rMode = ones;
533 fpscrMask.fz = ones;
534 fpscrMask.dn = ones;
535 fpscrMask.ahp = ones;
536 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
537 }
538 case MISCREG_NZCV:
539 {
540 CPSR cpsr = 0;
541 cpsr.nz = tc->readCCReg(CCREG_NZ);
542 cpsr.c = tc->readCCReg(CCREG_C);
543 cpsr.v = tc->readCCReg(CCREG_V);
544 return cpsr;
545 }
546 case MISCREG_DAIF:
547 {
548 CPSR cpsr = 0;
549 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
550 return cpsr;
551 }
552 case MISCREG_SP_EL0:
553 {
554 return tc->readIntReg(INTREG_SP0);
555 }
556 case MISCREG_SP_EL1:
557 {
558 return tc->readIntReg(INTREG_SP1);
559 }
560 case MISCREG_SP_EL2:
561 {
562 return tc->readIntReg(INTREG_SP2);
563 }
564 case MISCREG_SPSEL:
565 {
566 return miscRegs[MISCREG_CPSR] & 0x1;
567 }
568 case MISCREG_CURRENTEL:
569 {
570 return miscRegs[MISCREG_CPSR] & 0xc;
571 }
572 case MISCREG_L2CTLR:
573 {
574 // mostly unimplemented, just set NumCPUs field from sim and return
575 L2CTLR l2ctlr = 0;
576 // b00:1CPU to b11:4CPUs
577 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
578 return l2ctlr;
579 }
580 case MISCREG_DBGDIDR:
581 /* For now just implement the version number.
582 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
583 */
584 return 0x5 << 16;
585 case MISCREG_DBGDSCRint:
586 return 0;
587 case MISCREG_ISR:
588 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
589 readMiscRegNoEffect(MISCREG_HCR),
590 readMiscRegNoEffect(MISCREG_CPSR),
591 readMiscRegNoEffect(MISCREG_SCR));
592 case MISCREG_ISR_EL1:
593 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
594 readMiscRegNoEffect(MISCREG_HCR_EL2),
595 readMiscRegNoEffect(MISCREG_CPSR),
596 readMiscRegNoEffect(MISCREG_SCR_EL3));
597 case MISCREG_DCZID_EL0:
598 return 0x04; // DC ZVA clear 64-byte chunks
599 case MISCREG_HCPTR:
600 {
601 MiscReg val = readMiscRegNoEffect(misc_reg);
602 // The trap bit associated with CP14 is defined as RAZ
603 val &= ~(1 << 14);
604 // If a CP bit in NSACR is 0 then the corresponding bit in
605 // HCPTR is RAO/WI
606 bool secure_lookup = haveSecurity &&
607 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
608 readMiscRegNoEffect(MISCREG_CPSR));
609 if (!secure_lookup) {
610 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
611 val |= (mask ^ 0x7FFF) & 0xBFFF;
612 }
613 // Set the bits for unimplemented coprocessors to RAO/WI
614 val |= 0x33FF;
615 return (val);
616 }
617 case MISCREG_HDFAR: // alias for secure DFAR
618 return readMiscRegNoEffect(MISCREG_DFAR_S);
619 case MISCREG_HIFAR: // alias for secure IFAR
620 return readMiscRegNoEffect(MISCREG_IFAR_S);
621 case MISCREG_HVBAR: // bottom bits reserved
622 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
623 case MISCREG_SCTLR:
624 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
625 case MISCREG_SCTLR_EL1:
626 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
627 case MISCREG_SCTLR_EL2:
628 case MISCREG_SCTLR_EL3:
629 case MISCREG_HSCTLR:
630 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
631
632 case MISCREG_ID_PFR0:
633 // !ThumbEE | !Jazelle | Thumb | ARM
634 return 0x00000031;
635 case MISCREG_ID_PFR1:
636 { // Timer | Virti | !M Profile | TrustZone | ARMv4
637 bool haveTimer = (system->getGenericTimer() != NULL);
638 return 0x00000001
639 | (haveSecurity ? 0x00000010 : 0x0)
640 | (haveVirtualization ? 0x00001000 : 0x0)
641 | (haveTimer ? 0x00010000 : 0x0);
642 }
643 case MISCREG_ID_AA64PFR0_EL1:
644 return 0x0000000000000002 // AArch{64,32} supported at EL0
645 | 0x0000000000000020 // EL1
646 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
647 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
648 case MISCREG_ID_AA64PFR1_EL1:
649 return 0; // bits [63:0] RES0 (reserved for future use)
650
651 // Generic Timer registers
652 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
653 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
654 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
655 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
656 return getGenericTimer(tc).readMiscReg(misc_reg);
657
658 default:
659 break;
660
661 }
662 return readMiscRegNoEffect(misc_reg);
663}
664
665void
666ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
667{
668 assert(misc_reg < NumMiscRegs);
669
670 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
671 const auto &map = getMiscIndices(misc_reg);
672 int lower = map.first, upper = map.second;
673
674 auto v = (val & ~reg.wi()) | reg.rao();
675 if (upper > 0) {
676 miscRegs[lower] = bits(v, 31, 0);
677 miscRegs[upper] = bits(v, 63, 32);
678 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
679 misc_reg, lower, upper, v);
680 } else {
681 miscRegs[lower] = v;
682 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
683 misc_reg, lower, v);
684 }
685}
686
687void
688ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
689{
690
691 MiscReg newVal = val;
692 bool secure_lookup;
693 SCR scr;
694
695 if (misc_reg == MISCREG_CPSR) {
696 updateRegMap(val);
697
698
699 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
700 int old_mode = old_cpsr.mode;
701 CPSR cpsr = val;
702 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
703 getITBPtr(tc)->invalidateMiscReg();
704 getDTBPtr(tc)->invalidateMiscReg();
705 }
706
707 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
708 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
709 PCState pc = tc->pcState();
710 pc.nextThumb(cpsr.t);
711 pc.nextJazelle(cpsr.j);
712
713 // Follow slightly different semantics if a CheckerCPU object
714 // is connected
715 CheckerCPU *checker = tc->getCheckerCpuPtr();
716 if (checker) {
717 tc->pcStateNoRecord(pc);
718 } else {
719 tc->pcState(pc);
720 }
721 } else {
722#ifndef NDEBUG
723 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
724 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
725 warn("Unimplemented system register %s write with %#x.\n",
726 miscRegName[misc_reg], val);
727 else
728 panic("Unimplemented system register %s write with %#x.\n",
729 miscRegName[misc_reg], val);
730 }
731#endif
732 switch (unflattenMiscReg(misc_reg)) {
733 case MISCREG_CPACR:
734 {
735
736 const uint32_t ones = (uint32_t)(-1);
737 CPACR cpacrMask = 0;
738 // Only cp10, cp11, and ase are implemented, nothing else should
739 // be writable
740 cpacrMask.cp10 = ones;
741 cpacrMask.cp11 = ones;
742 cpacrMask.asedis = ones;
743
744 // Security Extensions may limit the writability of CPACR
745 if (haveSecurity) {
746 scr = readMiscRegNoEffect(MISCREG_SCR);
747 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
748 if (scr.ns && (cpsr.mode != MODE_MON)) {
749 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
750 // NB: Skipping the full loop, here
751 if (!nsacr.cp10) cpacrMask.cp10 = 0;
752 if (!nsacr.cp11) cpacrMask.cp11 = 0;
753 }
754 }
755
756 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
757 newVal &= cpacrMask;
758 newVal |= old_val & ~cpacrMask;
759 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
760 miscRegName[misc_reg], newVal);
761 }
762 break;
763 case MISCREG_CPACR_EL1:
764 {
765 const uint32_t ones = (uint32_t)(-1);
766 CPACR cpacrMask = 0;
767 cpacrMask.tta = ones;
768 cpacrMask.fpen = ones;
769 newVal &= cpacrMask;
770 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
771 miscRegName[misc_reg], newVal);
772 }
773 break;
774 case MISCREG_CPTR_EL2:
775 {
776 const uint32_t ones = (uint32_t)(-1);
777 CPTR cptrMask = 0;
778 cptrMask.tcpac = ones;
779 cptrMask.tta = ones;
780 cptrMask.tfp = ones;
781 newVal &= cptrMask;
782 cptrMask = 0;
783 cptrMask.res1_13_12_el2 = ones;
784 cptrMask.res1_9_0_el2 = ones;
785 newVal |= cptrMask;
786 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
787 miscRegName[misc_reg], newVal);
788 }
789 break;
790 case MISCREG_CPTR_EL3:
791 {
792 const uint32_t ones = (uint32_t)(-1);
793 CPTR cptrMask = 0;
794 cptrMask.tcpac = ones;
795 cptrMask.tta = ones;
796 cptrMask.tfp = ones;
797 newVal &= cptrMask;
798 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
799 miscRegName[misc_reg], newVal);
800 }
801 break;
802 case MISCREG_CSSELR:
803 warn_once("The csselr register isn't implemented.\n");
804 return;
805
806 case MISCREG_DC_ZVA_Xt:
807 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
808 return;
809
810 case MISCREG_FPSCR:
811 {
812 const uint32_t ones = (uint32_t)(-1);
813 FPSCR fpscrMask = 0;
814 fpscrMask.ioc = ones;
815 fpscrMask.dzc = ones;
816 fpscrMask.ofc = ones;
817 fpscrMask.ufc = ones;
818 fpscrMask.ixc = ones;
819 fpscrMask.idc = ones;
820 fpscrMask.ioe = ones;
821 fpscrMask.dze = ones;
822 fpscrMask.ofe = ones;
823 fpscrMask.ufe = ones;
824 fpscrMask.ixe = ones;
825 fpscrMask.ide = ones;
826 fpscrMask.len = ones;
827 fpscrMask.stride = ones;
828 fpscrMask.rMode = ones;
829 fpscrMask.fz = ones;
830 fpscrMask.dn = ones;
831 fpscrMask.ahp = ones;
832 fpscrMask.qc = ones;
833 fpscrMask.v = ones;
834 fpscrMask.c = ones;
835 fpscrMask.z = ones;
836 fpscrMask.n = ones;
837 newVal = (newVal & (uint32_t)fpscrMask) |
838 (readMiscRegNoEffect(MISCREG_FPSCR) &
839 ~(uint32_t)fpscrMask);
840 tc->getDecoderPtr()->setContext(newVal);
841 }
842 break;
843 case MISCREG_FPSR:
844 {
845 const uint32_t ones = (uint32_t)(-1);
846 FPSCR fpscrMask = 0;
847 fpscrMask.ioc = ones;
848 fpscrMask.dzc = ones;
849 fpscrMask.ofc = ones;
850 fpscrMask.ufc = ones;
851 fpscrMask.ixc = ones;
852 fpscrMask.idc = ones;
853 fpscrMask.qc = ones;
854 fpscrMask.v = ones;
855 fpscrMask.c = ones;
856 fpscrMask.z = ones;
857 fpscrMask.n = ones;
858 newVal = (newVal & (uint32_t)fpscrMask) |
859 (readMiscRegNoEffect(MISCREG_FPSCR) &
860 ~(uint32_t)fpscrMask);
861 misc_reg = MISCREG_FPSCR;
862 }
863 break;
864 case MISCREG_FPCR:
865 {
866 const uint32_t ones = (uint32_t)(-1);
867 FPSCR fpscrMask = 0;
868 fpscrMask.ioe = ones;
869 fpscrMask.dze = ones;
870 fpscrMask.ofe = ones;
871 fpscrMask.ufe = ones;
872 fpscrMask.ixe = ones;
873 fpscrMask.ide = ones;
874 fpscrMask.len = ones;
875 fpscrMask.stride = ones;
876 fpscrMask.rMode = ones;
877 fpscrMask.fz = ones;
878 fpscrMask.dn = ones;
879 fpscrMask.ahp = ones;
880 newVal = (newVal & (uint32_t)fpscrMask) |
881 (readMiscRegNoEffect(MISCREG_FPSCR) &
882 ~(uint32_t)fpscrMask);
883 misc_reg = MISCREG_FPSCR;
884 }
885 break;
886 case MISCREG_CPSR_Q:
887 {
888 assert(!(newVal & ~CpsrMaskQ));
889 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
890 misc_reg = MISCREG_CPSR;
891 }
892 break;
893 case MISCREG_FPSCR_QC:
894 {
895 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
896 (newVal & FpscrQcMask);
897 misc_reg = MISCREG_FPSCR;
898 }
899 break;
900 case MISCREG_FPSCR_EXC:
901 {
902 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
903 (newVal & FpscrExcMask);
904 misc_reg = MISCREG_FPSCR;
905 }
906 break;
907 case MISCREG_FPEXC:
908 {
909 // vfpv3 architecture, section B.6.1 of DDI04068
910 // bit 29 - valid only if fpexc[31] is 0
911 const uint32_t fpexcMask = 0x60000000;
912 newVal = (newVal & fpexcMask) |
913 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
914 }
915 break;
916 case MISCREG_HCR:
917 {
918 if (!haveVirtualization)
919 return;
920 }
921 break;
922 case MISCREG_IFSR:
923 {
924 // ARM ARM (ARM DDI 0406C.b) B4.1.96
925 const uint32_t ifsrMask =
926 mask(31, 13) | mask(11, 11) | mask(8, 6);
927 newVal = newVal & ~ifsrMask;
928 }
929 break;
930 case MISCREG_DFSR:
931 {
932 // ARM ARM (ARM DDI 0406C.b) B4.1.52
933 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
934 newVal = newVal & ~dfsrMask;
935 }
936 break;
937 case MISCREG_AMAIR0:
938 case MISCREG_AMAIR1:
939 {
940 // ARM ARM (ARM DDI 0406C.b) B4.1.5
941 // Valid only with LPAE
942 if (!haveLPAE)
943 return;
944 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
945 }
946 break;
947 case MISCREG_SCR:
948 getITBPtr(tc)->invalidateMiscReg();
949 getDTBPtr(tc)->invalidateMiscReg();
950 break;
951 case MISCREG_SCTLR:
952 {
953 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
954 scr = readMiscRegNoEffect(MISCREG_SCR);
|
957 SCTLR sctlr = miscRegs[sctlr_idx];
958 SCTLR new_sctlr = newVal;
959 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
960 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
961 getITBPtr(tc)->invalidateMiscReg();
962 getDTBPtr(tc)->invalidateMiscReg();
963 }
964 case MISCREG_MIDR:
965 case MISCREG_ID_PFR0:
966 case MISCREG_ID_PFR1:
967 case MISCREG_ID_DFR0:
968 case MISCREG_ID_MMFR0:
969 case MISCREG_ID_MMFR1:
970 case MISCREG_ID_MMFR2:
971 case MISCREG_ID_MMFR3:
972 case MISCREG_ID_ISAR0:
973 case MISCREG_ID_ISAR1:
974 case MISCREG_ID_ISAR2:
975 case MISCREG_ID_ISAR3:
976 case MISCREG_ID_ISAR4:
977 case MISCREG_ID_ISAR5:
978
979 case MISCREG_MPIDR:
980 case MISCREG_FPSID:
981 case MISCREG_TLBTR:
982 case MISCREG_MVFR0:
983 case MISCREG_MVFR1:
984
985 case MISCREG_ID_AA64AFR0_EL1:
986 case MISCREG_ID_AA64AFR1_EL1:
987 case MISCREG_ID_AA64DFR0_EL1:
988 case MISCREG_ID_AA64DFR1_EL1:
989 case MISCREG_ID_AA64ISAR0_EL1:
990 case MISCREG_ID_AA64ISAR1_EL1:
991 case MISCREG_ID_AA64MMFR0_EL1:
992 case MISCREG_ID_AA64MMFR1_EL1:
993 case MISCREG_ID_AA64PFR0_EL1:
994 case MISCREG_ID_AA64PFR1_EL1:
995 // ID registers are constants.
996 return;
997
998 // TLB Invalidate All
999 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1000 {
1001 assert32(tc);
1002 scr = readMiscReg(MISCREG_SCR, tc);
1003
1004 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1005 tlbiOp(tc);
1006 return;
1007 }
1008 // TLB Invalidate All, Inner Shareable
1009 case MISCREG_TLBIALLIS:
1010 {
1011 assert32(tc);
1012 scr = readMiscReg(MISCREG_SCR, tc);
1013
1014 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1015 tlbiOp.broadcast(tc);
1016 return;
1017 }
1018 // Instruction TLB Invalidate All
1019 case MISCREG_ITLBIALL:
1020 {
1021 assert32(tc);
1022 scr = readMiscReg(MISCREG_SCR, tc);
1023
1024 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1025 tlbiOp(tc);
1026 return;
1027 }
1028 // Data TLB Invalidate All
1029 case MISCREG_DTLBIALL:
1030 {
1031 assert32(tc);
1032 scr = readMiscReg(MISCREG_SCR, tc);
1033
1034 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1035 tlbiOp(tc);
1036 return;
1037 }
1038 // TLB Invalidate by VA
1039 // mcr tlbimval(is) is invalidating all matching entries
1040 // regardless of the level of lookup, since in gem5 we cache
1041 // in the tlb the last level of lookup only.
1042 case MISCREG_TLBIMVA:
1043 case MISCREG_TLBIMVAL:
1044 {
1045 assert32(tc);
1046 scr = readMiscReg(MISCREG_SCR, tc);
1047
1048 TLBIMVA tlbiOp(EL1,
1049 haveSecurity && !scr.ns,
1050 mbits(newVal, 31, 12),
1051 bits(newVal, 7,0));
1052
1053 tlbiOp(tc);
1054 return;
1055 }
1056 // TLB Invalidate by VA, Inner Shareable
1057 case MISCREG_TLBIMVAIS:
1058 case MISCREG_TLBIMVALIS:
1059 {
1060 assert32(tc);
1061 scr = readMiscReg(MISCREG_SCR, tc);
1062
1063 TLBIMVA tlbiOp(EL1,
1064 haveSecurity && !scr.ns,
1065 mbits(newVal, 31, 12),
1066 bits(newVal, 7,0));
1067
1068 tlbiOp.broadcast(tc);
1069 return;
1070 }
1071 // TLB Invalidate by ASID match
1072 case MISCREG_TLBIASID:
1073 {
1074 assert32(tc);
1075 scr = readMiscReg(MISCREG_SCR, tc);
1076
1077 TLBIASID tlbiOp(EL1,
1078 haveSecurity && !scr.ns,
1079 bits(newVal, 7,0));
1080
1081 tlbiOp(tc);
1082 return;
1083 }
1084 // TLB Invalidate by ASID match, Inner Shareable
1085 case MISCREG_TLBIASIDIS:
1086 {
1087 assert32(tc);
1088 scr = readMiscReg(MISCREG_SCR, tc);
1089
1090 TLBIASID tlbiOp(EL1,
1091 haveSecurity && !scr.ns,
1092 bits(newVal, 7,0));
1093
1094 tlbiOp.broadcast(tc);
1095 return;
1096 }
1097 // mcr tlbimvaal(is) is invalidating all matching entries
1098 // regardless of the level of lookup, since in gem5 we cache
1099 // in the tlb the last level of lookup only.
1100 // TLB Invalidate by VA, All ASID
1101 case MISCREG_TLBIMVAA:
1102 case MISCREG_TLBIMVAAL:
1103 {
1104 assert32(tc);
1105 scr = readMiscReg(MISCREG_SCR, tc);
1106
1107 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1108 mbits(newVal, 31,12), false);
1109
1110 tlbiOp(tc);
1111 return;
1112 }
1113 // TLB Invalidate by VA, All ASID, Inner Shareable
1114 case MISCREG_TLBIMVAAIS:
1115 case MISCREG_TLBIMVAALIS:
1116 {
1117 assert32(tc);
1118 scr = readMiscReg(MISCREG_SCR, tc);
1119
1120 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1121 mbits(newVal, 31,12), false);
1122
1123 tlbiOp.broadcast(tc);
1124 return;
1125 }
1126 // mcr tlbimvalh(is) is invalidating all matching entries
1127 // regardless of the level of lookup, since in gem5 we cache
1128 // in the tlb the last level of lookup only.
1129 // TLB Invalidate by VA, Hyp mode
1130 case MISCREG_TLBIMVAH:
1131 case MISCREG_TLBIMVALH:
1132 {
1133 assert32(tc);
1134 scr = readMiscReg(MISCREG_SCR, tc);
1135
1136 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1137 mbits(newVal, 31,12), true);
1138
1139 tlbiOp(tc);
1140 return;
1141 }
1142 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1143 case MISCREG_TLBIMVAHIS:
1144 case MISCREG_TLBIMVALHIS:
1145 {
1146 assert32(tc);
1147 scr = readMiscReg(MISCREG_SCR, tc);
1148
1149 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1150 mbits(newVal, 31,12), true);
1151
1152 tlbiOp.broadcast(tc);
1153 return;
1154 }
1155 // mcr tlbiipas2l(is) is invalidating all matching entries
1156 // regardless of the level of lookup, since in gem5 we cache
1157 // in the tlb the last level of lookup only.
1158 // TLB Invalidate by Intermediate Physical Address, Stage 2
1159 case MISCREG_TLBIIPAS2:
1160 case MISCREG_TLBIIPAS2L:
1161 {
1162 assert32(tc);
1163 scr = readMiscReg(MISCREG_SCR, tc);
1164
1165 TLBIIPA tlbiOp(EL1,
1166 haveSecurity && !scr.ns,
1167 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1168
1169 tlbiOp(tc);
1170 return;
1171 }
1172 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1173 // Inner Shareable
1174 case MISCREG_TLBIIPAS2IS:
1175 case MISCREG_TLBIIPAS2LIS:
1176 {
1177 assert32(tc);
1178 scr = readMiscReg(MISCREG_SCR, tc);
1179
1180 TLBIIPA tlbiOp(EL1,
1181 haveSecurity && !scr.ns,
1182 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1183
1184 tlbiOp.broadcast(tc);
1185 return;
1186 }
1187 // Instruction TLB Invalidate by VA
1188 case MISCREG_ITLBIMVA:
1189 {
1190 assert32(tc);
1191 scr = readMiscReg(MISCREG_SCR, tc);
1192
1193 ITLBIMVA tlbiOp(EL1,
1194 haveSecurity && !scr.ns,
1195 mbits(newVal, 31, 12),
1196 bits(newVal, 7,0));
1197
1198 tlbiOp(tc);
1199 return;
1200 }
1201 // Data TLB Invalidate by VA
1202 case MISCREG_DTLBIMVA:
1203 {
1204 assert32(tc);
1205 scr = readMiscReg(MISCREG_SCR, tc);
1206
1207 DTLBIMVA tlbiOp(EL1,
1208 haveSecurity && !scr.ns,
1209 mbits(newVal, 31, 12),
1210 bits(newVal, 7,0));
1211
1212 tlbiOp(tc);
1213 return;
1214 }
1215 // Instruction TLB Invalidate by ASID match
1216 case MISCREG_ITLBIASID:
1217 {
1218 assert32(tc);
1219 scr = readMiscReg(MISCREG_SCR, tc);
1220
1221 ITLBIASID tlbiOp(EL1,
1222 haveSecurity && !scr.ns,
1223 bits(newVal, 7,0));
1224
1225 tlbiOp(tc);
1226 return;
1227 }
1228 // Data TLB Invalidate by ASID match
1229 case MISCREG_DTLBIASID:
1230 {
1231 assert32(tc);
1232 scr = readMiscReg(MISCREG_SCR, tc);
1233
1234 DTLBIASID tlbiOp(EL1,
1235 haveSecurity && !scr.ns,
1236 bits(newVal, 7,0));
1237
1238 tlbiOp(tc);
1239 return;
1240 }
1241 // TLB Invalidate All, Non-Secure Non-Hyp
1242 case MISCREG_TLBIALLNSNH:
1243 {
1244 assert32(tc);
1245
1246 TLBIALLN tlbiOp(EL1, false);
1247 tlbiOp(tc);
1248 return;
1249 }
1250 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1251 case MISCREG_TLBIALLNSNHIS:
1252 {
1253 assert32(tc);
1254
1255 TLBIALLN tlbiOp(EL1, false);
1256 tlbiOp.broadcast(tc);
1257 return;
1258 }
1259 // TLB Invalidate All, Hyp mode
1260 case MISCREG_TLBIALLH:
1261 {
1262 assert32(tc);
1263
1264 TLBIALLN tlbiOp(EL1, true);
1265 tlbiOp(tc);
1266 return;
1267 }
1268 // TLB Invalidate All, Hyp mode, Inner Shareable
1269 case MISCREG_TLBIALLHIS:
1270 {
1271 assert32(tc);
1272
1273 TLBIALLN tlbiOp(EL1, true);
1274 tlbiOp.broadcast(tc);
1275 return;
1276 }
1277 // AArch64 TLB Invalidate All, EL3
1278 case MISCREG_TLBI_ALLE3:
1279 {
1280 assert64(tc);
1281
1282 TLBIALL tlbiOp(EL3, true);
1283 tlbiOp(tc);
1284 return;
1285 }
1286 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1287 case MISCREG_TLBI_ALLE3IS:
1288 {
1289 assert64(tc);
1290
1291 TLBIALL tlbiOp(EL3, true);
1292 tlbiOp.broadcast(tc);
1293 return;
1294 }
1295 // @todo: uncomment this to enable Virtualization
1296 // case MISCREG_TLBI_ALLE2IS:
1297 // case MISCREG_TLBI_ALLE2:
1298 // AArch64 TLB Invalidate All, EL1
1299 case MISCREG_TLBI_ALLE1:
1300 case MISCREG_TLBI_VMALLE1:
1301 case MISCREG_TLBI_VMALLS12E1:
1302 // @todo: handle VMID and stage 2 to enable Virtualization
1303 {
1304 assert64(tc);
1305 scr = readMiscReg(MISCREG_SCR, tc);
1306
1307 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1308 tlbiOp(tc);
1309 return;
1310 }
1311 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1312 case MISCREG_TLBI_ALLE1IS:
1313 case MISCREG_TLBI_VMALLE1IS:
1314 case MISCREG_TLBI_VMALLS12E1IS:
1315 // @todo: handle VMID and stage 2 to enable Virtualization
1316 {
1317 assert64(tc);
1318 scr = readMiscReg(MISCREG_SCR, tc);
1319
1320 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1321 tlbiOp.broadcast(tc);
1322 return;
1323 }
1324 // VAEx(IS) and VALEx(IS) are the same because TLBs
1325 // only store entries
1326 // from the last level of translation table walks
1327 // @todo: handle VMID to enable Virtualization
1328 // AArch64 TLB Invalidate by VA, EL3
1329 case MISCREG_TLBI_VAE3_Xt:
1330 case MISCREG_TLBI_VALE3_Xt:
1331 {
1332 assert64(tc);
1333
1334 TLBIMVA tlbiOp(EL3, true,
1335 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1336 0xbeef);
1337 tlbiOp(tc);
1338 return;
1339 }
1340 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1341 case MISCREG_TLBI_VAE3IS_Xt:
1342 case MISCREG_TLBI_VALE3IS_Xt:
1343 {
1344 assert64(tc);
1345
1346 TLBIMVA tlbiOp(EL3, true,
1347 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1348 0xbeef);
1349
1350 tlbiOp.broadcast(tc);
1351 return;
1352 }
1353 // AArch64 TLB Invalidate by VA, EL2
1354 case MISCREG_TLBI_VAE2_Xt:
1355 case MISCREG_TLBI_VALE2_Xt:
1356 {
1357 assert64(tc);
1358 scr = readMiscReg(MISCREG_SCR, tc);
1359
1360 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1361 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1362 0xbeef);
1363 tlbiOp(tc);
1364 return;
1365 }
1366 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1367 case MISCREG_TLBI_VAE2IS_Xt:
1368 case MISCREG_TLBI_VALE2IS_Xt:
1369 {
1370 assert64(tc);
1371 scr = readMiscReg(MISCREG_SCR, tc);
1372
1373 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1374 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1375 0xbeef);
1376
1377 tlbiOp.broadcast(tc);
1378 return;
1379 }
1380 // AArch64 TLB Invalidate by VA, EL1
1381 case MISCREG_TLBI_VAE1_Xt:
1382 case MISCREG_TLBI_VALE1_Xt:
1383 {
1384 assert64(tc);
1385 scr = readMiscReg(MISCREG_SCR, tc);
1386 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1387 bits(newVal, 55, 48);
1388
1389 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1390 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1391 asid);
1392
1393 tlbiOp(tc);
1394 return;
1395 }
1396 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1397 case MISCREG_TLBI_VAE1IS_Xt:
1398 case MISCREG_TLBI_VALE1IS_Xt:
1399 {
1400 assert64(tc);
1401 scr = readMiscReg(MISCREG_SCR, tc);
1402 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1403 bits(newVal, 55, 48);
1404
1405 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1406 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1407 asid);
1408
1409 tlbiOp.broadcast(tc);
1410 return;
1411 }
1412 // AArch64 TLB Invalidate by ASID, EL1
1413 // @todo: handle VMID to enable Virtualization
1414 case MISCREG_TLBI_ASIDE1_Xt:
1415 {
1416 assert64(tc);
1417 scr = readMiscReg(MISCREG_SCR, tc);
1418 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1419 bits(newVal, 55, 48);
1420
1421 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1422 tlbiOp(tc);
1423 return;
1424 }
1425 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1426 case MISCREG_TLBI_ASIDE1IS_Xt:
1427 {
1428 assert64(tc);
1429 scr = readMiscReg(MISCREG_SCR, tc);
1430 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1431 bits(newVal, 55, 48);
1432
1433 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1434 tlbiOp.broadcast(tc);
1435 return;
1436 }
1437 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1438 // entries from the last level of translation table walks
1439 // AArch64 TLB Invalidate by VA, All ASID, EL1
1440 case MISCREG_TLBI_VAAE1_Xt:
1441 case MISCREG_TLBI_VAALE1_Xt:
1442 {
1443 assert64(tc);
1444 scr = readMiscReg(MISCREG_SCR, tc);
1445
1446 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1447 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1448
1449 tlbiOp(tc);
1450 return;
1451 }
1452 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1453 case MISCREG_TLBI_VAAE1IS_Xt:
1454 case MISCREG_TLBI_VAALE1IS_Xt:
1455 {
1456 assert64(tc);
1457 scr = readMiscReg(MISCREG_SCR, tc);
1458
1459 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1460 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1461
1462 tlbiOp.broadcast(tc);
1463 return;
1464 }
1465 // AArch64 TLB Invalidate by Intermediate Physical Address,
1466 // Stage 2, EL1
1467 case MISCREG_TLBI_IPAS2E1_Xt:
1468 case MISCREG_TLBI_IPAS2LE1_Xt:
1469 {
1470 assert64(tc);
1471 scr = readMiscReg(MISCREG_SCR, tc);
1472
1473 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1474 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1475
1476 tlbiOp(tc);
1477 return;
1478 }
1479 // AArch64 TLB Invalidate by Intermediate Physical Address,
1480 // Stage 2, EL1, Inner Shareable
1481 case MISCREG_TLBI_IPAS2E1IS_Xt:
1482 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1483 {
1484 assert64(tc);
1485 scr = readMiscReg(MISCREG_SCR, tc);
1486
1487 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1488 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1489
1490 tlbiOp.broadcast(tc);
1491 return;
1492 }
1493 case MISCREG_ACTLR:
1494 warn("Not doing anything for write of miscreg ACTLR\n");
1495 break;
1496
1497 case MISCREG_PMXEVTYPER_PMCCFILTR:
1498 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1499 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1500 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1501 pmu->setMiscReg(misc_reg, newVal);
1502 break;
1503
1504
1505 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1506 {
1507 HSTR hstrMask = 0;
1508 hstrMask.tjdbx = 1;
1509 newVal &= ~((uint32_t) hstrMask);
1510 break;
1511 }
1512 case MISCREG_HCPTR:
1513 {
1514 // If a CP bit in NSACR is 0 then the corresponding bit in
1515 // HCPTR is RAO/WI. Same applies to NSASEDIS
1516 secure_lookup = haveSecurity &&
1517 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1518 readMiscRegNoEffect(MISCREG_CPSR));
1519 if (!secure_lookup) {
1520 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1521 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1522 newVal = (newVal & ~mask) | (oldValue & mask);
1523 }
1524 break;
1525 }
1526 case MISCREG_HDFAR: // alias for secure DFAR
1527 misc_reg = MISCREG_DFAR_S;
1528 break;
1529 case MISCREG_HIFAR: // alias for secure IFAR
1530 misc_reg = MISCREG_IFAR_S;
1531 break;
1532 case MISCREG_ATS1CPR:
1533 case MISCREG_ATS1CPW:
1534 case MISCREG_ATS1CUR:
1535 case MISCREG_ATS1CUW:
1536 case MISCREG_ATS12NSOPR:
1537 case MISCREG_ATS12NSOPW:
1538 case MISCREG_ATS12NSOUR:
1539 case MISCREG_ATS12NSOUW:
1540 case MISCREG_ATS1HR:
1541 case MISCREG_ATS1HW:
1542 {
1543 Request::Flags flags = 0;
1544 BaseTLB::Mode mode = BaseTLB::Read;
1545 TLB::ArmTranslationType tranType = TLB::NormalTran;
1546 Fault fault;
1547 switch(misc_reg) {
1548 case MISCREG_ATS1CPR:
1549 flags = TLB::MustBeOne;
1550 tranType = TLB::S1CTran;
1551 mode = BaseTLB::Read;
1552 break;
1553 case MISCREG_ATS1CPW:
1554 flags = TLB::MustBeOne;
1555 tranType = TLB::S1CTran;
1556 mode = BaseTLB::Write;
1557 break;
1558 case MISCREG_ATS1CUR:
1559 flags = TLB::MustBeOne | TLB::UserMode;
1560 tranType = TLB::S1CTran;
1561 mode = BaseTLB::Read;
1562 break;
1563 case MISCREG_ATS1CUW:
1564 flags = TLB::MustBeOne | TLB::UserMode;
1565 tranType = TLB::S1CTran;
1566 mode = BaseTLB::Write;
1567 break;
1568 case MISCREG_ATS12NSOPR:
1569 if (!haveSecurity)
1570 panic("Security Extensions required for ATS12NSOPR");
1571 flags = TLB::MustBeOne;
1572 tranType = TLB::S1S2NsTran;
1573 mode = BaseTLB::Read;
1574 break;
1575 case MISCREG_ATS12NSOPW:
1576 if (!haveSecurity)
1577 panic("Security Extensions required for ATS12NSOPW");
1578 flags = TLB::MustBeOne;
1579 tranType = TLB::S1S2NsTran;
1580 mode = BaseTLB::Write;
1581 break;
1582 case MISCREG_ATS12NSOUR:
1583 if (!haveSecurity)
1584 panic("Security Extensions required for ATS12NSOUR");
1585 flags = TLB::MustBeOne | TLB::UserMode;
1586 tranType = TLB::S1S2NsTran;
1587 mode = BaseTLB::Read;
1588 break;
1589 case MISCREG_ATS12NSOUW:
1590 if (!haveSecurity)
1591 panic("Security Extensions required for ATS12NSOUW");
1592 flags = TLB::MustBeOne | TLB::UserMode;
1593 tranType = TLB::S1S2NsTran;
1594 mode = BaseTLB::Write;
1595 break;
1596 case MISCREG_ATS1HR: // only really useful from secure mode.
1597 flags = TLB::MustBeOne;
1598 tranType = TLB::HypMode;
1599 mode = BaseTLB::Read;
1600 break;
1601 case MISCREG_ATS1HW:
1602 flags = TLB::MustBeOne;
1603 tranType = TLB::HypMode;
1604 mode = BaseTLB::Write;
1605 break;
1606 }
1607 // If we're in timing mode then doing the translation in
1608 // functional mode then we're slightly distorting performance
1609 // results obtained from simulations. The translation should be
1610 // done in the same mode the core is running in. NOTE: This
1611 // can't be an atomic translation because that causes problems
1612 // with unexpected atomic snoop requests.
1613 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1614 Request req(0, val, 0, flags, Request::funcMasterId,
1615 tc->pcState().pc(), tc->contextId());
1616 fault = getDTBPtr(tc)->translateFunctional(
1617 &req, tc, mode, tranType);
1618 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1619 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1620
1621 MiscReg newVal;
1622 if (fault == NoFault) {
1623 Addr paddr = req.getPaddr();
1624 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1625 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1626 newVal = (paddr & mask(39, 12)) |
1627 (getDTBPtr(tc)->getAttr());
1628 } else {
1629 newVal = (paddr & 0xfffff000) |
1630 (getDTBPtr(tc)->getAttr());
1631 }
1632 DPRINTF(MiscRegs,
1633 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1634 val, newVal);
1635 } else {
1636 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1637 armFault->update(tc);
1638 // Set fault bit and FSR
1639 FSR fsr = armFault->getFsr(tc);
1640
1641 newVal = ((fsr >> 9) & 1) << 11;
1642 if (newVal) {
1643 // LPAE - rearange fault status
1644 newVal |= ((fsr >> 0) & 0x3f) << 1;
1645 } else {
1646 // VMSA - rearange fault status
1647 newVal |= ((fsr >> 0) & 0xf) << 1;
1648 newVal |= ((fsr >> 10) & 0x1) << 5;
1649 newVal |= ((fsr >> 12) & 0x1) << 6;
1650 }
1651 newVal |= 0x1; // F bit
1652 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1653 newVal |= armFault->isStage2() ? 0x200 : 0;
1654 DPRINTF(MiscRegs,
1655 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1656 val, fsr, newVal);
1657 }
1658 setMiscRegNoEffect(MISCREG_PAR, newVal);
1659 return;
1660 }
1661 case MISCREG_TTBCR:
1662 {
1663 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1664 const uint32_t ones = (uint32_t)(-1);
1665 TTBCR ttbcrMask = 0;
1666 TTBCR ttbcrNew = newVal;
1667
1668 // ARM DDI 0406C.b, ARMv7-32
1669 ttbcrMask.n = ones; // T0SZ
1670 if (haveSecurity) {
1671 ttbcrMask.pd0 = ones;
1672 ttbcrMask.pd1 = ones;
1673 }
1674 ttbcrMask.epd0 = ones;
1675 ttbcrMask.irgn0 = ones;
1676 ttbcrMask.orgn0 = ones;
1677 ttbcrMask.sh0 = ones;
1678 ttbcrMask.ps = ones; // T1SZ
1679 ttbcrMask.a1 = ones;
1680 ttbcrMask.epd1 = ones;
1681 ttbcrMask.irgn1 = ones;
1682 ttbcrMask.orgn1 = ones;
1683 ttbcrMask.sh1 = ones;
1684 if (haveLPAE)
1685 ttbcrMask.eae = ones;
1686
1687 if (haveLPAE && ttbcrNew.eae) {
1688 newVal = newVal & ttbcrMask;
1689 } else {
1690 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1691 }
1692 }
1693 M5_FALLTHROUGH;
1694 case MISCREG_TTBR0:
1695 case MISCREG_TTBR1:
1696 {
1697 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1698 if (haveLPAE) {
1699 if (ttbcr.eae) {
1700 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1701 // ARMv8 AArch32 bit 63-56 only
1702 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1703 newVal = (newVal & (~ttbrMask));
1704 }
1705 }
1706 }
1707 M5_FALLTHROUGH;
1708 case MISCREG_SCTLR_EL1:
1709 {
1710 getITBPtr(tc)->invalidateMiscReg();
1711 getDTBPtr(tc)->invalidateMiscReg();
1712 setMiscRegNoEffect(misc_reg, newVal);
1713 }
1714 M5_FALLTHROUGH;
1715 case MISCREG_CONTEXTIDR:
1716 case MISCREG_PRRR:
1717 case MISCREG_NMRR:
1718 case MISCREG_MAIR0:
1719 case MISCREG_MAIR1:
1720 case MISCREG_DACR:
1721 case MISCREG_VTTBR:
1722 case MISCREG_SCR_EL3:
1723 case MISCREG_HCR_EL2:
1724 case MISCREG_TCR_EL1:
1725 case MISCREG_TCR_EL2:
1726 case MISCREG_TCR_EL3:
1727 case MISCREG_SCTLR_EL2:
1728 case MISCREG_SCTLR_EL3:
1729 case MISCREG_HSCTLR:
1730 case MISCREG_TTBR0_EL1:
1731 case MISCREG_TTBR1_EL1:
1732 case MISCREG_TTBR0_EL2:
1733 case MISCREG_TTBR0_EL3:
1734 getITBPtr(tc)->invalidateMiscReg();
1735 getDTBPtr(tc)->invalidateMiscReg();
1736 break;
1737 case MISCREG_NZCV:
1738 {
1739 CPSR cpsr = val;
1740
1741 tc->setCCReg(CCREG_NZ, cpsr.nz);
1742 tc->setCCReg(CCREG_C, cpsr.c);
1743 tc->setCCReg(CCREG_V, cpsr.v);
1744 }
1745 break;
1746 case MISCREG_DAIF:
1747 {
1748 CPSR cpsr = miscRegs[MISCREG_CPSR];
1749 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1750 newVal = cpsr;
1751 misc_reg = MISCREG_CPSR;
1752 }
1753 break;
1754 case MISCREG_SP_EL0:
1755 tc->setIntReg(INTREG_SP0, newVal);
1756 break;
1757 case MISCREG_SP_EL1:
1758 tc->setIntReg(INTREG_SP1, newVal);
1759 break;
1760 case MISCREG_SP_EL2:
1761 tc->setIntReg(INTREG_SP2, newVal);
1762 break;
1763 case MISCREG_SPSEL:
1764 {
1765 CPSR cpsr = miscRegs[MISCREG_CPSR];
1766 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1767 newVal = cpsr;
1768 misc_reg = MISCREG_CPSR;
1769 }
1770 break;
1771 case MISCREG_CURRENTEL:
1772 {
1773 CPSR cpsr = miscRegs[MISCREG_CPSR];
1774 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1775 newVal = cpsr;
1776 misc_reg = MISCREG_CPSR;
1777 }
1778 break;
1779 case MISCREG_AT_S1E1R_Xt:
1780 case MISCREG_AT_S1E1W_Xt:
1781 case MISCREG_AT_S1E0R_Xt:
1782 case MISCREG_AT_S1E0W_Xt:
1783 case MISCREG_AT_S1E2R_Xt:
1784 case MISCREG_AT_S1E2W_Xt:
1785 case MISCREG_AT_S12E1R_Xt:
1786 case MISCREG_AT_S12E1W_Xt:
1787 case MISCREG_AT_S12E0R_Xt:
1788 case MISCREG_AT_S12E0W_Xt:
1789 case MISCREG_AT_S1E3R_Xt:
1790 case MISCREG_AT_S1E3W_Xt:
1791 {
1792 RequestPtr req = new Request;
1793 Request::Flags flags = 0;
1794 BaseTLB::Mode mode = BaseTLB::Read;
1795 TLB::ArmTranslationType tranType = TLB::NormalTran;
1796 Fault fault;
1797 switch(misc_reg) {
1798 case MISCREG_AT_S1E1R_Xt:
1799 flags = TLB::MustBeOne;
1800 tranType = TLB::S1E1Tran;
1801 mode = BaseTLB::Read;
1802 break;
1803 case MISCREG_AT_S1E1W_Xt:
1804 flags = TLB::MustBeOne;
1805 tranType = TLB::S1E1Tran;
1806 mode = BaseTLB::Write;
1807 break;
1808 case MISCREG_AT_S1E0R_Xt:
1809 flags = TLB::MustBeOne | TLB::UserMode;
1810 tranType = TLB::S1E0Tran;
1811 mode = BaseTLB::Read;
1812 break;
1813 case MISCREG_AT_S1E0W_Xt:
1814 flags = TLB::MustBeOne | TLB::UserMode;
1815 tranType = TLB::S1E0Tran;
1816 mode = BaseTLB::Write;
1817 break;
1818 case MISCREG_AT_S1E2R_Xt:
1819 flags = TLB::MustBeOne;
1820 tranType = TLB::S1E2Tran;
1821 mode = BaseTLB::Read;
1822 break;
1823 case MISCREG_AT_S1E2W_Xt:
1824 flags = TLB::MustBeOne;
1825 tranType = TLB::S1E2Tran;
1826 mode = BaseTLB::Write;
1827 break;
1828 case MISCREG_AT_S12E0R_Xt:
1829 flags = TLB::MustBeOne | TLB::UserMode;
1830 tranType = TLB::S12E0Tran;
1831 mode = BaseTLB::Read;
1832 break;
1833 case MISCREG_AT_S12E0W_Xt:
1834 flags = TLB::MustBeOne | TLB::UserMode;
1835 tranType = TLB::S12E0Tran;
1836 mode = BaseTLB::Write;
1837 break;
1838 case MISCREG_AT_S12E1R_Xt:
1839 flags = TLB::MustBeOne;
1840 tranType = TLB::S12E1Tran;
1841 mode = BaseTLB::Read;
1842 break;
1843 case MISCREG_AT_S12E1W_Xt:
1844 flags = TLB::MustBeOne;
1845 tranType = TLB::S12E1Tran;
1846 mode = BaseTLB::Write;
1847 break;
1848 case MISCREG_AT_S1E3R_Xt:
1849 flags = TLB::MustBeOne;
1850 tranType = TLB::S1E3Tran;
1851 mode = BaseTLB::Read;
1852 break;
1853 case MISCREG_AT_S1E3W_Xt:
1854 flags = TLB::MustBeOne;
1855 tranType = TLB::S1E3Tran;
1856 mode = BaseTLB::Write;
1857 break;
1858 }
1859 // If we're in timing mode then doing the translation in
1860 // functional mode then we're slightly distorting performance
1861 // results obtained from simulations. The translation should be
1862 // done in the same mode the core is running in. NOTE: This
1863 // can't be an atomic translation because that causes problems
1864 // with unexpected atomic snoop requests.
1865 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1866 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1867 tc->pcState().pc());
1868 req->setContext(tc->contextId());
1869 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1870 tranType);
1871
1872 MiscReg newVal;
1873 if (fault == NoFault) {
1874 Addr paddr = req->getPaddr();
1875 uint64_t attr = getDTBPtr(tc)->getAttr();
1876 uint64_t attr1 = attr >> 56;
1877 if (!attr1 || attr1 ==0x44) {
1878 attr |= 0x100;
1879 attr &= ~ uint64_t(0x80);
1880 }
1881 newVal = (paddr & mask(47, 12)) | attr;
1882 DPRINTF(MiscRegs,
1883 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1884 val, newVal);
1885 } else {
1886 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1887 armFault->update(tc);
1888 // Set fault bit and FSR
1889 FSR fsr = armFault->getFsr(tc);
1890
1891 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1892 if (cpsr.width) { // AArch32
1893 newVal = ((fsr >> 9) & 1) << 11;
1894 // rearrange fault status
1895 newVal |= ((fsr >> 0) & 0x3f) << 1;
1896 newVal |= 0x1; // F bit
1897 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1898 newVal |= armFault->isStage2() ? 0x200 : 0;
1899 } else { // AArch64
1900 newVal = 1; // F bit
1901 newVal |= fsr << 1; // FST
1902 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1903 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1904 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1905 newVal |= 1 << 11; // RES1
1906 }
1907 DPRINTF(MiscRegs,
1908 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1909 val, fsr, newVal);
1910 }
1911 delete req;
1912 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1913 return;
1914 }
1915 case MISCREG_SPSR_EL3:
1916 case MISCREG_SPSR_EL2:
1917 case MISCREG_SPSR_EL1:
1918 // Force bits 23:21 to 0
1919 newVal = val & ~(0x7 << 21);
1920 break;
1921 case MISCREG_L2CTLR:
1922 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1923 miscRegName[misc_reg], uint32_t(val));
1924 break;
1925
1926 // Generic Timer registers
1927 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1928 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1929 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1930 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1931 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1932 break;
1933 }
1934 }
1935 setMiscRegNoEffect(misc_reg, newVal);
1936}
1937
1938BaseISADevice &
1939ISA::getGenericTimer(ThreadContext *tc)
1940{
1941 // We only need to create an ISA interface the first time we try
1942 // to access the timer.
1943 if (timer)
1944 return *timer.get();
1945
1946 assert(system);
1947 GenericTimer *generic_timer(system->getGenericTimer());
1948 if (!generic_timer) {
1949 panic("Trying to get a generic timer from a system that hasn't "
1950 "been configured to use a generic timer.\n");
1951 }
1952
1953 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1954 return *timer.get();
1955}
1956
1957}
1958
1959ArmISA::ISA *
1960ArmISAParams::create()
1961{
1962 return new ArmISA::ISA(this);
1963}
| 963 SCTLR sctlr = miscRegs[sctlr_idx];
964 SCTLR new_sctlr = newVal;
965 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
966 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
967 getITBPtr(tc)->invalidateMiscReg();
968 getDTBPtr(tc)->invalidateMiscReg();
969 }
970 case MISCREG_MIDR:
971 case MISCREG_ID_PFR0:
972 case MISCREG_ID_PFR1:
973 case MISCREG_ID_DFR0:
974 case MISCREG_ID_MMFR0:
975 case MISCREG_ID_MMFR1:
976 case MISCREG_ID_MMFR2:
977 case MISCREG_ID_MMFR3:
978 case MISCREG_ID_ISAR0:
979 case MISCREG_ID_ISAR1:
980 case MISCREG_ID_ISAR2:
981 case MISCREG_ID_ISAR3:
982 case MISCREG_ID_ISAR4:
983 case MISCREG_ID_ISAR5:
984
985 case MISCREG_MPIDR:
986 case MISCREG_FPSID:
987 case MISCREG_TLBTR:
988 case MISCREG_MVFR0:
989 case MISCREG_MVFR1:
990
991 case MISCREG_ID_AA64AFR0_EL1:
992 case MISCREG_ID_AA64AFR1_EL1:
993 case MISCREG_ID_AA64DFR0_EL1:
994 case MISCREG_ID_AA64DFR1_EL1:
995 case MISCREG_ID_AA64ISAR0_EL1:
996 case MISCREG_ID_AA64ISAR1_EL1:
997 case MISCREG_ID_AA64MMFR0_EL1:
998 case MISCREG_ID_AA64MMFR1_EL1:
999 case MISCREG_ID_AA64PFR0_EL1:
1000 case MISCREG_ID_AA64PFR1_EL1:
1001 // ID registers are constants.
1002 return;
1003
1004 // TLB Invalidate All
1005 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1006 {
1007 assert32(tc);
1008 scr = readMiscReg(MISCREG_SCR, tc);
1009
1010 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1011 tlbiOp(tc);
1012 return;
1013 }
1014 // TLB Invalidate All, Inner Shareable
1015 case MISCREG_TLBIALLIS:
1016 {
1017 assert32(tc);
1018 scr = readMiscReg(MISCREG_SCR, tc);
1019
1020 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1021 tlbiOp.broadcast(tc);
1022 return;
1023 }
1024 // Instruction TLB Invalidate All
1025 case MISCREG_ITLBIALL:
1026 {
1027 assert32(tc);
1028 scr = readMiscReg(MISCREG_SCR, tc);
1029
1030 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1031 tlbiOp(tc);
1032 return;
1033 }
1034 // Data TLB Invalidate All
1035 case MISCREG_DTLBIALL:
1036 {
1037 assert32(tc);
1038 scr = readMiscReg(MISCREG_SCR, tc);
1039
1040 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1041 tlbiOp(tc);
1042 return;
1043 }
1044 // TLB Invalidate by VA
1045 // mcr tlbimval(is) is invalidating all matching entries
1046 // regardless of the level of lookup, since in gem5 we cache
1047 // in the tlb the last level of lookup only.
1048 case MISCREG_TLBIMVA:
1049 case MISCREG_TLBIMVAL:
1050 {
1051 assert32(tc);
1052 scr = readMiscReg(MISCREG_SCR, tc);
1053
1054 TLBIMVA tlbiOp(EL1,
1055 haveSecurity && !scr.ns,
1056 mbits(newVal, 31, 12),
1057 bits(newVal, 7,0));
1058
1059 tlbiOp(tc);
1060 return;
1061 }
1062 // TLB Invalidate by VA, Inner Shareable
1063 case MISCREG_TLBIMVAIS:
1064 case MISCREG_TLBIMVALIS:
1065 {
1066 assert32(tc);
1067 scr = readMiscReg(MISCREG_SCR, tc);
1068
1069 TLBIMVA tlbiOp(EL1,
1070 haveSecurity && !scr.ns,
1071 mbits(newVal, 31, 12),
1072 bits(newVal, 7,0));
1073
1074 tlbiOp.broadcast(tc);
1075 return;
1076 }
1077 // TLB Invalidate by ASID match
1078 case MISCREG_TLBIASID:
1079 {
1080 assert32(tc);
1081 scr = readMiscReg(MISCREG_SCR, tc);
1082
1083 TLBIASID tlbiOp(EL1,
1084 haveSecurity && !scr.ns,
1085 bits(newVal, 7,0));
1086
1087 tlbiOp(tc);
1088 return;
1089 }
1090 // TLB Invalidate by ASID match, Inner Shareable
1091 case MISCREG_TLBIASIDIS:
1092 {
1093 assert32(tc);
1094 scr = readMiscReg(MISCREG_SCR, tc);
1095
1096 TLBIASID tlbiOp(EL1,
1097 haveSecurity && !scr.ns,
1098 bits(newVal, 7,0));
1099
1100 tlbiOp.broadcast(tc);
1101 return;
1102 }
1103 // mcr tlbimvaal(is) is invalidating all matching entries
1104 // regardless of the level of lookup, since in gem5 we cache
1105 // in the tlb the last level of lookup only.
1106 // TLB Invalidate by VA, All ASID
1107 case MISCREG_TLBIMVAA:
1108 case MISCREG_TLBIMVAAL:
1109 {
1110 assert32(tc);
1111 scr = readMiscReg(MISCREG_SCR, tc);
1112
1113 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1114 mbits(newVal, 31,12), false);
1115
1116 tlbiOp(tc);
1117 return;
1118 }
1119 // TLB Invalidate by VA, All ASID, Inner Shareable
1120 case MISCREG_TLBIMVAAIS:
1121 case MISCREG_TLBIMVAALIS:
1122 {
1123 assert32(tc);
1124 scr = readMiscReg(MISCREG_SCR, tc);
1125
1126 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1127 mbits(newVal, 31,12), false);
1128
1129 tlbiOp.broadcast(tc);
1130 return;
1131 }
1132 // mcr tlbimvalh(is) is invalidating all matching entries
1133 // regardless of the level of lookup, since in gem5 we cache
1134 // in the tlb the last level of lookup only.
1135 // TLB Invalidate by VA, Hyp mode
1136 case MISCREG_TLBIMVAH:
1137 case MISCREG_TLBIMVALH:
1138 {
1139 assert32(tc);
1140 scr = readMiscReg(MISCREG_SCR, tc);
1141
1142 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1143 mbits(newVal, 31,12), true);
1144
1145 tlbiOp(tc);
1146 return;
1147 }
1148 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1149 case MISCREG_TLBIMVAHIS:
1150 case MISCREG_TLBIMVALHIS:
1151 {
1152 assert32(tc);
1153 scr = readMiscReg(MISCREG_SCR, tc);
1154
1155 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1156 mbits(newVal, 31,12), true);
1157
1158 tlbiOp.broadcast(tc);
1159 return;
1160 }
1161 // mcr tlbiipas2l(is) is invalidating all matching entries
1162 // regardless of the level of lookup, since in gem5 we cache
1163 // in the tlb the last level of lookup only.
1164 // TLB Invalidate by Intermediate Physical Address, Stage 2
1165 case MISCREG_TLBIIPAS2:
1166 case MISCREG_TLBIIPAS2L:
1167 {
1168 assert32(tc);
1169 scr = readMiscReg(MISCREG_SCR, tc);
1170
1171 TLBIIPA tlbiOp(EL1,
1172 haveSecurity && !scr.ns,
1173 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1174
1175 tlbiOp(tc);
1176 return;
1177 }
1178 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1179 // Inner Shareable
1180 case MISCREG_TLBIIPAS2IS:
1181 case MISCREG_TLBIIPAS2LIS:
1182 {
1183 assert32(tc);
1184 scr = readMiscReg(MISCREG_SCR, tc);
1185
1186 TLBIIPA tlbiOp(EL1,
1187 haveSecurity && !scr.ns,
1188 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1189
1190 tlbiOp.broadcast(tc);
1191 return;
1192 }
1193 // Instruction TLB Invalidate by VA
1194 case MISCREG_ITLBIMVA:
1195 {
1196 assert32(tc);
1197 scr = readMiscReg(MISCREG_SCR, tc);
1198
1199 ITLBIMVA tlbiOp(EL1,
1200 haveSecurity && !scr.ns,
1201 mbits(newVal, 31, 12),
1202 bits(newVal, 7,0));
1203
1204 tlbiOp(tc);
1205 return;
1206 }
1207 // Data TLB Invalidate by VA
1208 case MISCREG_DTLBIMVA:
1209 {
1210 assert32(tc);
1211 scr = readMiscReg(MISCREG_SCR, tc);
1212
1213 DTLBIMVA tlbiOp(EL1,
1214 haveSecurity && !scr.ns,
1215 mbits(newVal, 31, 12),
1216 bits(newVal, 7,0));
1217
1218 tlbiOp(tc);
1219 return;
1220 }
1221 // Instruction TLB Invalidate by ASID match
1222 case MISCREG_ITLBIASID:
1223 {
1224 assert32(tc);
1225 scr = readMiscReg(MISCREG_SCR, tc);
1226
1227 ITLBIASID tlbiOp(EL1,
1228 haveSecurity && !scr.ns,
1229 bits(newVal, 7,0));
1230
1231 tlbiOp(tc);
1232 return;
1233 }
1234 // Data TLB Invalidate by ASID match
1235 case MISCREG_DTLBIASID:
1236 {
1237 assert32(tc);
1238 scr = readMiscReg(MISCREG_SCR, tc);
1239
1240 DTLBIASID tlbiOp(EL1,
1241 haveSecurity && !scr.ns,
1242 bits(newVal, 7,0));
1243
1244 tlbiOp(tc);
1245 return;
1246 }
1247 // TLB Invalidate All, Non-Secure Non-Hyp
1248 case MISCREG_TLBIALLNSNH:
1249 {
1250 assert32(tc);
1251
1252 TLBIALLN tlbiOp(EL1, false);
1253 tlbiOp(tc);
1254 return;
1255 }
1256 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1257 case MISCREG_TLBIALLNSNHIS:
1258 {
1259 assert32(tc);
1260
1261 TLBIALLN tlbiOp(EL1, false);
1262 tlbiOp.broadcast(tc);
1263 return;
1264 }
1265 // TLB Invalidate All, Hyp mode
1266 case MISCREG_TLBIALLH:
1267 {
1268 assert32(tc);
1269
1270 TLBIALLN tlbiOp(EL1, true);
1271 tlbiOp(tc);
1272 return;
1273 }
1274 // TLB Invalidate All, Hyp mode, Inner Shareable
1275 case MISCREG_TLBIALLHIS:
1276 {
1277 assert32(tc);
1278
1279 TLBIALLN tlbiOp(EL1, true);
1280 tlbiOp.broadcast(tc);
1281 return;
1282 }
1283 // AArch64 TLB Invalidate All, EL3
1284 case MISCREG_TLBI_ALLE3:
1285 {
1286 assert64(tc);
1287
1288 TLBIALL tlbiOp(EL3, true);
1289 tlbiOp(tc);
1290 return;
1291 }
1292 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1293 case MISCREG_TLBI_ALLE3IS:
1294 {
1295 assert64(tc);
1296
1297 TLBIALL tlbiOp(EL3, true);
1298 tlbiOp.broadcast(tc);
1299 return;
1300 }
1301 // @todo: uncomment this to enable Virtualization
1302 // case MISCREG_TLBI_ALLE2IS:
1303 // case MISCREG_TLBI_ALLE2:
1304 // AArch64 TLB Invalidate All, EL1
1305 case MISCREG_TLBI_ALLE1:
1306 case MISCREG_TLBI_VMALLE1:
1307 case MISCREG_TLBI_VMALLS12E1:
1308 // @todo: handle VMID and stage 2 to enable Virtualization
1309 {
1310 assert64(tc);
1311 scr = readMiscReg(MISCREG_SCR, tc);
1312
1313 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1314 tlbiOp(tc);
1315 return;
1316 }
1317 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1318 case MISCREG_TLBI_ALLE1IS:
1319 case MISCREG_TLBI_VMALLE1IS:
1320 case MISCREG_TLBI_VMALLS12E1IS:
1321 // @todo: handle VMID and stage 2 to enable Virtualization
1322 {
1323 assert64(tc);
1324 scr = readMiscReg(MISCREG_SCR, tc);
1325
1326 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1327 tlbiOp.broadcast(tc);
1328 return;
1329 }
1330 // VAEx(IS) and VALEx(IS) are the same because TLBs
1331 // only store entries
1332 // from the last level of translation table walks
1333 // @todo: handle VMID to enable Virtualization
1334 // AArch64 TLB Invalidate by VA, EL3
1335 case MISCREG_TLBI_VAE3_Xt:
1336 case MISCREG_TLBI_VALE3_Xt:
1337 {
1338 assert64(tc);
1339
1340 TLBIMVA tlbiOp(EL3, true,
1341 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1342 0xbeef);
1343 tlbiOp(tc);
1344 return;
1345 }
1346 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1347 case MISCREG_TLBI_VAE3IS_Xt:
1348 case MISCREG_TLBI_VALE3IS_Xt:
1349 {
1350 assert64(tc);
1351
1352 TLBIMVA tlbiOp(EL3, true,
1353 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1354 0xbeef);
1355
1356 tlbiOp.broadcast(tc);
1357 return;
1358 }
1359 // AArch64 TLB Invalidate by VA, EL2
1360 case MISCREG_TLBI_VAE2_Xt:
1361 case MISCREG_TLBI_VALE2_Xt:
1362 {
1363 assert64(tc);
1364 scr = readMiscReg(MISCREG_SCR, tc);
1365
1366 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1367 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1368 0xbeef);
1369 tlbiOp(tc);
1370 return;
1371 }
1372 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1373 case MISCREG_TLBI_VAE2IS_Xt:
1374 case MISCREG_TLBI_VALE2IS_Xt:
1375 {
1376 assert64(tc);
1377 scr = readMiscReg(MISCREG_SCR, tc);
1378
1379 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1380 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1381 0xbeef);
1382
1383 tlbiOp.broadcast(tc);
1384 return;
1385 }
1386 // AArch64 TLB Invalidate by VA, EL1
1387 case MISCREG_TLBI_VAE1_Xt:
1388 case MISCREG_TLBI_VALE1_Xt:
1389 {
1390 assert64(tc);
1391 scr = readMiscReg(MISCREG_SCR, tc);
1392 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1393 bits(newVal, 55, 48);
1394
1395 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1396 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1397 asid);
1398
1399 tlbiOp(tc);
1400 return;
1401 }
1402 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1403 case MISCREG_TLBI_VAE1IS_Xt:
1404 case MISCREG_TLBI_VALE1IS_Xt:
1405 {
1406 assert64(tc);
1407 scr = readMiscReg(MISCREG_SCR, tc);
1408 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1409 bits(newVal, 55, 48);
1410
1411 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1412 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1413 asid);
1414
1415 tlbiOp.broadcast(tc);
1416 return;
1417 }
1418 // AArch64 TLB Invalidate by ASID, EL1
1419 // @todo: handle VMID to enable Virtualization
1420 case MISCREG_TLBI_ASIDE1_Xt:
1421 {
1422 assert64(tc);
1423 scr = readMiscReg(MISCREG_SCR, tc);
1424 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1425 bits(newVal, 55, 48);
1426
1427 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1428 tlbiOp(tc);
1429 return;
1430 }
1431 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1432 case MISCREG_TLBI_ASIDE1IS_Xt:
1433 {
1434 assert64(tc);
1435 scr = readMiscReg(MISCREG_SCR, tc);
1436 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1437 bits(newVal, 55, 48);
1438
1439 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1440 tlbiOp.broadcast(tc);
1441 return;
1442 }
1443 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1444 // entries from the last level of translation table walks
1445 // AArch64 TLB Invalidate by VA, All ASID, EL1
1446 case MISCREG_TLBI_VAAE1_Xt:
1447 case MISCREG_TLBI_VAALE1_Xt:
1448 {
1449 assert64(tc);
1450 scr = readMiscReg(MISCREG_SCR, tc);
1451
1452 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1453 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1454
1455 tlbiOp(tc);
1456 return;
1457 }
1458 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1459 case MISCREG_TLBI_VAAE1IS_Xt:
1460 case MISCREG_TLBI_VAALE1IS_Xt:
1461 {
1462 assert64(tc);
1463 scr = readMiscReg(MISCREG_SCR, tc);
1464
1465 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1466 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1467
1468 tlbiOp.broadcast(tc);
1469 return;
1470 }
1471 // AArch64 TLB Invalidate by Intermediate Physical Address,
1472 // Stage 2, EL1
1473 case MISCREG_TLBI_IPAS2E1_Xt:
1474 case MISCREG_TLBI_IPAS2LE1_Xt:
1475 {
1476 assert64(tc);
1477 scr = readMiscReg(MISCREG_SCR, tc);
1478
1479 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1480 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1481
1482 tlbiOp(tc);
1483 return;
1484 }
1485 // AArch64 TLB Invalidate by Intermediate Physical Address,
1486 // Stage 2, EL1, Inner Shareable
1487 case MISCREG_TLBI_IPAS2E1IS_Xt:
1488 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1489 {
1490 assert64(tc);
1491 scr = readMiscReg(MISCREG_SCR, tc);
1492
1493 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1494 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1495
1496 tlbiOp.broadcast(tc);
1497 return;
1498 }
1499 case MISCREG_ACTLR:
1500 warn("Not doing anything for write of miscreg ACTLR\n");
1501 break;
1502
1503 case MISCREG_PMXEVTYPER_PMCCFILTR:
1504 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1505 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1506 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1507 pmu->setMiscReg(misc_reg, newVal);
1508 break;
1509
1510
1511 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1512 {
1513 HSTR hstrMask = 0;
1514 hstrMask.tjdbx = 1;
1515 newVal &= ~((uint32_t) hstrMask);
1516 break;
1517 }
1518 case MISCREG_HCPTR:
1519 {
1520 // If a CP bit in NSACR is 0 then the corresponding bit in
1521 // HCPTR is RAO/WI. Same applies to NSASEDIS
1522 secure_lookup = haveSecurity &&
1523 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1524 readMiscRegNoEffect(MISCREG_CPSR));
1525 if (!secure_lookup) {
1526 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1527 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1528 newVal = (newVal & ~mask) | (oldValue & mask);
1529 }
1530 break;
1531 }
1532 case MISCREG_HDFAR: // alias for secure DFAR
1533 misc_reg = MISCREG_DFAR_S;
1534 break;
1535 case MISCREG_HIFAR: // alias for secure IFAR
1536 misc_reg = MISCREG_IFAR_S;
1537 break;
1538 case MISCREG_ATS1CPR:
1539 case MISCREG_ATS1CPW:
1540 case MISCREG_ATS1CUR:
1541 case MISCREG_ATS1CUW:
1542 case MISCREG_ATS12NSOPR:
1543 case MISCREG_ATS12NSOPW:
1544 case MISCREG_ATS12NSOUR:
1545 case MISCREG_ATS12NSOUW:
1546 case MISCREG_ATS1HR:
1547 case MISCREG_ATS1HW:
1548 {
1549 Request::Flags flags = 0;
1550 BaseTLB::Mode mode = BaseTLB::Read;
1551 TLB::ArmTranslationType tranType = TLB::NormalTran;
1552 Fault fault;
1553 switch(misc_reg) {
1554 case MISCREG_ATS1CPR:
1555 flags = TLB::MustBeOne;
1556 tranType = TLB::S1CTran;
1557 mode = BaseTLB::Read;
1558 break;
1559 case MISCREG_ATS1CPW:
1560 flags = TLB::MustBeOne;
1561 tranType = TLB::S1CTran;
1562 mode = BaseTLB::Write;
1563 break;
1564 case MISCREG_ATS1CUR:
1565 flags = TLB::MustBeOne | TLB::UserMode;
1566 tranType = TLB::S1CTran;
1567 mode = BaseTLB::Read;
1568 break;
1569 case MISCREG_ATS1CUW:
1570 flags = TLB::MustBeOne | TLB::UserMode;
1571 tranType = TLB::S1CTran;
1572 mode = BaseTLB::Write;
1573 break;
1574 case MISCREG_ATS12NSOPR:
1575 if (!haveSecurity)
1576 panic("Security Extensions required for ATS12NSOPR");
1577 flags = TLB::MustBeOne;
1578 tranType = TLB::S1S2NsTran;
1579 mode = BaseTLB::Read;
1580 break;
1581 case MISCREG_ATS12NSOPW:
1582 if (!haveSecurity)
1583 panic("Security Extensions required for ATS12NSOPW");
1584 flags = TLB::MustBeOne;
1585 tranType = TLB::S1S2NsTran;
1586 mode = BaseTLB::Write;
1587 break;
1588 case MISCREG_ATS12NSOUR:
1589 if (!haveSecurity)
1590 panic("Security Extensions required for ATS12NSOUR");
1591 flags = TLB::MustBeOne | TLB::UserMode;
1592 tranType = TLB::S1S2NsTran;
1593 mode = BaseTLB::Read;
1594 break;
1595 case MISCREG_ATS12NSOUW:
1596 if (!haveSecurity)
1597 panic("Security Extensions required for ATS12NSOUW");
1598 flags = TLB::MustBeOne | TLB::UserMode;
1599 tranType = TLB::S1S2NsTran;
1600 mode = BaseTLB::Write;
1601 break;
1602 case MISCREG_ATS1HR: // only really useful from secure mode.
1603 flags = TLB::MustBeOne;
1604 tranType = TLB::HypMode;
1605 mode = BaseTLB::Read;
1606 break;
1607 case MISCREG_ATS1HW:
1608 flags = TLB::MustBeOne;
1609 tranType = TLB::HypMode;
1610 mode = BaseTLB::Write;
1611 break;
1612 }
1613 // If we're in timing mode then doing the translation in
1614 // functional mode then we're slightly distorting performance
1615 // results obtained from simulations. The translation should be
1616 // done in the same mode the core is running in. NOTE: This
1617 // can't be an atomic translation because that causes problems
1618 // with unexpected atomic snoop requests.
1619 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1620 Request req(0, val, 0, flags, Request::funcMasterId,
1621 tc->pcState().pc(), tc->contextId());
1622 fault = getDTBPtr(tc)->translateFunctional(
1623 &req, tc, mode, tranType);
1624 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1625 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1626
1627 MiscReg newVal;
1628 if (fault == NoFault) {
1629 Addr paddr = req.getPaddr();
1630 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1631 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1632 newVal = (paddr & mask(39, 12)) |
1633 (getDTBPtr(tc)->getAttr());
1634 } else {
1635 newVal = (paddr & 0xfffff000) |
1636 (getDTBPtr(tc)->getAttr());
1637 }
1638 DPRINTF(MiscRegs,
1639 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1640 val, newVal);
1641 } else {
1642 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1643 armFault->update(tc);
1644 // Set fault bit and FSR
1645 FSR fsr = armFault->getFsr(tc);
1646
1647 newVal = ((fsr >> 9) & 1) << 11;
1648 if (newVal) {
1649 // LPAE - rearange fault status
1650 newVal |= ((fsr >> 0) & 0x3f) << 1;
1651 } else {
1652 // VMSA - rearange fault status
1653 newVal |= ((fsr >> 0) & 0xf) << 1;
1654 newVal |= ((fsr >> 10) & 0x1) << 5;
1655 newVal |= ((fsr >> 12) & 0x1) << 6;
1656 }
1657 newVal |= 0x1; // F bit
1658 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1659 newVal |= armFault->isStage2() ? 0x200 : 0;
1660 DPRINTF(MiscRegs,
1661 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1662 val, fsr, newVal);
1663 }
1664 setMiscRegNoEffect(MISCREG_PAR, newVal);
1665 return;
1666 }
1667 case MISCREG_TTBCR:
1668 {
1669 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1670 const uint32_t ones = (uint32_t)(-1);
1671 TTBCR ttbcrMask = 0;
1672 TTBCR ttbcrNew = newVal;
1673
1674 // ARM DDI 0406C.b, ARMv7-32
1675 ttbcrMask.n = ones; // T0SZ
1676 if (haveSecurity) {
1677 ttbcrMask.pd0 = ones;
1678 ttbcrMask.pd1 = ones;
1679 }
1680 ttbcrMask.epd0 = ones;
1681 ttbcrMask.irgn0 = ones;
1682 ttbcrMask.orgn0 = ones;
1683 ttbcrMask.sh0 = ones;
1684 ttbcrMask.ps = ones; // T1SZ
1685 ttbcrMask.a1 = ones;
1686 ttbcrMask.epd1 = ones;
1687 ttbcrMask.irgn1 = ones;
1688 ttbcrMask.orgn1 = ones;
1689 ttbcrMask.sh1 = ones;
1690 if (haveLPAE)
1691 ttbcrMask.eae = ones;
1692
1693 if (haveLPAE && ttbcrNew.eae) {
1694 newVal = newVal & ttbcrMask;
1695 } else {
1696 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1697 }
1698 }
1699 M5_FALLTHROUGH;
1700 case MISCREG_TTBR0:
1701 case MISCREG_TTBR1:
1702 {
1703 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1704 if (haveLPAE) {
1705 if (ttbcr.eae) {
1706 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1707 // ARMv8 AArch32 bit 63-56 only
1708 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1709 newVal = (newVal & (~ttbrMask));
1710 }
1711 }
1712 }
1713 M5_FALLTHROUGH;
1714 case MISCREG_SCTLR_EL1:
1715 {
1716 getITBPtr(tc)->invalidateMiscReg();
1717 getDTBPtr(tc)->invalidateMiscReg();
1718 setMiscRegNoEffect(misc_reg, newVal);
1719 }
1720 M5_FALLTHROUGH;
1721 case MISCREG_CONTEXTIDR:
1722 case MISCREG_PRRR:
1723 case MISCREG_NMRR:
1724 case MISCREG_MAIR0:
1725 case MISCREG_MAIR1:
1726 case MISCREG_DACR:
1727 case MISCREG_VTTBR:
1728 case MISCREG_SCR_EL3:
1729 case MISCREG_HCR_EL2:
1730 case MISCREG_TCR_EL1:
1731 case MISCREG_TCR_EL2:
1732 case MISCREG_TCR_EL3:
1733 case MISCREG_SCTLR_EL2:
1734 case MISCREG_SCTLR_EL3:
1735 case MISCREG_HSCTLR:
1736 case MISCREG_TTBR0_EL1:
1737 case MISCREG_TTBR1_EL1:
1738 case MISCREG_TTBR0_EL2:
1739 case MISCREG_TTBR0_EL3:
1740 getITBPtr(tc)->invalidateMiscReg();
1741 getDTBPtr(tc)->invalidateMiscReg();
1742 break;
1743 case MISCREG_NZCV:
1744 {
1745 CPSR cpsr = val;
1746
1747 tc->setCCReg(CCREG_NZ, cpsr.nz);
1748 tc->setCCReg(CCREG_C, cpsr.c);
1749 tc->setCCReg(CCREG_V, cpsr.v);
1750 }
1751 break;
1752 case MISCREG_DAIF:
1753 {
1754 CPSR cpsr = miscRegs[MISCREG_CPSR];
1755 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1756 newVal = cpsr;
1757 misc_reg = MISCREG_CPSR;
1758 }
1759 break;
1760 case MISCREG_SP_EL0:
1761 tc->setIntReg(INTREG_SP0, newVal);
1762 break;
1763 case MISCREG_SP_EL1:
1764 tc->setIntReg(INTREG_SP1, newVal);
1765 break;
1766 case MISCREG_SP_EL2:
1767 tc->setIntReg(INTREG_SP2, newVal);
1768 break;
1769 case MISCREG_SPSEL:
1770 {
1771 CPSR cpsr = miscRegs[MISCREG_CPSR];
1772 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1773 newVal = cpsr;
1774 misc_reg = MISCREG_CPSR;
1775 }
1776 break;
1777 case MISCREG_CURRENTEL:
1778 {
1779 CPSR cpsr = miscRegs[MISCREG_CPSR];
1780 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1781 newVal = cpsr;
1782 misc_reg = MISCREG_CPSR;
1783 }
1784 break;
1785 case MISCREG_AT_S1E1R_Xt:
1786 case MISCREG_AT_S1E1W_Xt:
1787 case MISCREG_AT_S1E0R_Xt:
1788 case MISCREG_AT_S1E0W_Xt:
1789 case MISCREG_AT_S1E2R_Xt:
1790 case MISCREG_AT_S1E2W_Xt:
1791 case MISCREG_AT_S12E1R_Xt:
1792 case MISCREG_AT_S12E1W_Xt:
1793 case MISCREG_AT_S12E0R_Xt:
1794 case MISCREG_AT_S12E0W_Xt:
1795 case MISCREG_AT_S1E3R_Xt:
1796 case MISCREG_AT_S1E3W_Xt:
1797 {
1798 RequestPtr req = new Request;
1799 Request::Flags flags = 0;
1800 BaseTLB::Mode mode = BaseTLB::Read;
1801 TLB::ArmTranslationType tranType = TLB::NormalTran;
1802 Fault fault;
1803 switch(misc_reg) {
1804 case MISCREG_AT_S1E1R_Xt:
1805 flags = TLB::MustBeOne;
1806 tranType = TLB::S1E1Tran;
1807 mode = BaseTLB::Read;
1808 break;
1809 case MISCREG_AT_S1E1W_Xt:
1810 flags = TLB::MustBeOne;
1811 tranType = TLB::S1E1Tran;
1812 mode = BaseTLB::Write;
1813 break;
1814 case MISCREG_AT_S1E0R_Xt:
1815 flags = TLB::MustBeOne | TLB::UserMode;
1816 tranType = TLB::S1E0Tran;
1817 mode = BaseTLB::Read;
1818 break;
1819 case MISCREG_AT_S1E0W_Xt:
1820 flags = TLB::MustBeOne | TLB::UserMode;
1821 tranType = TLB::S1E0Tran;
1822 mode = BaseTLB::Write;
1823 break;
1824 case MISCREG_AT_S1E2R_Xt:
1825 flags = TLB::MustBeOne;
1826 tranType = TLB::S1E2Tran;
1827 mode = BaseTLB::Read;
1828 break;
1829 case MISCREG_AT_S1E2W_Xt:
1830 flags = TLB::MustBeOne;
1831 tranType = TLB::S1E2Tran;
1832 mode = BaseTLB::Write;
1833 break;
1834 case MISCREG_AT_S12E0R_Xt:
1835 flags = TLB::MustBeOne | TLB::UserMode;
1836 tranType = TLB::S12E0Tran;
1837 mode = BaseTLB::Read;
1838 break;
1839 case MISCREG_AT_S12E0W_Xt:
1840 flags = TLB::MustBeOne | TLB::UserMode;
1841 tranType = TLB::S12E0Tran;
1842 mode = BaseTLB::Write;
1843 break;
1844 case MISCREG_AT_S12E1R_Xt:
1845 flags = TLB::MustBeOne;
1846 tranType = TLB::S12E1Tran;
1847 mode = BaseTLB::Read;
1848 break;
1849 case MISCREG_AT_S12E1W_Xt:
1850 flags = TLB::MustBeOne;
1851 tranType = TLB::S12E1Tran;
1852 mode = BaseTLB::Write;
1853 break;
1854 case MISCREG_AT_S1E3R_Xt:
1855 flags = TLB::MustBeOne;
1856 tranType = TLB::S1E3Tran;
1857 mode = BaseTLB::Read;
1858 break;
1859 case MISCREG_AT_S1E3W_Xt:
1860 flags = TLB::MustBeOne;
1861 tranType = TLB::S1E3Tran;
1862 mode = BaseTLB::Write;
1863 break;
1864 }
1865 // If we're in timing mode then doing the translation in
1866 // functional mode then we're slightly distorting performance
1867 // results obtained from simulations. The translation should be
1868 // done in the same mode the core is running in. NOTE: This
1869 // can't be an atomic translation because that causes problems
1870 // with unexpected atomic snoop requests.
1871 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1872 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1873 tc->pcState().pc());
1874 req->setContext(tc->contextId());
1875 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1876 tranType);
1877
1878 MiscReg newVal;
1879 if (fault == NoFault) {
1880 Addr paddr = req->getPaddr();
1881 uint64_t attr = getDTBPtr(tc)->getAttr();
1882 uint64_t attr1 = attr >> 56;
1883 if (!attr1 || attr1 ==0x44) {
1884 attr |= 0x100;
1885 attr &= ~ uint64_t(0x80);
1886 }
1887 newVal = (paddr & mask(47, 12)) | attr;
1888 DPRINTF(MiscRegs,
1889 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1890 val, newVal);
1891 } else {
1892 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1893 armFault->update(tc);
1894 // Set fault bit and FSR
1895 FSR fsr = armFault->getFsr(tc);
1896
1897 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1898 if (cpsr.width) { // AArch32
1899 newVal = ((fsr >> 9) & 1) << 11;
1900 // rearrange fault status
1901 newVal |= ((fsr >> 0) & 0x3f) << 1;
1902 newVal |= 0x1; // F bit
1903 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1904 newVal |= armFault->isStage2() ? 0x200 : 0;
1905 } else { // AArch64
1906 newVal = 1; // F bit
1907 newVal |= fsr << 1; // FST
1908 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1909 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1910 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1911 newVal |= 1 << 11; // RES1
1912 }
1913 DPRINTF(MiscRegs,
1914 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1915 val, fsr, newVal);
1916 }
1917 delete req;
1918 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1919 return;
1920 }
1921 case MISCREG_SPSR_EL3:
1922 case MISCREG_SPSR_EL2:
1923 case MISCREG_SPSR_EL1:
1924 // Force bits 23:21 to 0
1925 newVal = val & ~(0x7 << 21);
1926 break;
1927 case MISCREG_L2CTLR:
1928 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1929 miscRegName[misc_reg], uint32_t(val));
1930 break;
1931
1932 // Generic Timer registers
1933 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1934 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1935 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1936 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1937 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1938 break;
1939 }
1940 }
1941 setMiscRegNoEffect(misc_reg, newVal);
1942}
1943
1944BaseISADevice &
1945ISA::getGenericTimer(ThreadContext *tc)
1946{
1947 // We only need to create an ISA interface the first time we try
1948 // to access the timer.
1949 if (timer)
1950 return *timer.get();
1951
1952 assert(system);
1953 GenericTimer *generic_timer(system->getGenericTimer());
1954 if (!generic_timer) {
1955 panic("Trying to get a generic timer from a system that hasn't "
1956 "been configured to use a generic timer.\n");
1957 }
1958
1959 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1960 return *timer.get();
1961}
1962
1963}
1964
1965ArmISA::ISA *
1966ArmISAParams::create()
1967{
1968 return new ArmISA::ISA(this);
1969}
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