1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58ISA::ISA(Params *p)
59 : SimObject(p),
60 system(NULL),
61 _decoderFlavour(p->decoderFlavour),
62 _vecRegRenameMode(p->vecRegRenameMode),
63 pmu(p->pmu)
64{
65 miscRegs[MISCREG_SCTLR_RST] = 0;
66
67 // Hook up a dummy device if we haven't been configured with a
68 // real PMU. By using a dummy device, we don't need to check that
69 // the PMU exist every time we try to access a PMU register.
70 if (!pmu)
71 pmu = &dummyDevice;
72
73 // Give all ISA devices a pointer to this ISA
74 pmu->setISA(this);
75
76 system = dynamic_cast<ArmSystem *>(p->system);
77
78 // Cache system-level properties
79 if (FullSystem && system) {
80 highestELIs64 = system->highestELIs64();
81 haveSecurity = system->haveSecurity();
82 haveLPAE = system->haveLPAE();
83 haveVirtualization = system->haveVirtualization();
84 haveLargeAsid64 = system->haveLargeAsid64();
85 physAddrRange64 = system->physAddrRange64();
86 } else {
87 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
88 haveSecurity = haveLPAE = haveVirtualization = false;
89 haveLargeAsid64 = false;
90 physAddrRange64 = 32; // dummy value
91 }
92
93 initializeMiscRegMetadata();
94 preUnflattenMiscReg();
95
96 clear();
97}
98
99std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
100
101const ArmISAParams *
102ISA::params() const
103{
104 return dynamic_cast<const Params *>(_params);
105}
106
107void
108ISA::clear()
109{
110 const Params *p(params());
111
112 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
113 memset(miscRegs, 0, sizeof(miscRegs));
114
115 // Initialize configurable default values
116 miscRegs[MISCREG_MIDR] = p->midr;
117 miscRegs[MISCREG_MIDR_EL1] = p->midr;
118 miscRegs[MISCREG_VPIDR] = p->midr;
119
120 if (FullSystem && system->highestELIs64()) {
121 // Initialize AArch64 state
122 clear64(p);
123 return;
124 }
125
126 // Initialize AArch32 state...
127
128 CPSR cpsr = 0;
129 cpsr.mode = MODE_USER;
130 miscRegs[MISCREG_CPSR] = cpsr;
131 updateRegMap(cpsr);
132
133 SCTLR sctlr = 0;
134 sctlr.te = (bool) sctlr_rst.te;
135 sctlr.nmfi = (bool) sctlr_rst.nmfi;
136 sctlr.v = (bool) sctlr_rst.v;
137 sctlr.u = 1;
138 sctlr.xp = 1;
139 sctlr.rao2 = 1;
140 sctlr.rao3 = 1;
141 sctlr.rao4 = 0xf; // SCTLR[6:3]
142 sctlr.uci = 1;
143 sctlr.dze = 1;
144 miscRegs[MISCREG_SCTLR_NS] = sctlr;
145 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
146 miscRegs[MISCREG_HCPTR] = 0;
147
148 // Start with an event in the mailbox
149 miscRegs[MISCREG_SEV_MAILBOX] = 1;
150
151 // Separate Instruction and Data TLBs
152 miscRegs[MISCREG_TLBTR] = 1;
153
154 MVFR0 mvfr0 = 0;
155 mvfr0.advSimdRegisters = 2;
156 mvfr0.singlePrecision = 2;
157 mvfr0.doublePrecision = 2;
158 mvfr0.vfpExceptionTrapping = 0;
159 mvfr0.divide = 1;
160 mvfr0.squareRoot = 1;
161 mvfr0.shortVectors = 1;
162 mvfr0.roundingModes = 1;
163 miscRegs[MISCREG_MVFR0] = mvfr0;
164
165 MVFR1 mvfr1 = 0;
166 mvfr1.flushToZero = 1;
167 mvfr1.defaultNaN = 1;
168 mvfr1.advSimdLoadStore = 1;
169 mvfr1.advSimdInteger = 1;
170 mvfr1.advSimdSinglePrecision = 1;
171 mvfr1.advSimdHalfPrecision = 1;
172 mvfr1.vfpHalfPrecision = 1;
173 miscRegs[MISCREG_MVFR1] = mvfr1;
174
175 // Reset values of PRRR and NMRR are implementation dependent
176
177 // @todo: PRRR and NMRR in secure state?
178 miscRegs[MISCREG_PRRR_NS] =
179 (1 << 19) | // 19
180 (0 << 18) | // 18
181 (0 << 17) | // 17
182 (1 << 16) | // 16
183 (2 << 14) | // 15:14
184 (0 << 12) | // 13:12
185 (2 << 10) | // 11:10
186 (2 << 8) | // 9:8
187 (2 << 6) | // 7:6
188 (2 << 4) | // 5:4
189 (1 << 2) | // 3:2
190 0; // 1:0
191 miscRegs[MISCREG_NMRR_NS] =
192 (1 << 30) | // 31:30
193 (0 << 26) | // 27:26
194 (0 << 24) | // 25:24
195 (3 << 22) | // 23:22
196 (2 << 20) | // 21:20
197 (0 << 18) | // 19:18
198 (0 << 16) | // 17:16
199 (1 << 14) | // 15:14
200 (0 << 12) | // 13:12
201 (2 << 10) | // 11:10
202 (0 << 8) | // 9:8
203 (3 << 6) | // 7:6
204 (2 << 4) | // 5:4
205 (0 << 2) | // 3:2
206 0; // 1:0
207
208 miscRegs[MISCREG_CPACR] = 0;
209
210 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
211 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
212 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
213 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
214
215 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
216 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
217 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
218 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
219 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
220 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
221
222 miscRegs[MISCREG_FPSID] = p->fpsid;
223
224 if (haveLPAE) {
225 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
226 ttbcr.eae = 0;
227 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
228 // Enforce consistency with system-level settings
229 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
230 }
231
232 if (haveSecurity) {
233 miscRegs[MISCREG_SCTLR_S] = sctlr;
234 miscRegs[MISCREG_SCR] = 0;
235 miscRegs[MISCREG_VBAR_S] = 0;
236 } else {
237 // we're always non-secure
238 miscRegs[MISCREG_SCR] = 1;
239 }
240
241 //XXX We need to initialize the rest of the state.
242}
243
244void
245ISA::clear64(const ArmISAParams *p)
246{
247 CPSR cpsr = 0;
248 Addr rvbar = system->resetAddr64();
249 switch (system->highestEL()) {
250 // Set initial EL to highest implemented EL using associated stack
251 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
252 // value
253 case EL3:
254 cpsr.mode = MODE_EL3H;
255 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
256 break;
257 case EL2:
258 cpsr.mode = MODE_EL2H;
259 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
260 break;
261 case EL1:
262 cpsr.mode = MODE_EL1H;
263 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
264 break;
265 default:
266 panic("Invalid highest implemented exception level");
267 break;
268 }
269
270 // Initialize rest of CPSR
271 cpsr.daif = 0xf; // Mask all interrupts
272 cpsr.ss = 0;
273 cpsr.il = 0;
274 miscRegs[MISCREG_CPSR] = cpsr;
275 updateRegMap(cpsr);
276
277 // Initialize other control registers
278 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
279 if (haveSecurity) {
280 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
281 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
282 } else if (haveVirtualization) {
283 // also MISCREG_SCTLR_EL2 (by mapping)
284 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
285 } else {
286 // also MISCREG_SCTLR_EL1 (by mapping)
287 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
288 // Always non-secure
289 miscRegs[MISCREG_SCR_EL3] = 1;
290 }
291
292 // Initialize configurable id registers
293 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
294 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
295 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
296 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
297 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
298
299 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
300 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
301 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
302 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
303 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
304
305 miscRegs[MISCREG_ID_DFR0_EL1] =
306 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
307
308 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
309
310 // Enforce consistency with system-level settings...
311
312 // EL3
313 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
314 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
315 haveSecurity ? 0x2 : 0x0);
316 // EL2
317 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
318 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
319 haveVirtualization ? 0x2 : 0x0);
320 // Large ASID support
321 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
322 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
323 haveLargeAsid64 ? 0x2 : 0x0);
324 // Physical address size
325 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
326 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
327 encodePhysAddrRange64(physAddrRange64));
328}
329
330MiscReg
331ISA::readMiscRegNoEffect(int misc_reg) const
332{
333 assert(misc_reg < NumMiscRegs);
334
335 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
336 const auto &map = getMiscIndices(misc_reg);
337 int lower = map.first, upper = map.second;
338 // NB!: apply architectural masks according to desired register,
339 // despite possibly getting value from different (mapped) register.
340 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
341 |(miscRegs[upper] << 32));
342 if (val & reg.res0()) {
343 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
344 miscRegName[misc_reg], val & reg.res0());
345 }
346 if ((val & reg.res1()) != reg.res1()) {
347 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
348 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
349 }
350 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
351}
352
353
354MiscReg
355ISA::readMiscReg(int misc_reg, ThreadContext *tc)
356{
357 CPSR cpsr = 0;
358 PCState pc = 0;
359 SCR scr = 0;
360
361 if (misc_reg == MISCREG_CPSR) {
362 cpsr = miscRegs[misc_reg];
363 pc = tc->pcState();
364 cpsr.j = pc.jazelle() ? 1 : 0;
365 cpsr.t = pc.thumb() ? 1 : 0;
366 return cpsr;
367 }
368
369#ifndef NDEBUG
370 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
371 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
372 warn("Unimplemented system register %s read.\n",
373 miscRegName[misc_reg]);
374 else
375 panic("Unimplemented system register %s read.\n",
376 miscRegName[misc_reg]);
377 }
378#endif
379
380 switch (unflattenMiscReg(misc_reg)) {
381 case MISCREG_HCR:
382 {
383 if (!haveVirtualization)
384 return 0;
385 else
386 return readMiscRegNoEffect(MISCREG_HCR);
387 }
388 case MISCREG_CPACR:
389 {
390 const uint32_t ones = (uint32_t)(-1);
391 CPACR cpacrMask = 0;
392 // Only cp10, cp11, and ase are implemented, nothing else should
393 // be readable? (straight copy from the write code)
394 cpacrMask.cp10 = ones;
395 cpacrMask.cp11 = ones;
396 cpacrMask.asedis = ones;
397
398 // Security Extensions may limit the readability of CPACR
399 if (haveSecurity) {
400 scr = readMiscRegNoEffect(MISCREG_SCR);
401 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
402 if (scr.ns && (cpsr.mode != MODE_MON)) {
403 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
404 // NB: Skipping the full loop, here
405 if (!nsacr.cp10) cpacrMask.cp10 = 0;
406 if (!nsacr.cp11) cpacrMask.cp11 = 0;
407 }
408 }
409 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
410 val &= cpacrMask;
411 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
412 miscRegName[misc_reg], val);
413 return val;
414 }
415 case MISCREG_MPIDR:
416 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
417 scr = readMiscRegNoEffect(MISCREG_SCR);
418 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
419 return getMPIDR(system, tc);
420 } else {
421 return readMiscReg(MISCREG_VMPIDR, tc);
422 }
423 break;
424 case MISCREG_MPIDR_EL1:
425 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
426 return getMPIDR(system, tc) & 0xffffffff;
427 case MISCREG_VMPIDR:
428 // top bit defined as RES1
429 return readMiscRegNoEffect(misc_reg) | 0x80000000;
430 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
431 case MISCREG_REVIDR: // not implemented, so alias MIDR
432 case MISCREG_MIDR:
433 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
434 scr = readMiscRegNoEffect(MISCREG_SCR);
435 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
436 return readMiscRegNoEffect(misc_reg);
437 } else {
438 return readMiscRegNoEffect(MISCREG_VPIDR);
439 }
440 break;
441 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
442 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_AIDR: // AUX ID set to 0
445 case MISCREG_TCMTR: // No TCM's
446 return 0;
447
448 case MISCREG_CLIDR:
449 warn_once("The clidr register always reports 0 caches.\n");
450 warn_once("clidr LoUIS field of 0b001 to match current "
451 "ARM implementations.\n");
452 return 0x00200000;
453 case MISCREG_CCSIDR:
454 warn_once("The ccsidr register isn't implemented and "
455 "always reads as 0.\n");
456 break;
457 case MISCREG_CTR: // AArch32, ARMv7, top bit set
458 case MISCREG_CTR_EL0: // AArch64
459 {
460 //all caches have the same line size in gem5
461 //4 byte words in ARM
462 unsigned lineSizeWords =
463 tc->getSystemPtr()->cacheLineSize() / 4;
464 unsigned log2LineSizeWords = 0;
465
466 while (lineSizeWords >>= 1) {
467 ++log2LineSizeWords;
468 }
469
470 CTR ctr = 0;
471 //log2 of minimun i-cache line size (words)
472 ctr.iCacheLineSize = log2LineSizeWords;
473 //b11 - gem5 uses pipt
474 ctr.l1IndexPolicy = 0x3;
475 //log2 of minimum d-cache line size (words)
476 ctr.dCacheLineSize = log2LineSizeWords;
477 //log2 of max reservation size (words)
478 ctr.erg = log2LineSizeWords;
479 //log2 of max writeback size (words)
480 ctr.cwg = log2LineSizeWords;
481 //b100 - gem5 format is ARMv7
482 ctr.format = 0x4;
483
484 return ctr;
485 }
486 case MISCREG_ACTLR:
487 warn("Not doing anything for miscreg ACTLR\n");
488 break;
489
490 case MISCREG_PMXEVTYPER_PMCCFILTR:
491 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
492 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
493 case MISCREG_PMCR ... MISCREG_PMOVSSET:
494 return pmu->readMiscReg(misc_reg);
495
496 case MISCREG_CPSR_Q:
497 panic("shouldn't be reading this register seperately\n");
498 case MISCREG_FPSCR_QC:
499 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
500 case MISCREG_FPSCR_EXC:
501 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
502 case MISCREG_FPSR:
503 {
504 const uint32_t ones = (uint32_t)(-1);
505 FPSCR fpscrMask = 0;
506 fpscrMask.ioc = ones;
507 fpscrMask.dzc = ones;
508 fpscrMask.ofc = ones;
509 fpscrMask.ufc = ones;
510 fpscrMask.ixc = ones;
511 fpscrMask.idc = ones;
512 fpscrMask.qc = ones;
513 fpscrMask.v = ones;
514 fpscrMask.c = ones;
515 fpscrMask.z = ones;
516 fpscrMask.n = ones;
517 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
518 }
519 case MISCREG_FPCR:
520 {
521 const uint32_t ones = (uint32_t)(-1);
522 FPSCR fpscrMask = 0;
523 fpscrMask.ioe = ones;
524 fpscrMask.dze = ones;
525 fpscrMask.ofe = ones;
526 fpscrMask.ufe = ones;
527 fpscrMask.ixe = ones;
528 fpscrMask.ide = ones;
529 fpscrMask.len = ones;
530 fpscrMask.stride = ones;
531 fpscrMask.rMode = ones;
532 fpscrMask.fz = ones;
533 fpscrMask.dn = ones;
534 fpscrMask.ahp = ones;
535 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
536 }
537 case MISCREG_NZCV:
538 {
539 CPSR cpsr = 0;
540 cpsr.nz = tc->readCCReg(CCREG_NZ);
541 cpsr.c = tc->readCCReg(CCREG_C);
542 cpsr.v = tc->readCCReg(CCREG_V);
543 return cpsr;
544 }
545 case MISCREG_DAIF:
546 {
547 CPSR cpsr = 0;
548 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
549 return cpsr;
550 }
551 case MISCREG_SP_EL0:
552 {
553 return tc->readIntReg(INTREG_SP0);
554 }
555 case MISCREG_SP_EL1:
556 {
557 return tc->readIntReg(INTREG_SP1);
558 }
559 case MISCREG_SP_EL2:
560 {
561 return tc->readIntReg(INTREG_SP2);
562 }
563 case MISCREG_SPSEL:
564 {
565 return miscRegs[MISCREG_CPSR] & 0x1;
566 }
567 case MISCREG_CURRENTEL:
568 {
569 return miscRegs[MISCREG_CPSR] & 0xc;
570 }
571 case MISCREG_L2CTLR:
572 {
573 // mostly unimplemented, just set NumCPUs field from sim and return
574 L2CTLR l2ctlr = 0;
575 // b00:1CPU to b11:4CPUs
576 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
577 return l2ctlr;
578 }
579 case MISCREG_DBGDIDR:
580 /* For now just implement the version number.
581 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
582 */
583 return 0x5 << 16;
584 case MISCREG_DBGDSCRint:
585 return 0;
586 case MISCREG_ISR:
587 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
588 readMiscRegNoEffect(MISCREG_HCR),
589 readMiscRegNoEffect(MISCREG_CPSR),
590 readMiscRegNoEffect(MISCREG_SCR));
591 case MISCREG_ISR_EL1:
592 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
593 readMiscRegNoEffect(MISCREG_HCR_EL2),
594 readMiscRegNoEffect(MISCREG_CPSR),
595 readMiscRegNoEffect(MISCREG_SCR_EL3));
596 case MISCREG_DCZID_EL0:
597 return 0x04; // DC ZVA clear 64-byte chunks
598 case MISCREG_HCPTR:
599 {
600 MiscReg val = readMiscRegNoEffect(misc_reg);
601 // The trap bit associated with CP14 is defined as RAZ
602 val &= ~(1 << 14);
603 // If a CP bit in NSACR is 0 then the corresponding bit in
604 // HCPTR is RAO/WI
605 bool secure_lookup = haveSecurity &&
606 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
607 readMiscRegNoEffect(MISCREG_CPSR));
608 if (!secure_lookup) {
609 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
610 val |= (mask ^ 0x7FFF) & 0xBFFF;
611 }
612 // Set the bits for unimplemented coprocessors to RAO/WI
613 val |= 0x33FF;
614 return (val);
615 }
616 case MISCREG_HDFAR: // alias for secure DFAR
617 return readMiscRegNoEffect(MISCREG_DFAR_S);
618 case MISCREG_HIFAR: // alias for secure IFAR
619 return readMiscRegNoEffect(MISCREG_IFAR_S);
620 case MISCREG_HVBAR: // bottom bits reserved
621 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
622 case MISCREG_SCTLR:
623 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
624 case MISCREG_SCTLR_EL1:
625 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
626 case MISCREG_SCTLR_EL2:
627 case MISCREG_SCTLR_EL3:
628 case MISCREG_HSCTLR:
629 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
630
631 case MISCREG_ID_PFR0:
632 // !ThumbEE | !Jazelle | Thumb | ARM
633 return 0x00000031;
634 case MISCREG_ID_PFR1:
635 { // Timer | Virti | !M Profile | TrustZone | ARMv4
636 bool haveTimer = (system->getGenericTimer() != NULL);
637 return 0x00000001
638 | (haveSecurity ? 0x00000010 : 0x0)
639 | (haveVirtualization ? 0x00001000 : 0x0)
640 | (haveTimer ? 0x00010000 : 0x0);
641 }
642 case MISCREG_ID_AA64PFR0_EL1:
643 return 0x0000000000000002 // AArch{64,32} supported at EL0
644 | 0x0000000000000020 // EL1
645 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
646 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
647 case MISCREG_ID_AA64PFR1_EL1:
648 return 0; // bits [63:0] RES0 (reserved for future use)
649
650 // Generic Timer registers
651 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
652 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
653 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
654 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
655 return getGenericTimer(tc).readMiscReg(misc_reg);
656
657 default:
658 break;
659
660 }
661 return readMiscRegNoEffect(misc_reg);
662}
663
664void
665ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
666{
667 assert(misc_reg < NumMiscRegs);
668
669 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
670 const auto &map = getMiscIndices(misc_reg);
671 int lower = map.first, upper = map.second;
672
673 auto v = (val & ~reg.wi()) | reg.rao();
674 if (upper > 0) {
675 miscRegs[lower] = bits(v, 31, 0);
676 miscRegs[upper] = bits(v, 63, 32);
677 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
678 misc_reg, lower, upper, v);
679 } else {
680 miscRegs[lower] = v;
681 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
682 misc_reg, lower, v);
683 }
684}
685
686namespace {
687
688template<typename T>
689TLB *
690getITBPtr(T *tc)
691{
692 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
693 assert(tlb);
694 return tlb;
695}
696
697template<typename T>
698TLB *
699getDTBPtr(T *tc)
700{
701 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
702 assert(tlb);
703 return tlb;
704}
705
706} // anonymous namespace
707
708void
709ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
710{
711
712 MiscReg newVal = val;
713 int x;
714 bool secure_lookup;
715 bool hyp;
716 System *sys;
717 ThreadContext *oc;
718 uint8_t target_el;
719 uint16_t asid;
720 SCR scr;
721
722 if (misc_reg == MISCREG_CPSR) {
723 updateRegMap(val);
724
725
726 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
727 int old_mode = old_cpsr.mode;
728 CPSR cpsr = val;
729 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
730 getITBPtr(tc)->invalidateMiscReg();
731 getDTBPtr(tc)->invalidateMiscReg();
732 }
733
734 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
735 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
736 PCState pc = tc->pcState();
737 pc.nextThumb(cpsr.t);
738 pc.nextJazelle(cpsr.j);
739
740 // Follow slightly different semantics if a CheckerCPU object
741 // is connected
742 CheckerCPU *checker = tc->getCheckerCpuPtr();
743 if (checker) {
744 tc->pcStateNoRecord(pc);
745 } else {
746 tc->pcState(pc);
747 }
748 } else {
749#ifndef NDEBUG
750 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
751 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
752 warn("Unimplemented system register %s write with %#x.\n",
753 miscRegName[misc_reg], val);
754 else
755 panic("Unimplemented system register %s write with %#x.\n",
756 miscRegName[misc_reg], val);
757 }
758#endif
759 switch (unflattenMiscReg(misc_reg)) {
760 case MISCREG_CPACR:
761 {
762
763 const uint32_t ones = (uint32_t)(-1);
764 CPACR cpacrMask = 0;
765 // Only cp10, cp11, and ase are implemented, nothing else should
766 // be writable
767 cpacrMask.cp10 = ones;
768 cpacrMask.cp11 = ones;
769 cpacrMask.asedis = ones;
770
771 // Security Extensions may limit the writability of CPACR
772 if (haveSecurity) {
773 scr = readMiscRegNoEffect(MISCREG_SCR);
774 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
775 if (scr.ns && (cpsr.mode != MODE_MON)) {
776 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
777 // NB: Skipping the full loop, here
778 if (!nsacr.cp10) cpacrMask.cp10 = 0;
779 if (!nsacr.cp11) cpacrMask.cp11 = 0;
780 }
781 }
782
783 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
784 newVal &= cpacrMask;
785 newVal |= old_val & ~cpacrMask;
786 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
787 miscRegName[misc_reg], newVal);
788 }
789 break;
790 case MISCREG_CPACR_EL1:
791 {
792 const uint32_t ones = (uint32_t)(-1);
793 CPACR cpacrMask = 0;
794 cpacrMask.tta = ones;
795 cpacrMask.fpen = ones;
796 newVal &= cpacrMask;
797 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
798 miscRegName[misc_reg], newVal);
799 }
800 break;
801 case MISCREG_CPTR_EL2:
802 {
803 const uint32_t ones = (uint32_t)(-1);
804 CPTR cptrMask = 0;
805 cptrMask.tcpac = ones;
806 cptrMask.tta = ones;
807 cptrMask.tfp = ones;
808 newVal &= cptrMask;
809 cptrMask = 0;
810 cptrMask.res1_13_12_el2 = ones;
811 cptrMask.res1_9_0_el2 = ones;
812 newVal |= cptrMask;
813 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
814 miscRegName[misc_reg], newVal);
815 }
816 break;
817 case MISCREG_CPTR_EL3:
818 {
819 const uint32_t ones = (uint32_t)(-1);
820 CPTR cptrMask = 0;
821 cptrMask.tcpac = ones;
822 cptrMask.tta = ones;
823 cptrMask.tfp = ones;
824 newVal &= cptrMask;
825 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
826 miscRegName[misc_reg], newVal);
827 }
828 break;
829 case MISCREG_CSSELR:
830 warn_once("The csselr register isn't implemented.\n");
831 return;
832
833 case MISCREG_DC_ZVA_Xt:
834 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
835 return;
836
837 case MISCREG_FPSCR:
838 {
839 const uint32_t ones = (uint32_t)(-1);
840 FPSCR fpscrMask = 0;
841 fpscrMask.ioc = ones;
842 fpscrMask.dzc = ones;
843 fpscrMask.ofc = ones;
844 fpscrMask.ufc = ones;
845 fpscrMask.ixc = ones;
846 fpscrMask.idc = ones;
847 fpscrMask.ioe = ones;
848 fpscrMask.dze = ones;
849 fpscrMask.ofe = ones;
850 fpscrMask.ufe = ones;
851 fpscrMask.ixe = ones;
852 fpscrMask.ide = ones;
853 fpscrMask.len = ones;
854 fpscrMask.stride = ones;
855 fpscrMask.rMode = ones;
856 fpscrMask.fz = ones;
857 fpscrMask.dn = ones;
858 fpscrMask.ahp = ones;
859 fpscrMask.qc = ones;
860 fpscrMask.v = ones;
861 fpscrMask.c = ones;
862 fpscrMask.z = ones;
863 fpscrMask.n = ones;
864 newVal = (newVal & (uint32_t)fpscrMask) |
865 (readMiscRegNoEffect(MISCREG_FPSCR) &
866 ~(uint32_t)fpscrMask);
867 tc->getDecoderPtr()->setContext(newVal);
868 }
869 break;
870 case MISCREG_FPSR:
871 {
872 const uint32_t ones = (uint32_t)(-1);
873 FPSCR fpscrMask = 0;
874 fpscrMask.ioc = ones;
875 fpscrMask.dzc = ones;
876 fpscrMask.ofc = ones;
877 fpscrMask.ufc = ones;
878 fpscrMask.ixc = ones;
879 fpscrMask.idc = ones;
880 fpscrMask.qc = ones;
881 fpscrMask.v = ones;
882 fpscrMask.c = ones;
883 fpscrMask.z = ones;
884 fpscrMask.n = ones;
885 newVal = (newVal & (uint32_t)fpscrMask) |
886 (readMiscRegNoEffect(MISCREG_FPSCR) &
887 ~(uint32_t)fpscrMask);
888 misc_reg = MISCREG_FPSCR;
889 }
890 break;
891 case MISCREG_FPCR:
892 {
893 const uint32_t ones = (uint32_t)(-1);
894 FPSCR fpscrMask = 0;
895 fpscrMask.ioe = ones;
896 fpscrMask.dze = ones;
897 fpscrMask.ofe = ones;
898 fpscrMask.ufe = ones;
899 fpscrMask.ixe = ones;
900 fpscrMask.ide = ones;
901 fpscrMask.len = ones;
902 fpscrMask.stride = ones;
903 fpscrMask.rMode = ones;
904 fpscrMask.fz = ones;
905 fpscrMask.dn = ones;
906 fpscrMask.ahp = ones;
907 newVal = (newVal & (uint32_t)fpscrMask) |
908 (readMiscRegNoEffect(MISCREG_FPSCR) &
909 ~(uint32_t)fpscrMask);
910 misc_reg = MISCREG_FPSCR;
911 }
912 break;
913 case MISCREG_CPSR_Q:
914 {
915 assert(!(newVal & ~CpsrMaskQ));
916 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
917 misc_reg = MISCREG_CPSR;
918 }
919 break;
920 case MISCREG_FPSCR_QC:
921 {
922 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
923 (newVal & FpscrQcMask);
924 misc_reg = MISCREG_FPSCR;
925 }
926 break;
927 case MISCREG_FPSCR_EXC:
928 {
929 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
930 (newVal & FpscrExcMask);
931 misc_reg = MISCREG_FPSCR;
932 }
933 break;
934 case MISCREG_FPEXC:
935 {
936 // vfpv3 architecture, section B.6.1 of DDI04068
937 // bit 29 - valid only if fpexc[31] is 0
938 const uint32_t fpexcMask = 0x60000000;
939 newVal = (newVal & fpexcMask) |
940 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
941 }
942 break;
943 case MISCREG_HCR:
944 {
945 if (!haveVirtualization)
946 return;
947 }
948 break;
949 case MISCREG_IFSR:
950 {
951 // ARM ARM (ARM DDI 0406C.b) B4.1.96
952 const uint32_t ifsrMask =
953 mask(31, 13) | mask(11, 11) | mask(8, 6);
954 newVal = newVal & ~ifsrMask;
955 }
956 break;
957 case MISCREG_DFSR:
958 {
959 // ARM ARM (ARM DDI 0406C.b) B4.1.52
960 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
961 newVal = newVal & ~dfsrMask;
962 }
963 break;
964 case MISCREG_AMAIR0:
965 case MISCREG_AMAIR1:
966 {
967 // ARM ARM (ARM DDI 0406C.b) B4.1.5
968 // Valid only with LPAE
969 if (!haveLPAE)
970 return;
971 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
972 }
973 break;
974 case MISCREG_SCR:
975 getITBPtr(tc)->invalidateMiscReg();
976 getDTBPtr(tc)->invalidateMiscReg();
977 break;
978 case MISCREG_SCTLR:
979 {
980 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
981 scr = readMiscRegNoEffect(MISCREG_SCR);
982 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
983 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
984 SCTLR sctlr = miscRegs[sctlr_idx];
985 SCTLR new_sctlr = newVal;
986 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
987 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
988 getITBPtr(tc)->invalidateMiscReg();
989 getDTBPtr(tc)->invalidateMiscReg();
990 }
991 case MISCREG_MIDR:
992 case MISCREG_ID_PFR0:
993 case MISCREG_ID_PFR1:
994 case MISCREG_ID_DFR0:
995 case MISCREG_ID_MMFR0:
996 case MISCREG_ID_MMFR1:
997 case MISCREG_ID_MMFR2:
998 case MISCREG_ID_MMFR3:
999 case MISCREG_ID_ISAR0:
1000 case MISCREG_ID_ISAR1:
1001 case MISCREG_ID_ISAR2:
1002 case MISCREG_ID_ISAR3:
1003 case MISCREG_ID_ISAR4:
1004 case MISCREG_ID_ISAR5:
1005
1006 case MISCREG_MPIDR:
1007 case MISCREG_FPSID:
1008 case MISCREG_TLBTR:
1009 case MISCREG_MVFR0:
1010 case MISCREG_MVFR1:
1011
1012 case MISCREG_ID_AA64AFR0_EL1:
1013 case MISCREG_ID_AA64AFR1_EL1:
1014 case MISCREG_ID_AA64DFR0_EL1:
1015 case MISCREG_ID_AA64DFR1_EL1:
1016 case MISCREG_ID_AA64ISAR0_EL1:
1017 case MISCREG_ID_AA64ISAR1_EL1:
1018 case MISCREG_ID_AA64MMFR0_EL1:
1019 case MISCREG_ID_AA64MMFR1_EL1:
1020 case MISCREG_ID_AA64PFR0_EL1:
1021 case MISCREG_ID_AA64PFR1_EL1:
1022 // ID registers are constants.
1023 return;
1024
1025 // TLBI all entries, EL0&1 inner sharable (ignored)
1026 case MISCREG_TLBIALLIS:
1027 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1028 assert32(tc);
1029 target_el = 1; // el 0 and 1 are handled together
1030 scr = readMiscReg(MISCREG_SCR, tc);
1031 secure_lookup = haveSecurity && !scr.ns;
1032 sys = tc->getSystemPtr();
1033 for (x = 0; x < sys->numContexts(); x++) {
1034 oc = sys->getThreadContext(x);
1035 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1036 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1037
1038 // If CheckerCPU is connected, need to notify it of a flush
1039 CheckerCPU *checker = oc->getCheckerCpuPtr();
1040 if (checker) {
1041 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1042 target_el);
1043 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1044 target_el);
1045 }
1046 }
1047 return;
1048 // TLBI all entries, EL0&1, instruction side
1049 case MISCREG_ITLBIALL:
1050 assert32(tc);
1051 target_el = 1; // el 0 and 1 are handled together
1052 scr = readMiscReg(MISCREG_SCR, tc);
1053 secure_lookup = haveSecurity && !scr.ns;
1054 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1055 return;
1056 // TLBI all entries, EL0&1, data side
1057 case MISCREG_DTLBIALL:
1058 assert32(tc);
1059 target_el = 1; // el 0 and 1 are handled together
1060 scr = readMiscReg(MISCREG_SCR, tc);
1061 secure_lookup = haveSecurity && !scr.ns;
1062 getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1063 return;
1064 // TLBI based on VA, EL0&1 inner sharable (ignored)
1065 case MISCREG_TLBIMVAL:
1066 case MISCREG_TLBIMVALIS:
1067 // mcr tlbimval(is) is invalidating all matching entries
1068 // regardless of the level of lookup, since in gem5 we cache
1069 // in the tlb the last level of lookup only.
1070 case MISCREG_TLBIMVA:
1071 case MISCREG_TLBIMVAIS:
1072 assert32(tc);
1073 target_el = 1; // el 0 and 1 are handled together
1074 scr = readMiscReg(MISCREG_SCR, tc);
1075 secure_lookup = haveSecurity && !scr.ns;
1076 sys = tc->getSystemPtr();
1077 for (x = 0; x < sys->numContexts(); x++) {
1078 oc = sys->getThreadContext(x);
1079 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1080 bits(newVal, 7,0),
1081 secure_lookup, target_el);
1082 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1083 bits(newVal, 7,0),
1084 secure_lookup, target_el);
1085
1086 CheckerCPU *checker = oc->getCheckerCpuPtr();
1087 if (checker) {
1088 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1089 bits(newVal, 7,0), secure_lookup, target_el);
1090 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1091 bits(newVal, 7,0), secure_lookup, target_el);
1092 }
1093 }
1094 return;
1095 // TLBI by ASID, EL0&1, inner sharable
1096 case MISCREG_TLBIASIDIS:
1097 case MISCREG_TLBIASID:
1098 assert32(tc);
1099 target_el = 1; // el 0 and 1 are handled together
1100 scr = readMiscReg(MISCREG_SCR, tc);
1101 secure_lookup = haveSecurity && !scr.ns;
1102 sys = tc->getSystemPtr();
1103 for (x = 0; x < sys->numContexts(); x++) {
1104 oc = sys->getThreadContext(x);
1105 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1106 secure_lookup, target_el);
1107 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1108 secure_lookup, target_el);
1109 CheckerCPU *checker = oc->getCheckerCpuPtr();
1110 if (checker) {
1111 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1112 secure_lookup, target_el);
1113 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1114 secure_lookup, target_el);
1115 }
1116 }
1117 return;
1118 // TLBI by address, EL0&1, inner sharable (ignored)
1119 case MISCREG_TLBIMVAAL:
1120 case MISCREG_TLBIMVAALIS:
1121 // mcr tlbimvaal(is) is invalidating all matching entries
1122 // regardless of the level of lookup, since in gem5 we cache
1123 // in the tlb the last level of lookup only.
1124 case MISCREG_TLBIMVAA:
1125 case MISCREG_TLBIMVAAIS:
1126 assert32(tc);
1127 target_el = 1; // el 0 and 1 are handled together
1128 scr = readMiscReg(MISCREG_SCR, tc);
1129 secure_lookup = haveSecurity && !scr.ns;
1130 hyp = 0;
1131 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1132 return;
1133 // TLBI by address, EL2, hypervisor mode
1134 case MISCREG_TLBIMVALH:
1135 case MISCREG_TLBIMVALHIS:
1136 // mcr tlbimvalh(is) is invalidating all matching entries
1137 // regardless of the level of lookup, since in gem5 we cache
1138 // in the tlb the last level of lookup only.
1139 case MISCREG_TLBIMVAH:
1140 case MISCREG_TLBIMVAHIS:
1141 assert32(tc);
1142 target_el = 1; // aarch32, use hyp bit
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144 secure_lookup = haveSecurity && !scr.ns;
1145 hyp = 1;
1146 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1147 return;
| 1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58ISA::ISA(Params *p)
59 : SimObject(p),
60 system(NULL),
61 _decoderFlavour(p->decoderFlavour),
62 _vecRegRenameMode(p->vecRegRenameMode),
63 pmu(p->pmu)
64{
65 miscRegs[MISCREG_SCTLR_RST] = 0;
66
67 // Hook up a dummy device if we haven't been configured with a
68 // real PMU. By using a dummy device, we don't need to check that
69 // the PMU exist every time we try to access a PMU register.
70 if (!pmu)
71 pmu = &dummyDevice;
72
73 // Give all ISA devices a pointer to this ISA
74 pmu->setISA(this);
75
76 system = dynamic_cast<ArmSystem *>(p->system);
77
78 // Cache system-level properties
79 if (FullSystem && system) {
80 highestELIs64 = system->highestELIs64();
81 haveSecurity = system->haveSecurity();
82 haveLPAE = system->haveLPAE();
83 haveVirtualization = system->haveVirtualization();
84 haveLargeAsid64 = system->haveLargeAsid64();
85 physAddrRange64 = system->physAddrRange64();
86 } else {
87 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
88 haveSecurity = haveLPAE = haveVirtualization = false;
89 haveLargeAsid64 = false;
90 physAddrRange64 = 32; // dummy value
91 }
92
93 initializeMiscRegMetadata();
94 preUnflattenMiscReg();
95
96 clear();
97}
98
99std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
100
101const ArmISAParams *
102ISA::params() const
103{
104 return dynamic_cast<const Params *>(_params);
105}
106
107void
108ISA::clear()
109{
110 const Params *p(params());
111
112 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
113 memset(miscRegs, 0, sizeof(miscRegs));
114
115 // Initialize configurable default values
116 miscRegs[MISCREG_MIDR] = p->midr;
117 miscRegs[MISCREG_MIDR_EL1] = p->midr;
118 miscRegs[MISCREG_VPIDR] = p->midr;
119
120 if (FullSystem && system->highestELIs64()) {
121 // Initialize AArch64 state
122 clear64(p);
123 return;
124 }
125
126 // Initialize AArch32 state...
127
128 CPSR cpsr = 0;
129 cpsr.mode = MODE_USER;
130 miscRegs[MISCREG_CPSR] = cpsr;
131 updateRegMap(cpsr);
132
133 SCTLR sctlr = 0;
134 sctlr.te = (bool) sctlr_rst.te;
135 sctlr.nmfi = (bool) sctlr_rst.nmfi;
136 sctlr.v = (bool) sctlr_rst.v;
137 sctlr.u = 1;
138 sctlr.xp = 1;
139 sctlr.rao2 = 1;
140 sctlr.rao3 = 1;
141 sctlr.rao4 = 0xf; // SCTLR[6:3]
142 sctlr.uci = 1;
143 sctlr.dze = 1;
144 miscRegs[MISCREG_SCTLR_NS] = sctlr;
145 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
146 miscRegs[MISCREG_HCPTR] = 0;
147
148 // Start with an event in the mailbox
149 miscRegs[MISCREG_SEV_MAILBOX] = 1;
150
151 // Separate Instruction and Data TLBs
152 miscRegs[MISCREG_TLBTR] = 1;
153
154 MVFR0 mvfr0 = 0;
155 mvfr0.advSimdRegisters = 2;
156 mvfr0.singlePrecision = 2;
157 mvfr0.doublePrecision = 2;
158 mvfr0.vfpExceptionTrapping = 0;
159 mvfr0.divide = 1;
160 mvfr0.squareRoot = 1;
161 mvfr0.shortVectors = 1;
162 mvfr0.roundingModes = 1;
163 miscRegs[MISCREG_MVFR0] = mvfr0;
164
165 MVFR1 mvfr1 = 0;
166 mvfr1.flushToZero = 1;
167 mvfr1.defaultNaN = 1;
168 mvfr1.advSimdLoadStore = 1;
169 mvfr1.advSimdInteger = 1;
170 mvfr1.advSimdSinglePrecision = 1;
171 mvfr1.advSimdHalfPrecision = 1;
172 mvfr1.vfpHalfPrecision = 1;
173 miscRegs[MISCREG_MVFR1] = mvfr1;
174
175 // Reset values of PRRR and NMRR are implementation dependent
176
177 // @todo: PRRR and NMRR in secure state?
178 miscRegs[MISCREG_PRRR_NS] =
179 (1 << 19) | // 19
180 (0 << 18) | // 18
181 (0 << 17) | // 17
182 (1 << 16) | // 16
183 (2 << 14) | // 15:14
184 (0 << 12) | // 13:12
185 (2 << 10) | // 11:10
186 (2 << 8) | // 9:8
187 (2 << 6) | // 7:6
188 (2 << 4) | // 5:4
189 (1 << 2) | // 3:2
190 0; // 1:0
191 miscRegs[MISCREG_NMRR_NS] =
192 (1 << 30) | // 31:30
193 (0 << 26) | // 27:26
194 (0 << 24) | // 25:24
195 (3 << 22) | // 23:22
196 (2 << 20) | // 21:20
197 (0 << 18) | // 19:18
198 (0 << 16) | // 17:16
199 (1 << 14) | // 15:14
200 (0 << 12) | // 13:12
201 (2 << 10) | // 11:10
202 (0 << 8) | // 9:8
203 (3 << 6) | // 7:6
204 (2 << 4) | // 5:4
205 (0 << 2) | // 3:2
206 0; // 1:0
207
208 miscRegs[MISCREG_CPACR] = 0;
209
210 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
211 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
212 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
213 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
214
215 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
216 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
217 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
218 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
219 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
220 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
221
222 miscRegs[MISCREG_FPSID] = p->fpsid;
223
224 if (haveLPAE) {
225 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
226 ttbcr.eae = 0;
227 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
228 // Enforce consistency with system-level settings
229 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
230 }
231
232 if (haveSecurity) {
233 miscRegs[MISCREG_SCTLR_S] = sctlr;
234 miscRegs[MISCREG_SCR] = 0;
235 miscRegs[MISCREG_VBAR_S] = 0;
236 } else {
237 // we're always non-secure
238 miscRegs[MISCREG_SCR] = 1;
239 }
240
241 //XXX We need to initialize the rest of the state.
242}
243
244void
245ISA::clear64(const ArmISAParams *p)
246{
247 CPSR cpsr = 0;
248 Addr rvbar = system->resetAddr64();
249 switch (system->highestEL()) {
250 // Set initial EL to highest implemented EL using associated stack
251 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
252 // value
253 case EL3:
254 cpsr.mode = MODE_EL3H;
255 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
256 break;
257 case EL2:
258 cpsr.mode = MODE_EL2H;
259 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
260 break;
261 case EL1:
262 cpsr.mode = MODE_EL1H;
263 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
264 break;
265 default:
266 panic("Invalid highest implemented exception level");
267 break;
268 }
269
270 // Initialize rest of CPSR
271 cpsr.daif = 0xf; // Mask all interrupts
272 cpsr.ss = 0;
273 cpsr.il = 0;
274 miscRegs[MISCREG_CPSR] = cpsr;
275 updateRegMap(cpsr);
276
277 // Initialize other control registers
278 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
279 if (haveSecurity) {
280 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
281 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
282 } else if (haveVirtualization) {
283 // also MISCREG_SCTLR_EL2 (by mapping)
284 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
285 } else {
286 // also MISCREG_SCTLR_EL1 (by mapping)
287 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
288 // Always non-secure
289 miscRegs[MISCREG_SCR_EL3] = 1;
290 }
291
292 // Initialize configurable id registers
293 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
294 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
295 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
296 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
297 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
298
299 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
300 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
301 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
302 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
303 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
304
305 miscRegs[MISCREG_ID_DFR0_EL1] =
306 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
307
308 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
309
310 // Enforce consistency with system-level settings...
311
312 // EL3
313 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
314 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
315 haveSecurity ? 0x2 : 0x0);
316 // EL2
317 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
318 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
319 haveVirtualization ? 0x2 : 0x0);
320 // Large ASID support
321 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
322 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
323 haveLargeAsid64 ? 0x2 : 0x0);
324 // Physical address size
325 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
326 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
327 encodePhysAddrRange64(physAddrRange64));
328}
329
330MiscReg
331ISA::readMiscRegNoEffect(int misc_reg) const
332{
333 assert(misc_reg < NumMiscRegs);
334
335 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
336 const auto &map = getMiscIndices(misc_reg);
337 int lower = map.first, upper = map.second;
338 // NB!: apply architectural masks according to desired register,
339 // despite possibly getting value from different (mapped) register.
340 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
341 |(miscRegs[upper] << 32));
342 if (val & reg.res0()) {
343 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
344 miscRegName[misc_reg], val & reg.res0());
345 }
346 if ((val & reg.res1()) != reg.res1()) {
347 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
348 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
349 }
350 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
351}
352
353
354MiscReg
355ISA::readMiscReg(int misc_reg, ThreadContext *tc)
356{
357 CPSR cpsr = 0;
358 PCState pc = 0;
359 SCR scr = 0;
360
361 if (misc_reg == MISCREG_CPSR) {
362 cpsr = miscRegs[misc_reg];
363 pc = tc->pcState();
364 cpsr.j = pc.jazelle() ? 1 : 0;
365 cpsr.t = pc.thumb() ? 1 : 0;
366 return cpsr;
367 }
368
369#ifndef NDEBUG
370 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
371 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
372 warn("Unimplemented system register %s read.\n",
373 miscRegName[misc_reg]);
374 else
375 panic("Unimplemented system register %s read.\n",
376 miscRegName[misc_reg]);
377 }
378#endif
379
380 switch (unflattenMiscReg(misc_reg)) {
381 case MISCREG_HCR:
382 {
383 if (!haveVirtualization)
384 return 0;
385 else
386 return readMiscRegNoEffect(MISCREG_HCR);
387 }
388 case MISCREG_CPACR:
389 {
390 const uint32_t ones = (uint32_t)(-1);
391 CPACR cpacrMask = 0;
392 // Only cp10, cp11, and ase are implemented, nothing else should
393 // be readable? (straight copy from the write code)
394 cpacrMask.cp10 = ones;
395 cpacrMask.cp11 = ones;
396 cpacrMask.asedis = ones;
397
398 // Security Extensions may limit the readability of CPACR
399 if (haveSecurity) {
400 scr = readMiscRegNoEffect(MISCREG_SCR);
401 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
402 if (scr.ns && (cpsr.mode != MODE_MON)) {
403 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
404 // NB: Skipping the full loop, here
405 if (!nsacr.cp10) cpacrMask.cp10 = 0;
406 if (!nsacr.cp11) cpacrMask.cp11 = 0;
407 }
408 }
409 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
410 val &= cpacrMask;
411 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
412 miscRegName[misc_reg], val);
413 return val;
414 }
415 case MISCREG_MPIDR:
416 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
417 scr = readMiscRegNoEffect(MISCREG_SCR);
418 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
419 return getMPIDR(system, tc);
420 } else {
421 return readMiscReg(MISCREG_VMPIDR, tc);
422 }
423 break;
424 case MISCREG_MPIDR_EL1:
425 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
426 return getMPIDR(system, tc) & 0xffffffff;
427 case MISCREG_VMPIDR:
428 // top bit defined as RES1
429 return readMiscRegNoEffect(misc_reg) | 0x80000000;
430 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
431 case MISCREG_REVIDR: // not implemented, so alias MIDR
432 case MISCREG_MIDR:
433 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
434 scr = readMiscRegNoEffect(MISCREG_SCR);
435 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
436 return readMiscRegNoEffect(misc_reg);
437 } else {
438 return readMiscRegNoEffect(MISCREG_VPIDR);
439 }
440 break;
441 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
442 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_AIDR: // AUX ID set to 0
445 case MISCREG_TCMTR: // No TCM's
446 return 0;
447
448 case MISCREG_CLIDR:
449 warn_once("The clidr register always reports 0 caches.\n");
450 warn_once("clidr LoUIS field of 0b001 to match current "
451 "ARM implementations.\n");
452 return 0x00200000;
453 case MISCREG_CCSIDR:
454 warn_once("The ccsidr register isn't implemented and "
455 "always reads as 0.\n");
456 break;
457 case MISCREG_CTR: // AArch32, ARMv7, top bit set
458 case MISCREG_CTR_EL0: // AArch64
459 {
460 //all caches have the same line size in gem5
461 //4 byte words in ARM
462 unsigned lineSizeWords =
463 tc->getSystemPtr()->cacheLineSize() / 4;
464 unsigned log2LineSizeWords = 0;
465
466 while (lineSizeWords >>= 1) {
467 ++log2LineSizeWords;
468 }
469
470 CTR ctr = 0;
471 //log2 of minimun i-cache line size (words)
472 ctr.iCacheLineSize = log2LineSizeWords;
473 //b11 - gem5 uses pipt
474 ctr.l1IndexPolicy = 0x3;
475 //log2 of minimum d-cache line size (words)
476 ctr.dCacheLineSize = log2LineSizeWords;
477 //log2 of max reservation size (words)
478 ctr.erg = log2LineSizeWords;
479 //log2 of max writeback size (words)
480 ctr.cwg = log2LineSizeWords;
481 //b100 - gem5 format is ARMv7
482 ctr.format = 0x4;
483
484 return ctr;
485 }
486 case MISCREG_ACTLR:
487 warn("Not doing anything for miscreg ACTLR\n");
488 break;
489
490 case MISCREG_PMXEVTYPER_PMCCFILTR:
491 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
492 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
493 case MISCREG_PMCR ... MISCREG_PMOVSSET:
494 return pmu->readMiscReg(misc_reg);
495
496 case MISCREG_CPSR_Q:
497 panic("shouldn't be reading this register seperately\n");
498 case MISCREG_FPSCR_QC:
499 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
500 case MISCREG_FPSCR_EXC:
501 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
502 case MISCREG_FPSR:
503 {
504 const uint32_t ones = (uint32_t)(-1);
505 FPSCR fpscrMask = 0;
506 fpscrMask.ioc = ones;
507 fpscrMask.dzc = ones;
508 fpscrMask.ofc = ones;
509 fpscrMask.ufc = ones;
510 fpscrMask.ixc = ones;
511 fpscrMask.idc = ones;
512 fpscrMask.qc = ones;
513 fpscrMask.v = ones;
514 fpscrMask.c = ones;
515 fpscrMask.z = ones;
516 fpscrMask.n = ones;
517 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
518 }
519 case MISCREG_FPCR:
520 {
521 const uint32_t ones = (uint32_t)(-1);
522 FPSCR fpscrMask = 0;
523 fpscrMask.ioe = ones;
524 fpscrMask.dze = ones;
525 fpscrMask.ofe = ones;
526 fpscrMask.ufe = ones;
527 fpscrMask.ixe = ones;
528 fpscrMask.ide = ones;
529 fpscrMask.len = ones;
530 fpscrMask.stride = ones;
531 fpscrMask.rMode = ones;
532 fpscrMask.fz = ones;
533 fpscrMask.dn = ones;
534 fpscrMask.ahp = ones;
535 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
536 }
537 case MISCREG_NZCV:
538 {
539 CPSR cpsr = 0;
540 cpsr.nz = tc->readCCReg(CCREG_NZ);
541 cpsr.c = tc->readCCReg(CCREG_C);
542 cpsr.v = tc->readCCReg(CCREG_V);
543 return cpsr;
544 }
545 case MISCREG_DAIF:
546 {
547 CPSR cpsr = 0;
548 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
549 return cpsr;
550 }
551 case MISCREG_SP_EL0:
552 {
553 return tc->readIntReg(INTREG_SP0);
554 }
555 case MISCREG_SP_EL1:
556 {
557 return tc->readIntReg(INTREG_SP1);
558 }
559 case MISCREG_SP_EL2:
560 {
561 return tc->readIntReg(INTREG_SP2);
562 }
563 case MISCREG_SPSEL:
564 {
565 return miscRegs[MISCREG_CPSR] & 0x1;
566 }
567 case MISCREG_CURRENTEL:
568 {
569 return miscRegs[MISCREG_CPSR] & 0xc;
570 }
571 case MISCREG_L2CTLR:
572 {
573 // mostly unimplemented, just set NumCPUs field from sim and return
574 L2CTLR l2ctlr = 0;
575 // b00:1CPU to b11:4CPUs
576 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
577 return l2ctlr;
578 }
579 case MISCREG_DBGDIDR:
580 /* For now just implement the version number.
581 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
582 */
583 return 0x5 << 16;
584 case MISCREG_DBGDSCRint:
585 return 0;
586 case MISCREG_ISR:
587 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
588 readMiscRegNoEffect(MISCREG_HCR),
589 readMiscRegNoEffect(MISCREG_CPSR),
590 readMiscRegNoEffect(MISCREG_SCR));
591 case MISCREG_ISR_EL1:
592 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
593 readMiscRegNoEffect(MISCREG_HCR_EL2),
594 readMiscRegNoEffect(MISCREG_CPSR),
595 readMiscRegNoEffect(MISCREG_SCR_EL3));
596 case MISCREG_DCZID_EL0:
597 return 0x04; // DC ZVA clear 64-byte chunks
598 case MISCREG_HCPTR:
599 {
600 MiscReg val = readMiscRegNoEffect(misc_reg);
601 // The trap bit associated with CP14 is defined as RAZ
602 val &= ~(1 << 14);
603 // If a CP bit in NSACR is 0 then the corresponding bit in
604 // HCPTR is RAO/WI
605 bool secure_lookup = haveSecurity &&
606 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
607 readMiscRegNoEffect(MISCREG_CPSR));
608 if (!secure_lookup) {
609 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
610 val |= (mask ^ 0x7FFF) & 0xBFFF;
611 }
612 // Set the bits for unimplemented coprocessors to RAO/WI
613 val |= 0x33FF;
614 return (val);
615 }
616 case MISCREG_HDFAR: // alias for secure DFAR
617 return readMiscRegNoEffect(MISCREG_DFAR_S);
618 case MISCREG_HIFAR: // alias for secure IFAR
619 return readMiscRegNoEffect(MISCREG_IFAR_S);
620 case MISCREG_HVBAR: // bottom bits reserved
621 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
622 case MISCREG_SCTLR:
623 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
624 case MISCREG_SCTLR_EL1:
625 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
626 case MISCREG_SCTLR_EL2:
627 case MISCREG_SCTLR_EL3:
628 case MISCREG_HSCTLR:
629 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
630
631 case MISCREG_ID_PFR0:
632 // !ThumbEE | !Jazelle | Thumb | ARM
633 return 0x00000031;
634 case MISCREG_ID_PFR1:
635 { // Timer | Virti | !M Profile | TrustZone | ARMv4
636 bool haveTimer = (system->getGenericTimer() != NULL);
637 return 0x00000001
638 | (haveSecurity ? 0x00000010 : 0x0)
639 | (haveVirtualization ? 0x00001000 : 0x0)
640 | (haveTimer ? 0x00010000 : 0x0);
641 }
642 case MISCREG_ID_AA64PFR0_EL1:
643 return 0x0000000000000002 // AArch{64,32} supported at EL0
644 | 0x0000000000000020 // EL1
645 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
646 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
647 case MISCREG_ID_AA64PFR1_EL1:
648 return 0; // bits [63:0] RES0 (reserved for future use)
649
650 // Generic Timer registers
651 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
652 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
653 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
654 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
655 return getGenericTimer(tc).readMiscReg(misc_reg);
656
657 default:
658 break;
659
660 }
661 return readMiscRegNoEffect(misc_reg);
662}
663
664void
665ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
666{
667 assert(misc_reg < NumMiscRegs);
668
669 const auto ® = lookUpMiscReg[misc_reg]; // bit masks
670 const auto &map = getMiscIndices(misc_reg);
671 int lower = map.first, upper = map.second;
672
673 auto v = (val & ~reg.wi()) | reg.rao();
674 if (upper > 0) {
675 miscRegs[lower] = bits(v, 31, 0);
676 miscRegs[upper] = bits(v, 63, 32);
677 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
678 misc_reg, lower, upper, v);
679 } else {
680 miscRegs[lower] = v;
681 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
682 misc_reg, lower, v);
683 }
684}
685
686namespace {
687
688template<typename T>
689TLB *
690getITBPtr(T *tc)
691{
692 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
693 assert(tlb);
694 return tlb;
695}
696
697template<typename T>
698TLB *
699getDTBPtr(T *tc)
700{
701 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
702 assert(tlb);
703 return tlb;
704}
705
706} // anonymous namespace
707
708void
709ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
710{
711
712 MiscReg newVal = val;
713 int x;
714 bool secure_lookup;
715 bool hyp;
716 System *sys;
717 ThreadContext *oc;
718 uint8_t target_el;
719 uint16_t asid;
720 SCR scr;
721
722 if (misc_reg == MISCREG_CPSR) {
723 updateRegMap(val);
724
725
726 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
727 int old_mode = old_cpsr.mode;
728 CPSR cpsr = val;
729 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
730 getITBPtr(tc)->invalidateMiscReg();
731 getDTBPtr(tc)->invalidateMiscReg();
732 }
733
734 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
735 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
736 PCState pc = tc->pcState();
737 pc.nextThumb(cpsr.t);
738 pc.nextJazelle(cpsr.j);
739
740 // Follow slightly different semantics if a CheckerCPU object
741 // is connected
742 CheckerCPU *checker = tc->getCheckerCpuPtr();
743 if (checker) {
744 tc->pcStateNoRecord(pc);
745 } else {
746 tc->pcState(pc);
747 }
748 } else {
749#ifndef NDEBUG
750 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
751 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
752 warn("Unimplemented system register %s write with %#x.\n",
753 miscRegName[misc_reg], val);
754 else
755 panic("Unimplemented system register %s write with %#x.\n",
756 miscRegName[misc_reg], val);
757 }
758#endif
759 switch (unflattenMiscReg(misc_reg)) {
760 case MISCREG_CPACR:
761 {
762
763 const uint32_t ones = (uint32_t)(-1);
764 CPACR cpacrMask = 0;
765 // Only cp10, cp11, and ase are implemented, nothing else should
766 // be writable
767 cpacrMask.cp10 = ones;
768 cpacrMask.cp11 = ones;
769 cpacrMask.asedis = ones;
770
771 // Security Extensions may limit the writability of CPACR
772 if (haveSecurity) {
773 scr = readMiscRegNoEffect(MISCREG_SCR);
774 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
775 if (scr.ns && (cpsr.mode != MODE_MON)) {
776 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
777 // NB: Skipping the full loop, here
778 if (!nsacr.cp10) cpacrMask.cp10 = 0;
779 if (!nsacr.cp11) cpacrMask.cp11 = 0;
780 }
781 }
782
783 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
784 newVal &= cpacrMask;
785 newVal |= old_val & ~cpacrMask;
786 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
787 miscRegName[misc_reg], newVal);
788 }
789 break;
790 case MISCREG_CPACR_EL1:
791 {
792 const uint32_t ones = (uint32_t)(-1);
793 CPACR cpacrMask = 0;
794 cpacrMask.tta = ones;
795 cpacrMask.fpen = ones;
796 newVal &= cpacrMask;
797 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
798 miscRegName[misc_reg], newVal);
799 }
800 break;
801 case MISCREG_CPTR_EL2:
802 {
803 const uint32_t ones = (uint32_t)(-1);
804 CPTR cptrMask = 0;
805 cptrMask.tcpac = ones;
806 cptrMask.tta = ones;
807 cptrMask.tfp = ones;
808 newVal &= cptrMask;
809 cptrMask = 0;
810 cptrMask.res1_13_12_el2 = ones;
811 cptrMask.res1_9_0_el2 = ones;
812 newVal |= cptrMask;
813 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
814 miscRegName[misc_reg], newVal);
815 }
816 break;
817 case MISCREG_CPTR_EL3:
818 {
819 const uint32_t ones = (uint32_t)(-1);
820 CPTR cptrMask = 0;
821 cptrMask.tcpac = ones;
822 cptrMask.tta = ones;
823 cptrMask.tfp = ones;
824 newVal &= cptrMask;
825 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
826 miscRegName[misc_reg], newVal);
827 }
828 break;
829 case MISCREG_CSSELR:
830 warn_once("The csselr register isn't implemented.\n");
831 return;
832
833 case MISCREG_DC_ZVA_Xt:
834 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
835 return;
836
837 case MISCREG_FPSCR:
838 {
839 const uint32_t ones = (uint32_t)(-1);
840 FPSCR fpscrMask = 0;
841 fpscrMask.ioc = ones;
842 fpscrMask.dzc = ones;
843 fpscrMask.ofc = ones;
844 fpscrMask.ufc = ones;
845 fpscrMask.ixc = ones;
846 fpscrMask.idc = ones;
847 fpscrMask.ioe = ones;
848 fpscrMask.dze = ones;
849 fpscrMask.ofe = ones;
850 fpscrMask.ufe = ones;
851 fpscrMask.ixe = ones;
852 fpscrMask.ide = ones;
853 fpscrMask.len = ones;
854 fpscrMask.stride = ones;
855 fpscrMask.rMode = ones;
856 fpscrMask.fz = ones;
857 fpscrMask.dn = ones;
858 fpscrMask.ahp = ones;
859 fpscrMask.qc = ones;
860 fpscrMask.v = ones;
861 fpscrMask.c = ones;
862 fpscrMask.z = ones;
863 fpscrMask.n = ones;
864 newVal = (newVal & (uint32_t)fpscrMask) |
865 (readMiscRegNoEffect(MISCREG_FPSCR) &
866 ~(uint32_t)fpscrMask);
867 tc->getDecoderPtr()->setContext(newVal);
868 }
869 break;
870 case MISCREG_FPSR:
871 {
872 const uint32_t ones = (uint32_t)(-1);
873 FPSCR fpscrMask = 0;
874 fpscrMask.ioc = ones;
875 fpscrMask.dzc = ones;
876 fpscrMask.ofc = ones;
877 fpscrMask.ufc = ones;
878 fpscrMask.ixc = ones;
879 fpscrMask.idc = ones;
880 fpscrMask.qc = ones;
881 fpscrMask.v = ones;
882 fpscrMask.c = ones;
883 fpscrMask.z = ones;
884 fpscrMask.n = ones;
885 newVal = (newVal & (uint32_t)fpscrMask) |
886 (readMiscRegNoEffect(MISCREG_FPSCR) &
887 ~(uint32_t)fpscrMask);
888 misc_reg = MISCREG_FPSCR;
889 }
890 break;
891 case MISCREG_FPCR:
892 {
893 const uint32_t ones = (uint32_t)(-1);
894 FPSCR fpscrMask = 0;
895 fpscrMask.ioe = ones;
896 fpscrMask.dze = ones;
897 fpscrMask.ofe = ones;
898 fpscrMask.ufe = ones;
899 fpscrMask.ixe = ones;
900 fpscrMask.ide = ones;
901 fpscrMask.len = ones;
902 fpscrMask.stride = ones;
903 fpscrMask.rMode = ones;
904 fpscrMask.fz = ones;
905 fpscrMask.dn = ones;
906 fpscrMask.ahp = ones;
907 newVal = (newVal & (uint32_t)fpscrMask) |
908 (readMiscRegNoEffect(MISCREG_FPSCR) &
909 ~(uint32_t)fpscrMask);
910 misc_reg = MISCREG_FPSCR;
911 }
912 break;
913 case MISCREG_CPSR_Q:
914 {
915 assert(!(newVal & ~CpsrMaskQ));
916 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
917 misc_reg = MISCREG_CPSR;
918 }
919 break;
920 case MISCREG_FPSCR_QC:
921 {
922 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
923 (newVal & FpscrQcMask);
924 misc_reg = MISCREG_FPSCR;
925 }
926 break;
927 case MISCREG_FPSCR_EXC:
928 {
929 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
930 (newVal & FpscrExcMask);
931 misc_reg = MISCREG_FPSCR;
932 }
933 break;
934 case MISCREG_FPEXC:
935 {
936 // vfpv3 architecture, section B.6.1 of DDI04068
937 // bit 29 - valid only if fpexc[31] is 0
938 const uint32_t fpexcMask = 0x60000000;
939 newVal = (newVal & fpexcMask) |
940 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
941 }
942 break;
943 case MISCREG_HCR:
944 {
945 if (!haveVirtualization)
946 return;
947 }
948 break;
949 case MISCREG_IFSR:
950 {
951 // ARM ARM (ARM DDI 0406C.b) B4.1.96
952 const uint32_t ifsrMask =
953 mask(31, 13) | mask(11, 11) | mask(8, 6);
954 newVal = newVal & ~ifsrMask;
955 }
956 break;
957 case MISCREG_DFSR:
958 {
959 // ARM ARM (ARM DDI 0406C.b) B4.1.52
960 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
961 newVal = newVal & ~dfsrMask;
962 }
963 break;
964 case MISCREG_AMAIR0:
965 case MISCREG_AMAIR1:
966 {
967 // ARM ARM (ARM DDI 0406C.b) B4.1.5
968 // Valid only with LPAE
969 if (!haveLPAE)
970 return;
971 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
972 }
973 break;
974 case MISCREG_SCR:
975 getITBPtr(tc)->invalidateMiscReg();
976 getDTBPtr(tc)->invalidateMiscReg();
977 break;
978 case MISCREG_SCTLR:
979 {
980 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
981 scr = readMiscRegNoEffect(MISCREG_SCR);
982 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
983 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
984 SCTLR sctlr = miscRegs[sctlr_idx];
985 SCTLR new_sctlr = newVal;
986 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
987 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
988 getITBPtr(tc)->invalidateMiscReg();
989 getDTBPtr(tc)->invalidateMiscReg();
990 }
991 case MISCREG_MIDR:
992 case MISCREG_ID_PFR0:
993 case MISCREG_ID_PFR1:
994 case MISCREG_ID_DFR0:
995 case MISCREG_ID_MMFR0:
996 case MISCREG_ID_MMFR1:
997 case MISCREG_ID_MMFR2:
998 case MISCREG_ID_MMFR3:
999 case MISCREG_ID_ISAR0:
1000 case MISCREG_ID_ISAR1:
1001 case MISCREG_ID_ISAR2:
1002 case MISCREG_ID_ISAR3:
1003 case MISCREG_ID_ISAR4:
1004 case MISCREG_ID_ISAR5:
1005
1006 case MISCREG_MPIDR:
1007 case MISCREG_FPSID:
1008 case MISCREG_TLBTR:
1009 case MISCREG_MVFR0:
1010 case MISCREG_MVFR1:
1011
1012 case MISCREG_ID_AA64AFR0_EL1:
1013 case MISCREG_ID_AA64AFR1_EL1:
1014 case MISCREG_ID_AA64DFR0_EL1:
1015 case MISCREG_ID_AA64DFR1_EL1:
1016 case MISCREG_ID_AA64ISAR0_EL1:
1017 case MISCREG_ID_AA64ISAR1_EL1:
1018 case MISCREG_ID_AA64MMFR0_EL1:
1019 case MISCREG_ID_AA64MMFR1_EL1:
1020 case MISCREG_ID_AA64PFR0_EL1:
1021 case MISCREG_ID_AA64PFR1_EL1:
1022 // ID registers are constants.
1023 return;
1024
1025 // TLBI all entries, EL0&1 inner sharable (ignored)
1026 case MISCREG_TLBIALLIS:
1027 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1028 assert32(tc);
1029 target_el = 1; // el 0 and 1 are handled together
1030 scr = readMiscReg(MISCREG_SCR, tc);
1031 secure_lookup = haveSecurity && !scr.ns;
1032 sys = tc->getSystemPtr();
1033 for (x = 0; x < sys->numContexts(); x++) {
1034 oc = sys->getThreadContext(x);
1035 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1036 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1037
1038 // If CheckerCPU is connected, need to notify it of a flush
1039 CheckerCPU *checker = oc->getCheckerCpuPtr();
1040 if (checker) {
1041 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1042 target_el);
1043 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1044 target_el);
1045 }
1046 }
1047 return;
1048 // TLBI all entries, EL0&1, instruction side
1049 case MISCREG_ITLBIALL:
1050 assert32(tc);
1051 target_el = 1; // el 0 and 1 are handled together
1052 scr = readMiscReg(MISCREG_SCR, tc);
1053 secure_lookup = haveSecurity && !scr.ns;
1054 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1055 return;
1056 // TLBI all entries, EL0&1, data side
1057 case MISCREG_DTLBIALL:
1058 assert32(tc);
1059 target_el = 1; // el 0 and 1 are handled together
1060 scr = readMiscReg(MISCREG_SCR, tc);
1061 secure_lookup = haveSecurity && !scr.ns;
1062 getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1063 return;
1064 // TLBI based on VA, EL0&1 inner sharable (ignored)
1065 case MISCREG_TLBIMVAL:
1066 case MISCREG_TLBIMVALIS:
1067 // mcr tlbimval(is) is invalidating all matching entries
1068 // regardless of the level of lookup, since in gem5 we cache
1069 // in the tlb the last level of lookup only.
1070 case MISCREG_TLBIMVA:
1071 case MISCREG_TLBIMVAIS:
1072 assert32(tc);
1073 target_el = 1; // el 0 and 1 are handled together
1074 scr = readMiscReg(MISCREG_SCR, tc);
1075 secure_lookup = haveSecurity && !scr.ns;
1076 sys = tc->getSystemPtr();
1077 for (x = 0; x < sys->numContexts(); x++) {
1078 oc = sys->getThreadContext(x);
1079 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1080 bits(newVal, 7,0),
1081 secure_lookup, target_el);
1082 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1083 bits(newVal, 7,0),
1084 secure_lookup, target_el);
1085
1086 CheckerCPU *checker = oc->getCheckerCpuPtr();
1087 if (checker) {
1088 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1089 bits(newVal, 7,0), secure_lookup, target_el);
1090 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1091 bits(newVal, 7,0), secure_lookup, target_el);
1092 }
1093 }
1094 return;
1095 // TLBI by ASID, EL0&1, inner sharable
1096 case MISCREG_TLBIASIDIS:
1097 case MISCREG_TLBIASID:
1098 assert32(tc);
1099 target_el = 1; // el 0 and 1 are handled together
1100 scr = readMiscReg(MISCREG_SCR, tc);
1101 secure_lookup = haveSecurity && !scr.ns;
1102 sys = tc->getSystemPtr();
1103 for (x = 0; x < sys->numContexts(); x++) {
1104 oc = sys->getThreadContext(x);
1105 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1106 secure_lookup, target_el);
1107 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1108 secure_lookup, target_el);
1109 CheckerCPU *checker = oc->getCheckerCpuPtr();
1110 if (checker) {
1111 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1112 secure_lookup, target_el);
1113 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1114 secure_lookup, target_el);
1115 }
1116 }
1117 return;
1118 // TLBI by address, EL0&1, inner sharable (ignored)
1119 case MISCREG_TLBIMVAAL:
1120 case MISCREG_TLBIMVAALIS:
1121 // mcr tlbimvaal(is) is invalidating all matching entries
1122 // regardless of the level of lookup, since in gem5 we cache
1123 // in the tlb the last level of lookup only.
1124 case MISCREG_TLBIMVAA:
1125 case MISCREG_TLBIMVAAIS:
1126 assert32(tc);
1127 target_el = 1; // el 0 and 1 are handled together
1128 scr = readMiscReg(MISCREG_SCR, tc);
1129 secure_lookup = haveSecurity && !scr.ns;
1130 hyp = 0;
1131 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1132 return;
1133 // TLBI by address, EL2, hypervisor mode
1134 case MISCREG_TLBIMVALH:
1135 case MISCREG_TLBIMVALHIS:
1136 // mcr tlbimvalh(is) is invalidating all matching entries
1137 // regardless of the level of lookup, since in gem5 we cache
1138 // in the tlb the last level of lookup only.
1139 case MISCREG_TLBIMVAH:
1140 case MISCREG_TLBIMVAHIS:
1141 assert32(tc);
1142 target_el = 1; // aarch32, use hyp bit
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144 secure_lookup = haveSecurity && !scr.ns;
1145 hyp = 1;
1146 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1147 return;
|
| 1148 case MISCREG_TLBIIPAS2L:
1149 case MISCREG_TLBIIPAS2LIS:
1150 // mcr tlbiipas2l(is) is invalidating all matching entries
1151 // regardless of the level of lookup, since in gem5 we cache
1152 // in the tlb the last level of lookup only.
1153 case MISCREG_TLBIIPAS2:
1154 case MISCREG_TLBIIPAS2IS:
1155 assert32(tc);
1156 target_el = 1; // EL 0 and 1 are handled together
1157 scr = readMiscReg(MISCREG_SCR, tc);
1158 secure_lookup = haveSecurity && !scr.ns;
1159 tlbiIPA(tc, newVal, secure_lookup, target_el);
1160 return;
|
1148 // TLBI by address and asid, EL0&1, instruction side only
1149 case MISCREG_ITLBIMVA:
1150 assert32(tc);
1151 target_el = 1; // el 0 and 1 are handled together
1152 scr = readMiscReg(MISCREG_SCR, tc);
1153 secure_lookup = haveSecurity && !scr.ns;
1154 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1155 bits(newVal, 7,0), secure_lookup, target_el);
1156 return;
1157 // TLBI by address and asid, EL0&1, data side only
1158 case MISCREG_DTLBIMVA:
1159 assert32(tc);
1160 target_el = 1; // el 0 and 1 are handled together
1161 scr = readMiscReg(MISCREG_SCR, tc);
1162 secure_lookup = haveSecurity && !scr.ns;
1163 getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1164 bits(newVal, 7,0), secure_lookup, target_el);
1165 return;
1166 // TLBI by ASID, EL0&1, instrution side only
1167 case MISCREG_ITLBIASID:
1168 assert32(tc);
1169 target_el = 1; // el 0 and 1 are handled together
1170 scr = readMiscReg(MISCREG_SCR, tc);
1171 secure_lookup = haveSecurity && !scr.ns;
1172 getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1173 target_el);
1174 return;
1175 // TLBI by ASID EL0&1 data size only
1176 case MISCREG_DTLBIASID:
1177 assert32(tc);
1178 target_el = 1; // el 0 and 1 are handled together
1179 scr = readMiscReg(MISCREG_SCR, tc);
1180 secure_lookup = haveSecurity && !scr.ns;
1181 getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1182 target_el);
1183 return;
1184 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1185 case MISCREG_TLBIALLNSNH:
1186 case MISCREG_TLBIALLNSNHIS:
1187 assert32(tc);
1188 target_el = 1; // el 0 and 1 are handled together
1189 hyp = 0;
1190 tlbiALLN(tc, hyp, target_el);
1191 return;
1192 // TLBI all entries, EL2, hyp,
1193 case MISCREG_TLBIALLH:
1194 case MISCREG_TLBIALLHIS:
1195 assert32(tc);
1196 target_el = 1; // aarch32, use hyp bit
1197 hyp = 1;
1198 tlbiALLN(tc, hyp, target_el);
1199 return;
1200 // AArch64 TLBI: invalidate all entries EL3
1201 case MISCREG_TLBI_ALLE3IS:
1202 case MISCREG_TLBI_ALLE3:
1203 assert64(tc);
1204 target_el = 3;
1205 secure_lookup = true;
1206 tlbiALL(tc, secure_lookup, target_el);
1207 return;
1208 // @todo: uncomment this to enable Virtualization
1209 // case MISCREG_TLBI_ALLE2IS:
1210 // case MISCREG_TLBI_ALLE2:
1211 // TLBI all entries, EL0&1
1212 case MISCREG_TLBI_ALLE1IS:
1213 case MISCREG_TLBI_ALLE1:
1214 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1215 case MISCREG_TLBI_VMALLE1IS:
1216 case MISCREG_TLBI_VMALLE1:
1217 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1218 case MISCREG_TLBI_VMALLS12E1IS:
1219 case MISCREG_TLBI_VMALLS12E1:
1220 // @todo: handle VMID and stage 2 to enable Virtualization
1221 assert64(tc);
1222 target_el = 1; // el 0 and 1 are handled together
1223 scr = readMiscReg(MISCREG_SCR, tc);
1224 secure_lookup = haveSecurity && !scr.ns;
1225 tlbiALL(tc, secure_lookup, target_el);
1226 return;
1227 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1228 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1229 // from the last level of translation table walks
1230 // @todo: handle VMID to enable Virtualization
1231 // TLBI all entries, EL0&1
1232 case MISCREG_TLBI_VAE3IS_Xt:
1233 case MISCREG_TLBI_VAE3_Xt:
1234 // TLBI by VA, EL3 regime stage 1, last level walk
1235 case MISCREG_TLBI_VALE3IS_Xt:
1236 case MISCREG_TLBI_VALE3_Xt:
1237 assert64(tc);
1238 target_el = 3;
1239 asid = 0xbeef; // does not matter, tlbi is global
1240 secure_lookup = true;
1241 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1242 return;
1243 // TLBI by VA, EL2
1244 case MISCREG_TLBI_VAE2IS_Xt:
1245 case MISCREG_TLBI_VAE2_Xt:
1246 // TLBI by VA, EL2, stage1 last level walk
1247 case MISCREG_TLBI_VALE2IS_Xt:
1248 case MISCREG_TLBI_VALE2_Xt:
1249 assert64(tc);
1250 target_el = 2;
1251 asid = 0xbeef; // does not matter, tlbi is global
1252 scr = readMiscReg(MISCREG_SCR, tc);
1253 secure_lookup = haveSecurity && !scr.ns;
1254 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1255 return;
1256 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1257 case MISCREG_TLBI_VAE1IS_Xt:
1258 case MISCREG_TLBI_VAE1_Xt:
1259 case MISCREG_TLBI_VALE1IS_Xt:
1260 case MISCREG_TLBI_VALE1_Xt:
1261 assert64(tc);
1262 asid = bits(newVal, 63, 48);
1263 target_el = 1; // el 0 and 1 are handled together
1264 scr = readMiscReg(MISCREG_SCR, tc);
1265 secure_lookup = haveSecurity && !scr.ns;
1266 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1267 return;
1268 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1269 // @todo: handle VMID to enable Virtualization
1270 case MISCREG_TLBI_ASIDE1IS_Xt:
1271 case MISCREG_TLBI_ASIDE1_Xt:
1272 assert64(tc);
1273 target_el = 1; // el 0 and 1 are handled together
1274 scr = readMiscReg(MISCREG_SCR, tc);
1275 secure_lookup = haveSecurity && !scr.ns;
1276 sys = tc->getSystemPtr();
1277 for (x = 0; x < sys->numContexts(); x++) {
1278 oc = sys->getThreadContext(x);
1279 asid = bits(newVal, 63, 48);
1280 if (!haveLargeAsid64)
1281 asid &= mask(8);
1282 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1283 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1284 CheckerCPU *checker = oc->getCheckerCpuPtr();
1285 if (checker) {
1286 getITBPtr(checker)->flushAsid(asid,
1287 secure_lookup, target_el);
1288 getDTBPtr(checker)->flushAsid(asid,
1289 secure_lookup, target_el);
1290 }
1291 }
1292 return;
1293 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1294 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1295 // entries from the last level of translation table walks
1296 // @todo: handle VMID to enable Virtualization
1297 case MISCREG_TLBI_VAAE1IS_Xt:
1298 case MISCREG_TLBI_VAAE1_Xt:
1299 case MISCREG_TLBI_VAALE1IS_Xt:
1300 case MISCREG_TLBI_VAALE1_Xt:
1301 assert64(tc);
1302 target_el = 1; // el 0 and 1 are handled together
1303 scr = readMiscReg(MISCREG_SCR, tc);
1304 secure_lookup = haveSecurity && !scr.ns;
1305 sys = tc->getSystemPtr();
1306 for (x = 0; x < sys->numContexts(); x++) {
1307 // @todo: extra controls on TLBI broadcast?
1308 oc = sys->getThreadContext(x);
1309 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1310 getITBPtr(oc)->flushMva(va,
1311 secure_lookup, false, target_el);
1312 getDTBPtr(oc)->flushMva(va,
1313 secure_lookup, false, target_el);
1314
1315 CheckerCPU *checker = oc->getCheckerCpuPtr();
1316 if (checker) {
1317 getITBPtr(checker)->flushMva(va,
1318 secure_lookup, false, target_el);
1319 getDTBPtr(checker)->flushMva(va,
1320 secure_lookup, false, target_el);
1321 }
1322 }
1323 return;
1324 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1325 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1326 case MISCREG_TLBI_IPAS2LE1_Xt:
1327 case MISCREG_TLBI_IPAS2E1IS_Xt:
1328 case MISCREG_TLBI_IPAS2E1_Xt:
1329 assert64(tc);
1330 target_el = 1; // EL 0 and 1 are handled together
1331 scr = readMiscReg(MISCREG_SCR, tc);
1332 secure_lookup = haveSecurity && !scr.ns;
| 1161 // TLBI by address and asid, EL0&1, instruction side only
1162 case MISCREG_ITLBIMVA:
1163 assert32(tc);
1164 target_el = 1; // el 0 and 1 are handled together
1165 scr = readMiscReg(MISCREG_SCR, tc);
1166 secure_lookup = haveSecurity && !scr.ns;
1167 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1168 bits(newVal, 7,0), secure_lookup, target_el);
1169 return;
1170 // TLBI by address and asid, EL0&1, data side only
1171 case MISCREG_DTLBIMVA:
1172 assert32(tc);
1173 target_el = 1; // el 0 and 1 are handled together
1174 scr = readMiscReg(MISCREG_SCR, tc);
1175 secure_lookup = haveSecurity && !scr.ns;
1176 getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1177 bits(newVal, 7,0), secure_lookup, target_el);
1178 return;
1179 // TLBI by ASID, EL0&1, instrution side only
1180 case MISCREG_ITLBIASID:
1181 assert32(tc);
1182 target_el = 1; // el 0 and 1 are handled together
1183 scr = readMiscReg(MISCREG_SCR, tc);
1184 secure_lookup = haveSecurity && !scr.ns;
1185 getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1186 target_el);
1187 return;
1188 // TLBI by ASID EL0&1 data size only
1189 case MISCREG_DTLBIASID:
1190 assert32(tc);
1191 target_el = 1; // el 0 and 1 are handled together
1192 scr = readMiscReg(MISCREG_SCR, tc);
1193 secure_lookup = haveSecurity && !scr.ns;
1194 getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1195 target_el);
1196 return;
1197 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1198 case MISCREG_TLBIALLNSNH:
1199 case MISCREG_TLBIALLNSNHIS:
1200 assert32(tc);
1201 target_el = 1; // el 0 and 1 are handled together
1202 hyp = 0;
1203 tlbiALLN(tc, hyp, target_el);
1204 return;
1205 // TLBI all entries, EL2, hyp,
1206 case MISCREG_TLBIALLH:
1207 case MISCREG_TLBIALLHIS:
1208 assert32(tc);
1209 target_el = 1; // aarch32, use hyp bit
1210 hyp = 1;
1211 tlbiALLN(tc, hyp, target_el);
1212 return;
1213 // AArch64 TLBI: invalidate all entries EL3
1214 case MISCREG_TLBI_ALLE3IS:
1215 case MISCREG_TLBI_ALLE3:
1216 assert64(tc);
1217 target_el = 3;
1218 secure_lookup = true;
1219 tlbiALL(tc, secure_lookup, target_el);
1220 return;
1221 // @todo: uncomment this to enable Virtualization
1222 // case MISCREG_TLBI_ALLE2IS:
1223 // case MISCREG_TLBI_ALLE2:
1224 // TLBI all entries, EL0&1
1225 case MISCREG_TLBI_ALLE1IS:
1226 case MISCREG_TLBI_ALLE1:
1227 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1228 case MISCREG_TLBI_VMALLE1IS:
1229 case MISCREG_TLBI_VMALLE1:
1230 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1231 case MISCREG_TLBI_VMALLS12E1IS:
1232 case MISCREG_TLBI_VMALLS12E1:
1233 // @todo: handle VMID and stage 2 to enable Virtualization
1234 assert64(tc);
1235 target_el = 1; // el 0 and 1 are handled together
1236 scr = readMiscReg(MISCREG_SCR, tc);
1237 secure_lookup = haveSecurity && !scr.ns;
1238 tlbiALL(tc, secure_lookup, target_el);
1239 return;
1240 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1241 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1242 // from the last level of translation table walks
1243 // @todo: handle VMID to enable Virtualization
1244 // TLBI all entries, EL0&1
1245 case MISCREG_TLBI_VAE3IS_Xt:
1246 case MISCREG_TLBI_VAE3_Xt:
1247 // TLBI by VA, EL3 regime stage 1, last level walk
1248 case MISCREG_TLBI_VALE3IS_Xt:
1249 case MISCREG_TLBI_VALE3_Xt:
1250 assert64(tc);
1251 target_el = 3;
1252 asid = 0xbeef; // does not matter, tlbi is global
1253 secure_lookup = true;
1254 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1255 return;
1256 // TLBI by VA, EL2
1257 case MISCREG_TLBI_VAE2IS_Xt:
1258 case MISCREG_TLBI_VAE2_Xt:
1259 // TLBI by VA, EL2, stage1 last level walk
1260 case MISCREG_TLBI_VALE2IS_Xt:
1261 case MISCREG_TLBI_VALE2_Xt:
1262 assert64(tc);
1263 target_el = 2;
1264 asid = 0xbeef; // does not matter, tlbi is global
1265 scr = readMiscReg(MISCREG_SCR, tc);
1266 secure_lookup = haveSecurity && !scr.ns;
1267 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1268 return;
1269 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1270 case MISCREG_TLBI_VAE1IS_Xt:
1271 case MISCREG_TLBI_VAE1_Xt:
1272 case MISCREG_TLBI_VALE1IS_Xt:
1273 case MISCREG_TLBI_VALE1_Xt:
1274 assert64(tc);
1275 asid = bits(newVal, 63, 48);
1276 target_el = 1; // el 0 and 1 are handled together
1277 scr = readMiscReg(MISCREG_SCR, tc);
1278 secure_lookup = haveSecurity && !scr.ns;
1279 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1280 return;
1281 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1282 // @todo: handle VMID to enable Virtualization
1283 case MISCREG_TLBI_ASIDE1IS_Xt:
1284 case MISCREG_TLBI_ASIDE1_Xt:
1285 assert64(tc);
1286 target_el = 1; // el 0 and 1 are handled together
1287 scr = readMiscReg(MISCREG_SCR, tc);
1288 secure_lookup = haveSecurity && !scr.ns;
1289 sys = tc->getSystemPtr();
1290 for (x = 0; x < sys->numContexts(); x++) {
1291 oc = sys->getThreadContext(x);
1292 asid = bits(newVal, 63, 48);
1293 if (!haveLargeAsid64)
1294 asid &= mask(8);
1295 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1296 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1297 CheckerCPU *checker = oc->getCheckerCpuPtr();
1298 if (checker) {
1299 getITBPtr(checker)->flushAsid(asid,
1300 secure_lookup, target_el);
1301 getDTBPtr(checker)->flushAsid(asid,
1302 secure_lookup, target_el);
1303 }
1304 }
1305 return;
1306 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1307 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1308 // entries from the last level of translation table walks
1309 // @todo: handle VMID to enable Virtualization
1310 case MISCREG_TLBI_VAAE1IS_Xt:
1311 case MISCREG_TLBI_VAAE1_Xt:
1312 case MISCREG_TLBI_VAALE1IS_Xt:
1313 case MISCREG_TLBI_VAALE1_Xt:
1314 assert64(tc);
1315 target_el = 1; // el 0 and 1 are handled together
1316 scr = readMiscReg(MISCREG_SCR, tc);
1317 secure_lookup = haveSecurity && !scr.ns;
1318 sys = tc->getSystemPtr();
1319 for (x = 0; x < sys->numContexts(); x++) {
1320 // @todo: extra controls on TLBI broadcast?
1321 oc = sys->getThreadContext(x);
1322 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1323 getITBPtr(oc)->flushMva(va,
1324 secure_lookup, false, target_el);
1325 getDTBPtr(oc)->flushMva(va,
1326 secure_lookup, false, target_el);
1327
1328 CheckerCPU *checker = oc->getCheckerCpuPtr();
1329 if (checker) {
1330 getITBPtr(checker)->flushMva(va,
1331 secure_lookup, false, target_el);
1332 getDTBPtr(checker)->flushMva(va,
1333 secure_lookup, false, target_el);
1334 }
1335 }
1336 return;
1337 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1338 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1339 case MISCREG_TLBI_IPAS2LE1_Xt:
1340 case MISCREG_TLBI_IPAS2E1IS_Xt:
1341 case MISCREG_TLBI_IPAS2E1_Xt:
1342 assert64(tc);
1343 target_el = 1; // EL 0 and 1 are handled together
1344 scr = readMiscReg(MISCREG_SCR, tc);
1345 secure_lookup = haveSecurity && !scr.ns;
|
1333 sys = tc->getSystemPtr();
1334 for (x = 0; x < sys->numContexts(); x++) {
1335 oc = sys->getThreadContext(x);
1336 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1337 getITBPtr(oc)->flushIpaVmid(ipa,
1338 secure_lookup, false, target_el);
1339 getDTBPtr(oc)->flushIpaVmid(ipa,
1340 secure_lookup, false, target_el);
1341
1342 CheckerCPU *checker = oc->getCheckerCpuPtr();
1343 if (checker) {
1344 getITBPtr(checker)->flushIpaVmid(ipa,
1345 secure_lookup, false, target_el);
1346 getDTBPtr(checker)->flushIpaVmid(ipa,
1347 secure_lookup, false, target_el);
1348 }
1349 }
| 1346 tlbiIPA(tc, newVal, secure_lookup, target_el);
|
1350 return;
1351 case MISCREG_ACTLR:
1352 warn("Not doing anything for write of miscreg ACTLR\n");
1353 break;
1354
1355 case MISCREG_PMXEVTYPER_PMCCFILTR:
1356 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1357 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1358 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1359 pmu->setMiscReg(misc_reg, newVal);
1360 break;
1361
1362
1363 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1364 {
1365 HSTR hstrMask = 0;
1366 hstrMask.tjdbx = 1;
1367 newVal &= ~((uint32_t) hstrMask);
1368 break;
1369 }
1370 case MISCREG_HCPTR:
1371 {
1372 // If a CP bit in NSACR is 0 then the corresponding bit in
1373 // HCPTR is RAO/WI. Same applies to NSASEDIS
1374 secure_lookup = haveSecurity &&
1375 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1376 readMiscRegNoEffect(MISCREG_CPSR));
1377 if (!secure_lookup) {
1378 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1379 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1380 newVal = (newVal & ~mask) | (oldValue & mask);
1381 }
1382 break;
1383 }
1384 case MISCREG_HDFAR: // alias for secure DFAR
1385 misc_reg = MISCREG_DFAR_S;
1386 break;
1387 case MISCREG_HIFAR: // alias for secure IFAR
1388 misc_reg = MISCREG_IFAR_S;
1389 break;
1390 case MISCREG_ATS1CPR:
1391 case MISCREG_ATS1CPW:
1392 case MISCREG_ATS1CUR:
1393 case MISCREG_ATS1CUW:
1394 case MISCREG_ATS12NSOPR:
1395 case MISCREG_ATS12NSOPW:
1396 case MISCREG_ATS12NSOUR:
1397 case MISCREG_ATS12NSOUW:
1398 case MISCREG_ATS1HR:
1399 case MISCREG_ATS1HW:
1400 {
1401 Request::Flags flags = 0;
1402 BaseTLB::Mode mode = BaseTLB::Read;
1403 TLB::ArmTranslationType tranType = TLB::NormalTran;
1404 Fault fault;
1405 switch(misc_reg) {
1406 case MISCREG_ATS1CPR:
1407 flags = TLB::MustBeOne;
1408 tranType = TLB::S1CTran;
1409 mode = BaseTLB::Read;
1410 break;
1411 case MISCREG_ATS1CPW:
1412 flags = TLB::MustBeOne;
1413 tranType = TLB::S1CTran;
1414 mode = BaseTLB::Write;
1415 break;
1416 case MISCREG_ATS1CUR:
1417 flags = TLB::MustBeOne | TLB::UserMode;
1418 tranType = TLB::S1CTran;
1419 mode = BaseTLB::Read;
1420 break;
1421 case MISCREG_ATS1CUW:
1422 flags = TLB::MustBeOne | TLB::UserMode;
1423 tranType = TLB::S1CTran;
1424 mode = BaseTLB::Write;
1425 break;
1426 case MISCREG_ATS12NSOPR:
1427 if (!haveSecurity)
1428 panic("Security Extensions required for ATS12NSOPR");
1429 flags = TLB::MustBeOne;
1430 tranType = TLB::S1S2NsTran;
1431 mode = BaseTLB::Read;
1432 break;
1433 case MISCREG_ATS12NSOPW:
1434 if (!haveSecurity)
1435 panic("Security Extensions required for ATS12NSOPW");
1436 flags = TLB::MustBeOne;
1437 tranType = TLB::S1S2NsTran;
1438 mode = BaseTLB::Write;
1439 break;
1440 case MISCREG_ATS12NSOUR:
1441 if (!haveSecurity)
1442 panic("Security Extensions required for ATS12NSOUR");
1443 flags = TLB::MustBeOne | TLB::UserMode;
1444 tranType = TLB::S1S2NsTran;
1445 mode = BaseTLB::Read;
1446 break;
1447 case MISCREG_ATS12NSOUW:
1448 if (!haveSecurity)
1449 panic("Security Extensions required for ATS12NSOUW");
1450 flags = TLB::MustBeOne | TLB::UserMode;
1451 tranType = TLB::S1S2NsTran;
1452 mode = BaseTLB::Write;
1453 break;
1454 case MISCREG_ATS1HR: // only really useful from secure mode.
1455 flags = TLB::MustBeOne;
1456 tranType = TLB::HypMode;
1457 mode = BaseTLB::Read;
1458 break;
1459 case MISCREG_ATS1HW:
1460 flags = TLB::MustBeOne;
1461 tranType = TLB::HypMode;
1462 mode = BaseTLB::Write;
1463 break;
1464 }
1465 // If we're in timing mode then doing the translation in
1466 // functional mode then we're slightly distorting performance
1467 // results obtained from simulations. The translation should be
1468 // done in the same mode the core is running in. NOTE: This
1469 // can't be an atomic translation because that causes problems
1470 // with unexpected atomic snoop requests.
1471 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1472 Request req(0, val, 0, flags, Request::funcMasterId,
1473 tc->pcState().pc(), tc->contextId());
1474 fault = getDTBPtr(tc)->translateFunctional(
1475 &req, tc, mode, tranType);
1476 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1477 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1478
1479 MiscReg newVal;
1480 if (fault == NoFault) {
1481 Addr paddr = req.getPaddr();
1482 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1483 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1484 newVal = (paddr & mask(39, 12)) |
1485 (getDTBPtr(tc)->getAttr());
1486 } else {
1487 newVal = (paddr & 0xfffff000) |
1488 (getDTBPtr(tc)->getAttr());
1489 }
1490 DPRINTF(MiscRegs,
1491 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1492 val, newVal);
1493 } else {
1494 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1495 armFault->update(tc);
1496 // Set fault bit and FSR
1497 FSR fsr = armFault->getFsr(tc);
1498
1499 newVal = ((fsr >> 9) & 1) << 11;
1500 if (newVal) {
1501 // LPAE - rearange fault status
1502 newVal |= ((fsr >> 0) & 0x3f) << 1;
1503 } else {
1504 // VMSA - rearange fault status
1505 newVal |= ((fsr >> 0) & 0xf) << 1;
1506 newVal |= ((fsr >> 10) & 0x1) << 5;
1507 newVal |= ((fsr >> 12) & 0x1) << 6;
1508 }
1509 newVal |= 0x1; // F bit
1510 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1511 newVal |= armFault->isStage2() ? 0x200 : 0;
1512 DPRINTF(MiscRegs,
1513 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1514 val, fsr, newVal);
1515 }
1516 setMiscRegNoEffect(MISCREG_PAR, newVal);
1517 return;
1518 }
1519 case MISCREG_TTBCR:
1520 {
1521 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1522 const uint32_t ones = (uint32_t)(-1);
1523 TTBCR ttbcrMask = 0;
1524 TTBCR ttbcrNew = newVal;
1525
1526 // ARM DDI 0406C.b, ARMv7-32
1527 ttbcrMask.n = ones; // T0SZ
1528 if (haveSecurity) {
1529 ttbcrMask.pd0 = ones;
1530 ttbcrMask.pd1 = ones;
1531 }
1532 ttbcrMask.epd0 = ones;
1533 ttbcrMask.irgn0 = ones;
1534 ttbcrMask.orgn0 = ones;
1535 ttbcrMask.sh0 = ones;
1536 ttbcrMask.ps = ones; // T1SZ
1537 ttbcrMask.a1 = ones;
1538 ttbcrMask.epd1 = ones;
1539 ttbcrMask.irgn1 = ones;
1540 ttbcrMask.orgn1 = ones;
1541 ttbcrMask.sh1 = ones;
1542 if (haveLPAE)
1543 ttbcrMask.eae = ones;
1544
1545 if (haveLPAE && ttbcrNew.eae) {
1546 newVal = newVal & ttbcrMask;
1547 } else {
1548 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1549 }
1550 }
1551 M5_FALLTHROUGH;
1552 case MISCREG_TTBR0:
1553 case MISCREG_TTBR1:
1554 {
1555 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1556 if (haveLPAE) {
1557 if (ttbcr.eae) {
1558 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1559 // ARMv8 AArch32 bit 63-56 only
1560 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1561 newVal = (newVal & (~ttbrMask));
1562 }
1563 }
1564 }
1565 M5_FALLTHROUGH;
1566 case MISCREG_SCTLR_EL1:
1567 {
1568 getITBPtr(tc)->invalidateMiscReg();
1569 getDTBPtr(tc)->invalidateMiscReg();
1570 setMiscRegNoEffect(misc_reg, newVal);
1571 }
1572 M5_FALLTHROUGH;
1573 case MISCREG_CONTEXTIDR:
1574 case MISCREG_PRRR:
1575 case MISCREG_NMRR:
1576 case MISCREG_MAIR0:
1577 case MISCREG_MAIR1:
1578 case MISCREG_DACR:
1579 case MISCREG_VTTBR:
1580 case MISCREG_SCR_EL3:
1581 case MISCREG_HCR_EL2:
1582 case MISCREG_TCR_EL1:
1583 case MISCREG_TCR_EL2:
1584 case MISCREG_TCR_EL3:
1585 case MISCREG_SCTLR_EL2:
1586 case MISCREG_SCTLR_EL3:
1587 case MISCREG_HSCTLR:
1588 case MISCREG_TTBR0_EL1:
1589 case MISCREG_TTBR1_EL1:
1590 case MISCREG_TTBR0_EL2:
1591 case MISCREG_TTBR0_EL3:
1592 getITBPtr(tc)->invalidateMiscReg();
1593 getDTBPtr(tc)->invalidateMiscReg();
1594 break;
1595 case MISCREG_NZCV:
1596 {
1597 CPSR cpsr = val;
1598
1599 tc->setCCReg(CCREG_NZ, cpsr.nz);
1600 tc->setCCReg(CCREG_C, cpsr.c);
1601 tc->setCCReg(CCREG_V, cpsr.v);
1602 }
1603 break;
1604 case MISCREG_DAIF:
1605 {
1606 CPSR cpsr = miscRegs[MISCREG_CPSR];
1607 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1608 newVal = cpsr;
1609 misc_reg = MISCREG_CPSR;
1610 }
1611 break;
1612 case MISCREG_SP_EL0:
1613 tc->setIntReg(INTREG_SP0, newVal);
1614 break;
1615 case MISCREG_SP_EL1:
1616 tc->setIntReg(INTREG_SP1, newVal);
1617 break;
1618 case MISCREG_SP_EL2:
1619 tc->setIntReg(INTREG_SP2, newVal);
1620 break;
1621 case MISCREG_SPSEL:
1622 {
1623 CPSR cpsr = miscRegs[MISCREG_CPSR];
1624 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1625 newVal = cpsr;
1626 misc_reg = MISCREG_CPSR;
1627 }
1628 break;
1629 case MISCREG_CURRENTEL:
1630 {
1631 CPSR cpsr = miscRegs[MISCREG_CPSR];
1632 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1633 newVal = cpsr;
1634 misc_reg = MISCREG_CPSR;
1635 }
1636 break;
1637 case MISCREG_AT_S1E1R_Xt:
1638 case MISCREG_AT_S1E1W_Xt:
1639 case MISCREG_AT_S1E0R_Xt:
1640 case MISCREG_AT_S1E0W_Xt:
1641 case MISCREG_AT_S1E2R_Xt:
1642 case MISCREG_AT_S1E2W_Xt:
1643 case MISCREG_AT_S12E1R_Xt:
1644 case MISCREG_AT_S12E1W_Xt:
1645 case MISCREG_AT_S12E0R_Xt:
1646 case MISCREG_AT_S12E0W_Xt:
1647 case MISCREG_AT_S1E3R_Xt:
1648 case MISCREG_AT_S1E3W_Xt:
1649 {
1650 RequestPtr req = new Request;
1651 Request::Flags flags = 0;
1652 BaseTLB::Mode mode = BaseTLB::Read;
1653 TLB::ArmTranslationType tranType = TLB::NormalTran;
1654 Fault fault;
1655 switch(misc_reg) {
1656 case MISCREG_AT_S1E1R_Xt:
1657 flags = TLB::MustBeOne;
1658 tranType = TLB::S1E1Tran;
1659 mode = BaseTLB::Read;
1660 break;
1661 case MISCREG_AT_S1E1W_Xt:
1662 flags = TLB::MustBeOne;
1663 tranType = TLB::S1E1Tran;
1664 mode = BaseTLB::Write;
1665 break;
1666 case MISCREG_AT_S1E0R_Xt:
1667 flags = TLB::MustBeOne | TLB::UserMode;
1668 tranType = TLB::S1E0Tran;
1669 mode = BaseTLB::Read;
1670 break;
1671 case MISCREG_AT_S1E0W_Xt:
1672 flags = TLB::MustBeOne | TLB::UserMode;
1673 tranType = TLB::S1E0Tran;
1674 mode = BaseTLB::Write;
1675 break;
1676 case MISCREG_AT_S1E2R_Xt:
1677 flags = TLB::MustBeOne;
1678 tranType = TLB::S1E2Tran;
1679 mode = BaseTLB::Read;
1680 break;
1681 case MISCREG_AT_S1E2W_Xt:
1682 flags = TLB::MustBeOne;
1683 tranType = TLB::S1E2Tran;
1684 mode = BaseTLB::Write;
1685 break;
1686 case MISCREG_AT_S12E0R_Xt:
1687 flags = TLB::MustBeOne | TLB::UserMode;
1688 tranType = TLB::S12E0Tran;
1689 mode = BaseTLB::Read;
1690 break;
1691 case MISCREG_AT_S12E0W_Xt:
1692 flags = TLB::MustBeOne | TLB::UserMode;
1693 tranType = TLB::S12E0Tran;
1694 mode = BaseTLB::Write;
1695 break;
1696 case MISCREG_AT_S12E1R_Xt:
1697 flags = TLB::MustBeOne;
1698 tranType = TLB::S12E1Tran;
1699 mode = BaseTLB::Read;
1700 break;
1701 case MISCREG_AT_S12E1W_Xt:
1702 flags = TLB::MustBeOne;
1703 tranType = TLB::S12E1Tran;
1704 mode = BaseTLB::Write;
1705 break;
1706 case MISCREG_AT_S1E3R_Xt:
1707 flags = TLB::MustBeOne;
1708 tranType = TLB::S1E3Tran;
1709 mode = BaseTLB::Read;
1710 break;
1711 case MISCREG_AT_S1E3W_Xt:
1712 flags = TLB::MustBeOne;
1713 tranType = TLB::S1E3Tran;
1714 mode = BaseTLB::Write;
1715 break;
1716 }
1717 // If we're in timing mode then doing the translation in
1718 // functional mode then we're slightly distorting performance
1719 // results obtained from simulations. The translation should be
1720 // done in the same mode the core is running in. NOTE: This
1721 // can't be an atomic translation because that causes problems
1722 // with unexpected atomic snoop requests.
1723 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1724 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1725 tc->pcState().pc());
1726 req->setContext(tc->contextId());
1727 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1728 tranType);
1729
1730 MiscReg newVal;
1731 if (fault == NoFault) {
1732 Addr paddr = req->getPaddr();
1733 uint64_t attr = getDTBPtr(tc)->getAttr();
1734 uint64_t attr1 = attr >> 56;
1735 if (!attr1 || attr1 ==0x44) {
1736 attr |= 0x100;
1737 attr &= ~ uint64_t(0x80);
1738 }
1739 newVal = (paddr & mask(47, 12)) | attr;
1740 DPRINTF(MiscRegs,
1741 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1742 val, newVal);
1743 } else {
1744 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1745 armFault->update(tc);
1746 // Set fault bit and FSR
1747 FSR fsr = armFault->getFsr(tc);
1748
1749 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1750 if (cpsr.width) { // AArch32
1751 newVal = ((fsr >> 9) & 1) << 11;
1752 // rearrange fault status
1753 newVal |= ((fsr >> 0) & 0x3f) << 1;
1754 newVal |= 0x1; // F bit
1755 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1756 newVal |= armFault->isStage2() ? 0x200 : 0;
1757 } else { // AArch64
1758 newVal = 1; // F bit
1759 newVal |= fsr << 1; // FST
1760 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1761 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1762 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1763 newVal |= 1 << 11; // RES1
1764 }
1765 DPRINTF(MiscRegs,
1766 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1767 val, fsr, newVal);
1768 }
1769 delete req;
1770 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1771 return;
1772 }
1773 case MISCREG_SPSR_EL3:
1774 case MISCREG_SPSR_EL2:
1775 case MISCREG_SPSR_EL1:
1776 // Force bits 23:21 to 0
1777 newVal = val & ~(0x7 << 21);
1778 break;
1779 case MISCREG_L2CTLR:
1780 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1781 miscRegName[misc_reg], uint32_t(val));
1782 break;
1783
1784 // Generic Timer registers
1785 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1786 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1787 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1788 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1789 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1790 break;
1791 }
1792 }
1793 setMiscRegNoEffect(misc_reg, newVal);
1794}
1795
1796void
1797ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1798 bool secure_lookup, uint8_t target_el)
1799{
1800 if (!haveLargeAsid64)
1801 asid &= mask(8);
1802 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1803 System *sys = tc->getSystemPtr();
1804 for (int x = 0; x < sys->numContexts(); x++) {
1805 ThreadContext *oc = sys->getThreadContext(x);
1806 getITBPtr(oc)->flushMvaAsid(va, asid,
1807 secure_lookup, target_el);
1808 getDTBPtr(oc)->flushMvaAsid(va, asid,
1809 secure_lookup, target_el);
1810
1811 CheckerCPU *checker = oc->getCheckerCpuPtr();
1812 if (checker) {
1813 getITBPtr(checker)->flushMvaAsid(
1814 va, asid, secure_lookup, target_el);
1815 getDTBPtr(checker)->flushMvaAsid(
1816 va, asid, secure_lookup, target_el);
1817 }
1818 }
1819}
1820
1821void
1822ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1823{
1824 System *sys = tc->getSystemPtr();
1825 for (int x = 0; x < sys->numContexts(); x++) {
1826 ThreadContext *oc = sys->getThreadContext(x);
1827 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1828 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1829
1830 // If CheckerCPU is connected, need to notify it of a flush
1831 CheckerCPU *checker = oc->getCheckerCpuPtr();
1832 if (checker) {
1833 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1834 target_el);
1835 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1836 target_el);
1837 }
1838 }
1839}
1840
1841void
1842ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1843{
1844 System *sys = tc->getSystemPtr();
1845 for (int x = 0; x < sys->numContexts(); x++) {
1846 ThreadContext *oc = sys->getThreadContext(x);
1847 getITBPtr(oc)->flushAllNs(hyp, target_el);
1848 getDTBPtr(oc)->flushAllNs(hyp, target_el);
1849
1850 CheckerCPU *checker = oc->getCheckerCpuPtr();
1851 if (checker) {
1852 getITBPtr(checker)->flushAllNs(hyp, target_el);
1853 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1854 }
1855 }
1856}
1857
1858void
1859ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1860 uint8_t target_el)
1861{
1862 System *sys = tc->getSystemPtr();
1863 for (int x = 0; x < sys->numContexts(); x++) {
1864 ThreadContext *oc = sys->getThreadContext(x);
1865 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
1866 secure_lookup, hyp, target_el);
1867 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
1868 secure_lookup, hyp, target_el);
1869
1870 CheckerCPU *checker = oc->getCheckerCpuPtr();
1871 if (checker) {
1872 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1873 secure_lookup, hyp, target_el);
1874 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1875 secure_lookup, hyp, target_el);
1876 }
1877 }
1878}
1879
| 1347 return;
1348 case MISCREG_ACTLR:
1349 warn("Not doing anything for write of miscreg ACTLR\n");
1350 break;
1351
1352 case MISCREG_PMXEVTYPER_PMCCFILTR:
1353 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1354 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1355 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1356 pmu->setMiscReg(misc_reg, newVal);
1357 break;
1358
1359
1360 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1361 {
1362 HSTR hstrMask = 0;
1363 hstrMask.tjdbx = 1;
1364 newVal &= ~((uint32_t) hstrMask);
1365 break;
1366 }
1367 case MISCREG_HCPTR:
1368 {
1369 // If a CP bit in NSACR is 0 then the corresponding bit in
1370 // HCPTR is RAO/WI. Same applies to NSASEDIS
1371 secure_lookup = haveSecurity &&
1372 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1373 readMiscRegNoEffect(MISCREG_CPSR));
1374 if (!secure_lookup) {
1375 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1376 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1377 newVal = (newVal & ~mask) | (oldValue & mask);
1378 }
1379 break;
1380 }
1381 case MISCREG_HDFAR: // alias for secure DFAR
1382 misc_reg = MISCREG_DFAR_S;
1383 break;
1384 case MISCREG_HIFAR: // alias for secure IFAR
1385 misc_reg = MISCREG_IFAR_S;
1386 break;
1387 case MISCREG_ATS1CPR:
1388 case MISCREG_ATS1CPW:
1389 case MISCREG_ATS1CUR:
1390 case MISCREG_ATS1CUW:
1391 case MISCREG_ATS12NSOPR:
1392 case MISCREG_ATS12NSOPW:
1393 case MISCREG_ATS12NSOUR:
1394 case MISCREG_ATS12NSOUW:
1395 case MISCREG_ATS1HR:
1396 case MISCREG_ATS1HW:
1397 {
1398 Request::Flags flags = 0;
1399 BaseTLB::Mode mode = BaseTLB::Read;
1400 TLB::ArmTranslationType tranType = TLB::NormalTran;
1401 Fault fault;
1402 switch(misc_reg) {
1403 case MISCREG_ATS1CPR:
1404 flags = TLB::MustBeOne;
1405 tranType = TLB::S1CTran;
1406 mode = BaseTLB::Read;
1407 break;
1408 case MISCREG_ATS1CPW:
1409 flags = TLB::MustBeOne;
1410 tranType = TLB::S1CTran;
1411 mode = BaseTLB::Write;
1412 break;
1413 case MISCREG_ATS1CUR:
1414 flags = TLB::MustBeOne | TLB::UserMode;
1415 tranType = TLB::S1CTran;
1416 mode = BaseTLB::Read;
1417 break;
1418 case MISCREG_ATS1CUW:
1419 flags = TLB::MustBeOne | TLB::UserMode;
1420 tranType = TLB::S1CTran;
1421 mode = BaseTLB::Write;
1422 break;
1423 case MISCREG_ATS12NSOPR:
1424 if (!haveSecurity)
1425 panic("Security Extensions required for ATS12NSOPR");
1426 flags = TLB::MustBeOne;
1427 tranType = TLB::S1S2NsTran;
1428 mode = BaseTLB::Read;
1429 break;
1430 case MISCREG_ATS12NSOPW:
1431 if (!haveSecurity)
1432 panic("Security Extensions required for ATS12NSOPW");
1433 flags = TLB::MustBeOne;
1434 tranType = TLB::S1S2NsTran;
1435 mode = BaseTLB::Write;
1436 break;
1437 case MISCREG_ATS12NSOUR:
1438 if (!haveSecurity)
1439 panic("Security Extensions required for ATS12NSOUR");
1440 flags = TLB::MustBeOne | TLB::UserMode;
1441 tranType = TLB::S1S2NsTran;
1442 mode = BaseTLB::Read;
1443 break;
1444 case MISCREG_ATS12NSOUW:
1445 if (!haveSecurity)
1446 panic("Security Extensions required for ATS12NSOUW");
1447 flags = TLB::MustBeOne | TLB::UserMode;
1448 tranType = TLB::S1S2NsTran;
1449 mode = BaseTLB::Write;
1450 break;
1451 case MISCREG_ATS1HR: // only really useful from secure mode.
1452 flags = TLB::MustBeOne;
1453 tranType = TLB::HypMode;
1454 mode = BaseTLB::Read;
1455 break;
1456 case MISCREG_ATS1HW:
1457 flags = TLB::MustBeOne;
1458 tranType = TLB::HypMode;
1459 mode = BaseTLB::Write;
1460 break;
1461 }
1462 // If we're in timing mode then doing the translation in
1463 // functional mode then we're slightly distorting performance
1464 // results obtained from simulations. The translation should be
1465 // done in the same mode the core is running in. NOTE: This
1466 // can't be an atomic translation because that causes problems
1467 // with unexpected atomic snoop requests.
1468 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1469 Request req(0, val, 0, flags, Request::funcMasterId,
1470 tc->pcState().pc(), tc->contextId());
1471 fault = getDTBPtr(tc)->translateFunctional(
1472 &req, tc, mode, tranType);
1473 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1474 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1475
1476 MiscReg newVal;
1477 if (fault == NoFault) {
1478 Addr paddr = req.getPaddr();
1479 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1480 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1481 newVal = (paddr & mask(39, 12)) |
1482 (getDTBPtr(tc)->getAttr());
1483 } else {
1484 newVal = (paddr & 0xfffff000) |
1485 (getDTBPtr(tc)->getAttr());
1486 }
1487 DPRINTF(MiscRegs,
1488 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1489 val, newVal);
1490 } else {
1491 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1492 armFault->update(tc);
1493 // Set fault bit and FSR
1494 FSR fsr = armFault->getFsr(tc);
1495
1496 newVal = ((fsr >> 9) & 1) << 11;
1497 if (newVal) {
1498 // LPAE - rearange fault status
1499 newVal |= ((fsr >> 0) & 0x3f) << 1;
1500 } else {
1501 // VMSA - rearange fault status
1502 newVal |= ((fsr >> 0) & 0xf) << 1;
1503 newVal |= ((fsr >> 10) & 0x1) << 5;
1504 newVal |= ((fsr >> 12) & 0x1) << 6;
1505 }
1506 newVal |= 0x1; // F bit
1507 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1508 newVal |= armFault->isStage2() ? 0x200 : 0;
1509 DPRINTF(MiscRegs,
1510 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1511 val, fsr, newVal);
1512 }
1513 setMiscRegNoEffect(MISCREG_PAR, newVal);
1514 return;
1515 }
1516 case MISCREG_TTBCR:
1517 {
1518 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1519 const uint32_t ones = (uint32_t)(-1);
1520 TTBCR ttbcrMask = 0;
1521 TTBCR ttbcrNew = newVal;
1522
1523 // ARM DDI 0406C.b, ARMv7-32
1524 ttbcrMask.n = ones; // T0SZ
1525 if (haveSecurity) {
1526 ttbcrMask.pd0 = ones;
1527 ttbcrMask.pd1 = ones;
1528 }
1529 ttbcrMask.epd0 = ones;
1530 ttbcrMask.irgn0 = ones;
1531 ttbcrMask.orgn0 = ones;
1532 ttbcrMask.sh0 = ones;
1533 ttbcrMask.ps = ones; // T1SZ
1534 ttbcrMask.a1 = ones;
1535 ttbcrMask.epd1 = ones;
1536 ttbcrMask.irgn1 = ones;
1537 ttbcrMask.orgn1 = ones;
1538 ttbcrMask.sh1 = ones;
1539 if (haveLPAE)
1540 ttbcrMask.eae = ones;
1541
1542 if (haveLPAE && ttbcrNew.eae) {
1543 newVal = newVal & ttbcrMask;
1544 } else {
1545 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1546 }
1547 }
1548 M5_FALLTHROUGH;
1549 case MISCREG_TTBR0:
1550 case MISCREG_TTBR1:
1551 {
1552 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1553 if (haveLPAE) {
1554 if (ttbcr.eae) {
1555 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1556 // ARMv8 AArch32 bit 63-56 only
1557 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1558 newVal = (newVal & (~ttbrMask));
1559 }
1560 }
1561 }
1562 M5_FALLTHROUGH;
1563 case MISCREG_SCTLR_EL1:
1564 {
1565 getITBPtr(tc)->invalidateMiscReg();
1566 getDTBPtr(tc)->invalidateMiscReg();
1567 setMiscRegNoEffect(misc_reg, newVal);
1568 }
1569 M5_FALLTHROUGH;
1570 case MISCREG_CONTEXTIDR:
1571 case MISCREG_PRRR:
1572 case MISCREG_NMRR:
1573 case MISCREG_MAIR0:
1574 case MISCREG_MAIR1:
1575 case MISCREG_DACR:
1576 case MISCREG_VTTBR:
1577 case MISCREG_SCR_EL3:
1578 case MISCREG_HCR_EL2:
1579 case MISCREG_TCR_EL1:
1580 case MISCREG_TCR_EL2:
1581 case MISCREG_TCR_EL3:
1582 case MISCREG_SCTLR_EL2:
1583 case MISCREG_SCTLR_EL3:
1584 case MISCREG_HSCTLR:
1585 case MISCREG_TTBR0_EL1:
1586 case MISCREG_TTBR1_EL1:
1587 case MISCREG_TTBR0_EL2:
1588 case MISCREG_TTBR0_EL3:
1589 getITBPtr(tc)->invalidateMiscReg();
1590 getDTBPtr(tc)->invalidateMiscReg();
1591 break;
1592 case MISCREG_NZCV:
1593 {
1594 CPSR cpsr = val;
1595
1596 tc->setCCReg(CCREG_NZ, cpsr.nz);
1597 tc->setCCReg(CCREG_C, cpsr.c);
1598 tc->setCCReg(CCREG_V, cpsr.v);
1599 }
1600 break;
1601 case MISCREG_DAIF:
1602 {
1603 CPSR cpsr = miscRegs[MISCREG_CPSR];
1604 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1605 newVal = cpsr;
1606 misc_reg = MISCREG_CPSR;
1607 }
1608 break;
1609 case MISCREG_SP_EL0:
1610 tc->setIntReg(INTREG_SP0, newVal);
1611 break;
1612 case MISCREG_SP_EL1:
1613 tc->setIntReg(INTREG_SP1, newVal);
1614 break;
1615 case MISCREG_SP_EL2:
1616 tc->setIntReg(INTREG_SP2, newVal);
1617 break;
1618 case MISCREG_SPSEL:
1619 {
1620 CPSR cpsr = miscRegs[MISCREG_CPSR];
1621 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1622 newVal = cpsr;
1623 misc_reg = MISCREG_CPSR;
1624 }
1625 break;
1626 case MISCREG_CURRENTEL:
1627 {
1628 CPSR cpsr = miscRegs[MISCREG_CPSR];
1629 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1630 newVal = cpsr;
1631 misc_reg = MISCREG_CPSR;
1632 }
1633 break;
1634 case MISCREG_AT_S1E1R_Xt:
1635 case MISCREG_AT_S1E1W_Xt:
1636 case MISCREG_AT_S1E0R_Xt:
1637 case MISCREG_AT_S1E0W_Xt:
1638 case MISCREG_AT_S1E2R_Xt:
1639 case MISCREG_AT_S1E2W_Xt:
1640 case MISCREG_AT_S12E1R_Xt:
1641 case MISCREG_AT_S12E1W_Xt:
1642 case MISCREG_AT_S12E0R_Xt:
1643 case MISCREG_AT_S12E0W_Xt:
1644 case MISCREG_AT_S1E3R_Xt:
1645 case MISCREG_AT_S1E3W_Xt:
1646 {
1647 RequestPtr req = new Request;
1648 Request::Flags flags = 0;
1649 BaseTLB::Mode mode = BaseTLB::Read;
1650 TLB::ArmTranslationType tranType = TLB::NormalTran;
1651 Fault fault;
1652 switch(misc_reg) {
1653 case MISCREG_AT_S1E1R_Xt:
1654 flags = TLB::MustBeOne;
1655 tranType = TLB::S1E1Tran;
1656 mode = BaseTLB::Read;
1657 break;
1658 case MISCREG_AT_S1E1W_Xt:
1659 flags = TLB::MustBeOne;
1660 tranType = TLB::S1E1Tran;
1661 mode = BaseTLB::Write;
1662 break;
1663 case MISCREG_AT_S1E0R_Xt:
1664 flags = TLB::MustBeOne | TLB::UserMode;
1665 tranType = TLB::S1E0Tran;
1666 mode = BaseTLB::Read;
1667 break;
1668 case MISCREG_AT_S1E0W_Xt:
1669 flags = TLB::MustBeOne | TLB::UserMode;
1670 tranType = TLB::S1E0Tran;
1671 mode = BaseTLB::Write;
1672 break;
1673 case MISCREG_AT_S1E2R_Xt:
1674 flags = TLB::MustBeOne;
1675 tranType = TLB::S1E2Tran;
1676 mode = BaseTLB::Read;
1677 break;
1678 case MISCREG_AT_S1E2W_Xt:
1679 flags = TLB::MustBeOne;
1680 tranType = TLB::S1E2Tran;
1681 mode = BaseTLB::Write;
1682 break;
1683 case MISCREG_AT_S12E0R_Xt:
1684 flags = TLB::MustBeOne | TLB::UserMode;
1685 tranType = TLB::S12E0Tran;
1686 mode = BaseTLB::Read;
1687 break;
1688 case MISCREG_AT_S12E0W_Xt:
1689 flags = TLB::MustBeOne | TLB::UserMode;
1690 tranType = TLB::S12E0Tran;
1691 mode = BaseTLB::Write;
1692 break;
1693 case MISCREG_AT_S12E1R_Xt:
1694 flags = TLB::MustBeOne;
1695 tranType = TLB::S12E1Tran;
1696 mode = BaseTLB::Read;
1697 break;
1698 case MISCREG_AT_S12E1W_Xt:
1699 flags = TLB::MustBeOne;
1700 tranType = TLB::S12E1Tran;
1701 mode = BaseTLB::Write;
1702 break;
1703 case MISCREG_AT_S1E3R_Xt:
1704 flags = TLB::MustBeOne;
1705 tranType = TLB::S1E3Tran;
1706 mode = BaseTLB::Read;
1707 break;
1708 case MISCREG_AT_S1E3W_Xt:
1709 flags = TLB::MustBeOne;
1710 tranType = TLB::S1E3Tran;
1711 mode = BaseTLB::Write;
1712 break;
1713 }
1714 // If we're in timing mode then doing the translation in
1715 // functional mode then we're slightly distorting performance
1716 // results obtained from simulations. The translation should be
1717 // done in the same mode the core is running in. NOTE: This
1718 // can't be an atomic translation because that causes problems
1719 // with unexpected atomic snoop requests.
1720 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1721 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1722 tc->pcState().pc());
1723 req->setContext(tc->contextId());
1724 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1725 tranType);
1726
1727 MiscReg newVal;
1728 if (fault == NoFault) {
1729 Addr paddr = req->getPaddr();
1730 uint64_t attr = getDTBPtr(tc)->getAttr();
1731 uint64_t attr1 = attr >> 56;
1732 if (!attr1 || attr1 ==0x44) {
1733 attr |= 0x100;
1734 attr &= ~ uint64_t(0x80);
1735 }
1736 newVal = (paddr & mask(47, 12)) | attr;
1737 DPRINTF(MiscRegs,
1738 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1739 val, newVal);
1740 } else {
1741 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1742 armFault->update(tc);
1743 // Set fault bit and FSR
1744 FSR fsr = armFault->getFsr(tc);
1745
1746 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1747 if (cpsr.width) { // AArch32
1748 newVal = ((fsr >> 9) & 1) << 11;
1749 // rearrange fault status
1750 newVal |= ((fsr >> 0) & 0x3f) << 1;
1751 newVal |= 0x1; // F bit
1752 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1753 newVal |= armFault->isStage2() ? 0x200 : 0;
1754 } else { // AArch64
1755 newVal = 1; // F bit
1756 newVal |= fsr << 1; // FST
1757 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1758 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1759 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1760 newVal |= 1 << 11; // RES1
1761 }
1762 DPRINTF(MiscRegs,
1763 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1764 val, fsr, newVal);
1765 }
1766 delete req;
1767 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1768 return;
1769 }
1770 case MISCREG_SPSR_EL3:
1771 case MISCREG_SPSR_EL2:
1772 case MISCREG_SPSR_EL1:
1773 // Force bits 23:21 to 0
1774 newVal = val & ~(0x7 << 21);
1775 break;
1776 case MISCREG_L2CTLR:
1777 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1778 miscRegName[misc_reg], uint32_t(val));
1779 break;
1780
1781 // Generic Timer registers
1782 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1783 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1784 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1785 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1786 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1787 break;
1788 }
1789 }
1790 setMiscRegNoEffect(misc_reg, newVal);
1791}
1792
1793void
1794ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1795 bool secure_lookup, uint8_t target_el)
1796{
1797 if (!haveLargeAsid64)
1798 asid &= mask(8);
1799 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1800 System *sys = tc->getSystemPtr();
1801 for (int x = 0; x < sys->numContexts(); x++) {
1802 ThreadContext *oc = sys->getThreadContext(x);
1803 getITBPtr(oc)->flushMvaAsid(va, asid,
1804 secure_lookup, target_el);
1805 getDTBPtr(oc)->flushMvaAsid(va, asid,
1806 secure_lookup, target_el);
1807
1808 CheckerCPU *checker = oc->getCheckerCpuPtr();
1809 if (checker) {
1810 getITBPtr(checker)->flushMvaAsid(
1811 va, asid, secure_lookup, target_el);
1812 getDTBPtr(checker)->flushMvaAsid(
1813 va, asid, secure_lookup, target_el);
1814 }
1815 }
1816}
1817
1818void
1819ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1820{
1821 System *sys = tc->getSystemPtr();
1822 for (int x = 0; x < sys->numContexts(); x++) {
1823 ThreadContext *oc = sys->getThreadContext(x);
1824 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1825 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1826
1827 // If CheckerCPU is connected, need to notify it of a flush
1828 CheckerCPU *checker = oc->getCheckerCpuPtr();
1829 if (checker) {
1830 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1831 target_el);
1832 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1833 target_el);
1834 }
1835 }
1836}
1837
1838void
1839ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1840{
1841 System *sys = tc->getSystemPtr();
1842 for (int x = 0; x < sys->numContexts(); x++) {
1843 ThreadContext *oc = sys->getThreadContext(x);
1844 getITBPtr(oc)->flushAllNs(hyp, target_el);
1845 getDTBPtr(oc)->flushAllNs(hyp, target_el);
1846
1847 CheckerCPU *checker = oc->getCheckerCpuPtr();
1848 if (checker) {
1849 getITBPtr(checker)->flushAllNs(hyp, target_el);
1850 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1851 }
1852 }
1853}
1854
1855void
1856ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1857 uint8_t target_el)
1858{
1859 System *sys = tc->getSystemPtr();
1860 for (int x = 0; x < sys->numContexts(); x++) {
1861 ThreadContext *oc = sys->getThreadContext(x);
1862 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
1863 secure_lookup, hyp, target_el);
1864 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
1865 secure_lookup, hyp, target_el);
1866
1867 CheckerCPU *checker = oc->getCheckerCpuPtr();
1868 if (checker) {
1869 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1870 secure_lookup, hyp, target_el);
1871 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1872 secure_lookup, hyp, target_el);
1873 }
1874 }
1875}
1876
|
| 1877void
1878ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
1879 uint8_t target_el)
1880{
1881 System *sys = tc->getSystemPtr();
1882 for (auto x = 0; x < sys->numContexts(); x++) {
1883 tc = sys->getThreadContext(x);
1884 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1885 getITBPtr(tc)->flushIpaVmid(ipa,
1886 secure_lookup, false, target_el);
1887 getDTBPtr(tc)->flushIpaVmid(ipa,
1888 secure_lookup, false, target_el);
1889
1890 CheckerCPU *checker = tc->getCheckerCpuPtr();
1891 if (checker) {
1892 getITBPtr(checker)->flushIpaVmid(ipa,
1893 secure_lookup, false, target_el);
1894 getDTBPtr(checker)->flushIpaVmid(ipa,
1895 secure_lookup, false, target_el);
1896 }
1897 }
1898}
1899
|
1880BaseISADevice &
1881ISA::getGenericTimer(ThreadContext *tc)
1882{
1883 // We only need to create an ISA interface the first time we try
1884 // to access the timer.
1885 if (timer)
1886 return *timer.get();
1887
1888 assert(system);
1889 GenericTimer *generic_timer(system->getGenericTimer());
1890 if (!generic_timer) {
1891 panic("Trying to get a generic timer from a system that hasn't "
1892 "been configured to use a generic timer.\n");
1893 }
1894
1895 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1896 return *timer.get();
1897}
1898
1899}
1900
1901ArmISA::ISA *
1902ArmISAParams::create()
1903{
1904 return new ArmISA::ISA(this);
1905}
| 1900BaseISADevice &
1901ISA::getGenericTimer(ThreadContext *tc)
1902{
1903 // We only need to create an ISA interface the first time we try
1904 // to access the timer.
1905 if (timer)
1906 return *timer.get();
1907
1908 assert(system);
1909 GenericTimer *generic_timer(system->getGenericTimer());
1910 if (!generic_timer) {
1911 panic("Trying to get a generic timer from a system that hasn't "
1912 "been configured to use a generic timer.\n");
1913 }
1914
1915 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1916 return *timer.get();
1917}
1918
1919}
1920
1921ArmISA::ISA *
1922ArmISAParams::create()
1923{
1924 return new ArmISA::ISA(this);
1925}
|