1/*
| 1/*
|
2 * Copyright (c) 2010-2013 ARM Limited
| 2 * Copyright (c) 2010-2014 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/system.hh"
43#include "cpu/checker/cpu.hh"
44#include "debug/Arm.hh"
45#include "debug/MiscRegs.hh"
46#include "params/ArmISA.hh"
47#include "sim/faults.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51namespace ArmISA
52{
53
54
55/**
56 * Some registers aliase with others, and therefore need to be translated.
57 * For each entry:
58 * The first value is the misc register that is to be looked up
59 * the second value is the lower part of the translation
60 * the third the upper part
61 */
62const struct ISA::MiscRegInitializerEntry
63 ISA::MiscRegSwitch[miscRegTranslateMax] = {
64 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}},
65 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}},
66 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
67 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}},
68 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
69 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
70 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
71 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}},
72 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
73 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
74 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
75 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}},
76 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}},
77 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
78 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
79 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}},
80 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
81 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
82 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}},
83 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}},
84 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
85 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
86 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
87 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}},
88 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
89 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
90 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}},
91 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}},
92 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
93 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}},
94 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}},
95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
96 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}},
97 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}},
98 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}},
99 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}},
100 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
101 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}},
102 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
103 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}},
104 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}},
105 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}},
106 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
107 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
108 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}},
109 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}},
110 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}},
111 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
112 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
113 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}},
114 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
115 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
116 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}},
117 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
118 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
119 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
120 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
121};
122
123
124ISA::ISA(Params *p)
125 : SimObject(p), system(NULL), lookUpMiscReg(NUM_MISCREGS, {0,0})
126{
127 SCTLR sctlr;
128 sctlr = 0;
129 miscRegs[MISCREG_SCTLR_RST] = sctlr;
130
131 system = dynamic_cast<ArmSystem *>(p->system);
132 DPRINTFN("ISA system set to: %p %p\n", system, p->system);
133
134 // Cache system-level properties
135 if (FullSystem && system) {
136 haveSecurity = system->haveSecurity();
137 haveLPAE = system->haveLPAE();
138 haveVirtualization = system->haveVirtualization();
139 haveLargeAsid64 = system->haveLargeAsid64();
140 physAddrRange64 = system->physAddrRange64();
141 } else {
142 haveSecurity = haveLPAE = haveVirtualization = false;
143 haveLargeAsid64 = false;
144 physAddrRange64 = 32; // dummy value
145 }
146
147 /** Fill in the miscReg translation table */
148 for (uint32_t i = 0; i < miscRegTranslateMax; i++) {
149 struct MiscRegLUTEntry new_entry;
150
151 uint32_t select = MiscRegSwitch[i].index;
152 new_entry = MiscRegSwitch[i].entry;
153
154 lookUpMiscReg[select] = new_entry;
155 }
156
157 preUnflattenMiscReg();
158
159 clear();
160}
161
162const ArmISAParams *
163ISA::params() const
164{
165 return dynamic_cast<const Params *>(_params);
166}
167
168void
169ISA::clear()
170{
171 const Params *p(params());
172
173 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
174 memset(miscRegs, 0, sizeof(miscRegs));
175
176 // Initialize configurable default values
177 miscRegs[MISCREG_MIDR] = p->midr;
178 miscRegs[MISCREG_MIDR_EL1] = p->midr;
179 miscRegs[MISCREG_VPIDR] = p->midr;
180
181 if (FullSystem && system->highestELIs64()) {
182 // Initialize AArch64 state
183 clear64(p);
184 return;
185 }
186
187 // Initialize AArch32 state...
188
189 CPSR cpsr = 0;
190 cpsr.mode = MODE_USER;
191 miscRegs[MISCREG_CPSR] = cpsr;
192 updateRegMap(cpsr);
193
194 SCTLR sctlr = 0;
195 sctlr.te = (bool) sctlr_rst.te;
196 sctlr.nmfi = (bool) sctlr_rst.nmfi;
197 sctlr.v = (bool) sctlr_rst.v;
198 sctlr.u = 1;
199 sctlr.xp = 1;
200 sctlr.rao2 = 1;
201 sctlr.rao3 = 1;
202 sctlr.rao4 = 0xf; // SCTLR[6:3]
203 sctlr.uci = 1;
204 sctlr.dze = 1;
205 miscRegs[MISCREG_SCTLR_NS] = sctlr;
206 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
207 miscRegs[MISCREG_HCPTR] = 0;
208
209 // Start with an event in the mailbox
210 miscRegs[MISCREG_SEV_MAILBOX] = 1;
211
212 // Separate Instruction and Data TLBs
213 miscRegs[MISCREG_TLBTR] = 1;
214
215 MVFR0 mvfr0 = 0;
216 mvfr0.advSimdRegisters = 2;
217 mvfr0.singlePrecision = 2;
218 mvfr0.doublePrecision = 2;
219 mvfr0.vfpExceptionTrapping = 0;
220 mvfr0.divide = 1;
221 mvfr0.squareRoot = 1;
222 mvfr0.shortVectors = 1;
223 mvfr0.roundingModes = 1;
224 miscRegs[MISCREG_MVFR0] = mvfr0;
225
226 MVFR1 mvfr1 = 0;
227 mvfr1.flushToZero = 1;
228 mvfr1.defaultNaN = 1;
229 mvfr1.advSimdLoadStore = 1;
230 mvfr1.advSimdInteger = 1;
231 mvfr1.advSimdSinglePrecision = 1;
232 mvfr1.advSimdHalfPrecision = 1;
233 mvfr1.vfpHalfPrecision = 1;
234 miscRegs[MISCREG_MVFR1] = mvfr1;
235
236 // Reset values of PRRR and NMRR are implementation dependent
237
238 // @todo: PRRR and NMRR in secure state?
239 miscRegs[MISCREG_PRRR_NS] =
240 (1 << 19) | // 19
241 (0 << 18) | // 18
242 (0 << 17) | // 17
243 (1 << 16) | // 16
244 (2 << 14) | // 15:14
245 (0 << 12) | // 13:12
246 (2 << 10) | // 11:10
247 (2 << 8) | // 9:8
248 (2 << 6) | // 7:6
249 (2 << 4) | // 5:4
250 (1 << 2) | // 3:2
251 0; // 1:0
252 miscRegs[MISCREG_NMRR_NS] =
253 (1 << 30) | // 31:30
254 (0 << 26) | // 27:26
255 (0 << 24) | // 25:24
256 (3 << 22) | // 23:22
257 (2 << 20) | // 21:20
258 (0 << 18) | // 19:18
259 (0 << 16) | // 17:16
260 (1 << 14) | // 15:14
261 (0 << 12) | // 13:12
262 (2 << 10) | // 11:10
263 (0 << 8) | // 9:8
264 (3 << 6) | // 7:6
265 (2 << 4) | // 5:4
266 (0 << 2) | // 3:2
267 0; // 1:0
268
269 miscRegs[MISCREG_CPACR] = 0;
270
271
272 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
273 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
274
275 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
276 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
277 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
278 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
279
280 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
281 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
282 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
283 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
284 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
285 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
286
287 miscRegs[MISCREG_FPSID] = p->fpsid;
288
289 if (haveLPAE) {
290 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
291 ttbcr.eae = 0;
292 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
293 // Enforce consistency with system-level settings
294 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
295 }
296
297 if (haveSecurity) {
298 miscRegs[MISCREG_SCTLR_S] = sctlr;
299 miscRegs[MISCREG_SCR] = 0;
300 miscRegs[MISCREG_VBAR_S] = 0;
301 } else {
302 // we're always non-secure
303 miscRegs[MISCREG_SCR] = 1;
304 }
305
306 //XXX We need to initialize the rest of the state.
307}
308
309void
310ISA::clear64(const ArmISAParams *p)
311{
312 CPSR cpsr = 0;
313 Addr rvbar = system->resetAddr64();
314 switch (system->highestEL()) {
315 // Set initial EL to highest implemented EL using associated stack
316 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
317 // value
318 case EL3:
319 cpsr.mode = MODE_EL3H;
320 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
321 break;
322 case EL2:
323 cpsr.mode = MODE_EL2H;
324 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
325 break;
326 case EL1:
327 cpsr.mode = MODE_EL1H;
328 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
329 break;
330 default:
331 panic("Invalid highest implemented exception level");
332 break;
333 }
334
335 // Initialize rest of CPSR
336 cpsr.daif = 0xf; // Mask all interrupts
337 cpsr.ss = 0;
338 cpsr.il = 0;
339 miscRegs[MISCREG_CPSR] = cpsr;
340 updateRegMap(cpsr);
341
342 // Initialize other control registers
343 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
344 if (haveSecurity) {
345 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
346 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
347 // @todo: uncomment this to enable Virtualization
348 // } else if (haveVirtualization) {
349 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
350 } else {
351 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
352 // Always non-secure
353 miscRegs[MISCREG_SCR_EL3] = 1;
354 }
355
356 // Initialize configurable id registers
357 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
358 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
359 miscRegs[MISCREG_ID_AA64DFR0_EL1] = p->id_aa64dfr0_el1;
360 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
361 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
362 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
363 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
364 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
365 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
366 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
367
368 // Enforce consistency with system-level settings...
369
370 // EL3
371 // (no AArch32/64 interprocessing support for now)
372 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
373 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
374 haveSecurity ? 0x1 : 0x0);
375 // EL2
376 // (no AArch32/64 interprocessing support for now)
377 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
378 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
379 haveVirtualization ? 0x1 : 0x0);
380 // Large ASID support
381 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
382 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
383 haveLargeAsid64 ? 0x2 : 0x0);
384 // Physical address size
385 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
386 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
387 encodePhysAddrRange64(physAddrRange64));
388}
389
390MiscReg
391ISA::readMiscRegNoEffect(int misc_reg) const
392{
393 assert(misc_reg < NumMiscRegs);
394
395 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
396 // registers are left unchanged
397 MiscReg val;
398
399 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR
400 || flat_idx == MISCREG_SCTLR_EL1) {
401 if (flat_idx == MISCREG_SPSR)
402 flat_idx = flattenMiscIndex(MISCREG_SPSR);
403 if (flat_idx == MISCREG_SCTLR_EL1)
404 flat_idx = flattenMiscIndex(MISCREG_SCTLR);
405 val = miscRegs[flat_idx];
406 } else
407 if (lookUpMiscReg[flat_idx].upper > 0)
408 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32))
409 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32));
410 else
411 val = miscRegs[lookUpMiscReg[flat_idx].lower];
412
413 return val;
414}
415
416
417MiscReg
418ISA::readMiscReg(int misc_reg, ThreadContext *tc)
419{
420 CPSR cpsr = 0;
421 PCState pc = 0;
422 SCR scr = 0;
423
424 if (misc_reg == MISCREG_CPSR) {
425 cpsr = miscRegs[misc_reg];
426 pc = tc->pcState();
427 cpsr.j = pc.jazelle() ? 1 : 0;
428 cpsr.t = pc.thumb() ? 1 : 0;
429 return cpsr;
430 }
431
432#ifndef NDEBUG
433 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
434 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
435 warn("Unimplemented system register %s read.\n",
436 miscRegName[misc_reg]);
437 else
438 panic("Unimplemented system register %s read.\n",
439 miscRegName[misc_reg]);
440 }
441#endif
442
443 switch (unflattenMiscReg(misc_reg)) {
444 case MISCREG_HCR:
445 {
446 if (!haveVirtualization)
447 return 0;
448 else
449 return readMiscRegNoEffect(MISCREG_HCR);
450 }
451 case MISCREG_CPACR:
452 {
453 const uint32_t ones = (uint32_t)(-1);
454 CPACR cpacrMask = 0;
455 // Only cp10, cp11, and ase are implemented, nothing else should
456 // be readable? (straight copy from the write code)
457 cpacrMask.cp10 = ones;
458 cpacrMask.cp11 = ones;
459 cpacrMask.asedis = ones;
460
461 // Security Extensions may limit the readability of CPACR
462 if (haveSecurity) {
463 scr = readMiscRegNoEffect(MISCREG_SCR);
464 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
465 if (scr.ns && (cpsr.mode != MODE_MON)) {
466 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
467 // NB: Skipping the full loop, here
468 if (!nsacr.cp10) cpacrMask.cp10 = 0;
469 if (!nsacr.cp11) cpacrMask.cp11 = 0;
470 }
471 }
472 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
473 val &= cpacrMask;
474 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
475 miscRegName[misc_reg], val);
476 return val;
477 }
478 case MISCREG_MPIDR:
479 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
480 scr = readMiscRegNoEffect(MISCREG_SCR);
481 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
482 return getMPIDR(system, tc);
483 } else {
484 return readMiscReg(MISCREG_VMPIDR, tc);
485 }
486 break;
487 case MISCREG_MPIDR_EL1:
488 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
489 return getMPIDR(system, tc) & 0xffffffff;
490 case MISCREG_VMPIDR:
491 // top bit defined as RES1
492 return readMiscRegNoEffect(misc_reg) | 0x80000000;
493 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
494 case MISCREG_ID_DFR0: // not implemented, so alias MIDR
495 case MISCREG_REVIDR: // not implemented, so alias MIDR
496 case MISCREG_MIDR:
497 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
498 scr = readMiscRegNoEffect(MISCREG_SCR);
499 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
500 return readMiscRegNoEffect(misc_reg);
501 } else {
502 return readMiscRegNoEffect(MISCREG_VPIDR);
503 }
504 break;
505 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
506 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
507 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
508 case MISCREG_AIDR: // AUX ID set to 0
509 case MISCREG_TCMTR: // No TCM's
510 return 0;
511
512 case MISCREG_CLIDR:
513 warn_once("The clidr register always reports 0 caches.\n");
514 warn_once("clidr LoUIS field of 0b001 to match current "
515 "ARM implementations.\n");
516 return 0x00200000;
517 case MISCREG_CCSIDR:
518 warn_once("The ccsidr register isn't implemented and "
519 "always reads as 0.\n");
520 break;
521 case MISCREG_CTR:
522 {
523 //all caches have the same line size in gem5
524 //4 byte words in ARM
525 unsigned lineSizeWords =
526 tc->getSystemPtr()->cacheLineSize() / 4;
527 unsigned log2LineSizeWords = 0;
528
529 while (lineSizeWords >>= 1) {
530 ++log2LineSizeWords;
531 }
532
533 CTR ctr = 0;
534 //log2 of minimun i-cache line size (words)
535 ctr.iCacheLineSize = log2LineSizeWords;
536 //b11 - gem5 uses pipt
537 ctr.l1IndexPolicy = 0x3;
538 //log2 of minimum d-cache line size (words)
539 ctr.dCacheLineSize = log2LineSizeWords;
540 //log2 of max reservation size (words)
541 ctr.erg = log2LineSizeWords;
542 //log2 of max writeback size (words)
543 ctr.cwg = log2LineSizeWords;
544 //b100 - gem5 format is ARMv7
545 ctr.format = 0x4;
546
547 return ctr;
548 }
549 case MISCREG_ACTLR:
550 warn("Not doing anything for miscreg ACTLR\n");
551 break;
552 case MISCREG_PMCR:
553 case MISCREG_PMCCNTR:
554 case MISCREG_PMSELR:
555 warn("Not doing anything for read to miscreg %s\n",
556 miscRegName[misc_reg]);
557 break;
558 case MISCREG_CPSR_Q:
559 panic("shouldn't be reading this register seperately\n");
560 case MISCREG_FPSCR_QC:
561 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
562 case MISCREG_FPSCR_EXC:
563 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
564 case MISCREG_FPSR:
565 {
566 const uint32_t ones = (uint32_t)(-1);
567 FPSCR fpscrMask = 0;
568 fpscrMask.ioc = ones;
569 fpscrMask.dzc = ones;
570 fpscrMask.ofc = ones;
571 fpscrMask.ufc = ones;
572 fpscrMask.ixc = ones;
573 fpscrMask.idc = ones;
574 fpscrMask.qc = ones;
575 fpscrMask.v = ones;
576 fpscrMask.c = ones;
577 fpscrMask.z = ones;
578 fpscrMask.n = ones;
579 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
580 }
581 case MISCREG_FPCR:
582 {
583 const uint32_t ones = (uint32_t)(-1);
584 FPSCR fpscrMask = 0;
585 fpscrMask.ioe = ones;
586 fpscrMask.dze = ones;
587 fpscrMask.ofe = ones;
588 fpscrMask.ufe = ones;
589 fpscrMask.ixe = ones;
590 fpscrMask.ide = ones;
591 fpscrMask.len = ones;
592 fpscrMask.stride = ones;
593 fpscrMask.rMode = ones;
594 fpscrMask.fz = ones;
595 fpscrMask.dn = ones;
596 fpscrMask.ahp = ones;
597 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
598 }
599 case MISCREG_NZCV:
600 {
601 CPSR cpsr = 0;
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/system.hh"
43#include "cpu/checker/cpu.hh"
44#include "debug/Arm.hh"
45#include "debug/MiscRegs.hh"
46#include "params/ArmISA.hh"
47#include "sim/faults.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51namespace ArmISA
52{
53
54
55/**
56 * Some registers aliase with others, and therefore need to be translated.
57 * For each entry:
58 * The first value is the misc register that is to be looked up
59 * the second value is the lower part of the translation
60 * the third the upper part
61 */
62const struct ISA::MiscRegInitializerEntry
63 ISA::MiscRegSwitch[miscRegTranslateMax] = {
64 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}},
65 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}},
66 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
67 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}},
68 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
69 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
70 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
71 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}},
72 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
73 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
74 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
75 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}},
76 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}},
77 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
78 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
79 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}},
80 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
81 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
82 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}},
83 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}},
84 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
85 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
86 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
87 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}},
88 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
89 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
90 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}},
91 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}},
92 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
93 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}},
94 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}},
95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
96 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}},
97 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}},
98 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}},
99 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}},
100 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
101 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}},
102 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
103 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}},
104 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}},
105 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}},
106 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
107 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
108 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}},
109 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}},
110 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}},
111 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
112 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
113 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}},
114 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
115 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
116 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}},
117 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
118 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
119 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
120 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
121};
122
123
124ISA::ISA(Params *p)
125 : SimObject(p), system(NULL), lookUpMiscReg(NUM_MISCREGS, {0,0})
126{
127 SCTLR sctlr;
128 sctlr = 0;
129 miscRegs[MISCREG_SCTLR_RST] = sctlr;
130
131 system = dynamic_cast<ArmSystem *>(p->system);
132 DPRINTFN("ISA system set to: %p %p\n", system, p->system);
133
134 // Cache system-level properties
135 if (FullSystem && system) {
136 haveSecurity = system->haveSecurity();
137 haveLPAE = system->haveLPAE();
138 haveVirtualization = system->haveVirtualization();
139 haveLargeAsid64 = system->haveLargeAsid64();
140 physAddrRange64 = system->physAddrRange64();
141 } else {
142 haveSecurity = haveLPAE = haveVirtualization = false;
143 haveLargeAsid64 = false;
144 physAddrRange64 = 32; // dummy value
145 }
146
147 /** Fill in the miscReg translation table */
148 for (uint32_t i = 0; i < miscRegTranslateMax; i++) {
149 struct MiscRegLUTEntry new_entry;
150
151 uint32_t select = MiscRegSwitch[i].index;
152 new_entry = MiscRegSwitch[i].entry;
153
154 lookUpMiscReg[select] = new_entry;
155 }
156
157 preUnflattenMiscReg();
158
159 clear();
160}
161
162const ArmISAParams *
163ISA::params() const
164{
165 return dynamic_cast<const Params *>(_params);
166}
167
168void
169ISA::clear()
170{
171 const Params *p(params());
172
173 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
174 memset(miscRegs, 0, sizeof(miscRegs));
175
176 // Initialize configurable default values
177 miscRegs[MISCREG_MIDR] = p->midr;
178 miscRegs[MISCREG_MIDR_EL1] = p->midr;
179 miscRegs[MISCREG_VPIDR] = p->midr;
180
181 if (FullSystem && system->highestELIs64()) {
182 // Initialize AArch64 state
183 clear64(p);
184 return;
185 }
186
187 // Initialize AArch32 state...
188
189 CPSR cpsr = 0;
190 cpsr.mode = MODE_USER;
191 miscRegs[MISCREG_CPSR] = cpsr;
192 updateRegMap(cpsr);
193
194 SCTLR sctlr = 0;
195 sctlr.te = (bool) sctlr_rst.te;
196 sctlr.nmfi = (bool) sctlr_rst.nmfi;
197 sctlr.v = (bool) sctlr_rst.v;
198 sctlr.u = 1;
199 sctlr.xp = 1;
200 sctlr.rao2 = 1;
201 sctlr.rao3 = 1;
202 sctlr.rao4 = 0xf; // SCTLR[6:3]
203 sctlr.uci = 1;
204 sctlr.dze = 1;
205 miscRegs[MISCREG_SCTLR_NS] = sctlr;
206 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
207 miscRegs[MISCREG_HCPTR] = 0;
208
209 // Start with an event in the mailbox
210 miscRegs[MISCREG_SEV_MAILBOX] = 1;
211
212 // Separate Instruction and Data TLBs
213 miscRegs[MISCREG_TLBTR] = 1;
214
215 MVFR0 mvfr0 = 0;
216 mvfr0.advSimdRegisters = 2;
217 mvfr0.singlePrecision = 2;
218 mvfr0.doublePrecision = 2;
219 mvfr0.vfpExceptionTrapping = 0;
220 mvfr0.divide = 1;
221 mvfr0.squareRoot = 1;
222 mvfr0.shortVectors = 1;
223 mvfr0.roundingModes = 1;
224 miscRegs[MISCREG_MVFR0] = mvfr0;
225
226 MVFR1 mvfr1 = 0;
227 mvfr1.flushToZero = 1;
228 mvfr1.defaultNaN = 1;
229 mvfr1.advSimdLoadStore = 1;
230 mvfr1.advSimdInteger = 1;
231 mvfr1.advSimdSinglePrecision = 1;
232 mvfr1.advSimdHalfPrecision = 1;
233 mvfr1.vfpHalfPrecision = 1;
234 miscRegs[MISCREG_MVFR1] = mvfr1;
235
236 // Reset values of PRRR and NMRR are implementation dependent
237
238 // @todo: PRRR and NMRR in secure state?
239 miscRegs[MISCREG_PRRR_NS] =
240 (1 << 19) | // 19
241 (0 << 18) | // 18
242 (0 << 17) | // 17
243 (1 << 16) | // 16
244 (2 << 14) | // 15:14
245 (0 << 12) | // 13:12
246 (2 << 10) | // 11:10
247 (2 << 8) | // 9:8
248 (2 << 6) | // 7:6
249 (2 << 4) | // 5:4
250 (1 << 2) | // 3:2
251 0; // 1:0
252 miscRegs[MISCREG_NMRR_NS] =
253 (1 << 30) | // 31:30
254 (0 << 26) | // 27:26
255 (0 << 24) | // 25:24
256 (3 << 22) | // 23:22
257 (2 << 20) | // 21:20
258 (0 << 18) | // 19:18
259 (0 << 16) | // 17:16
260 (1 << 14) | // 15:14
261 (0 << 12) | // 13:12
262 (2 << 10) | // 11:10
263 (0 << 8) | // 9:8
264 (3 << 6) | // 7:6
265 (2 << 4) | // 5:4
266 (0 << 2) | // 3:2
267 0; // 1:0
268
269 miscRegs[MISCREG_CPACR] = 0;
270
271
272 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
273 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
274
275 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
276 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
277 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
278 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
279
280 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
281 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
282 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
283 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
284 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
285 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
286
287 miscRegs[MISCREG_FPSID] = p->fpsid;
288
289 if (haveLPAE) {
290 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
291 ttbcr.eae = 0;
292 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
293 // Enforce consistency with system-level settings
294 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
295 }
296
297 if (haveSecurity) {
298 miscRegs[MISCREG_SCTLR_S] = sctlr;
299 miscRegs[MISCREG_SCR] = 0;
300 miscRegs[MISCREG_VBAR_S] = 0;
301 } else {
302 // we're always non-secure
303 miscRegs[MISCREG_SCR] = 1;
304 }
305
306 //XXX We need to initialize the rest of the state.
307}
308
309void
310ISA::clear64(const ArmISAParams *p)
311{
312 CPSR cpsr = 0;
313 Addr rvbar = system->resetAddr64();
314 switch (system->highestEL()) {
315 // Set initial EL to highest implemented EL using associated stack
316 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
317 // value
318 case EL3:
319 cpsr.mode = MODE_EL3H;
320 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
321 break;
322 case EL2:
323 cpsr.mode = MODE_EL2H;
324 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
325 break;
326 case EL1:
327 cpsr.mode = MODE_EL1H;
328 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
329 break;
330 default:
331 panic("Invalid highest implemented exception level");
332 break;
333 }
334
335 // Initialize rest of CPSR
336 cpsr.daif = 0xf; // Mask all interrupts
337 cpsr.ss = 0;
338 cpsr.il = 0;
339 miscRegs[MISCREG_CPSR] = cpsr;
340 updateRegMap(cpsr);
341
342 // Initialize other control registers
343 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
344 if (haveSecurity) {
345 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
346 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
347 // @todo: uncomment this to enable Virtualization
348 // } else if (haveVirtualization) {
349 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
350 } else {
351 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
352 // Always non-secure
353 miscRegs[MISCREG_SCR_EL3] = 1;
354 }
355
356 // Initialize configurable id registers
357 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
358 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
359 miscRegs[MISCREG_ID_AA64DFR0_EL1] = p->id_aa64dfr0_el1;
360 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
361 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
362 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
363 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
364 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
365 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
366 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
367
368 // Enforce consistency with system-level settings...
369
370 // EL3
371 // (no AArch32/64 interprocessing support for now)
372 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
373 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
374 haveSecurity ? 0x1 : 0x0);
375 // EL2
376 // (no AArch32/64 interprocessing support for now)
377 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
378 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
379 haveVirtualization ? 0x1 : 0x0);
380 // Large ASID support
381 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
382 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
383 haveLargeAsid64 ? 0x2 : 0x0);
384 // Physical address size
385 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
386 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
387 encodePhysAddrRange64(physAddrRange64));
388}
389
390MiscReg
391ISA::readMiscRegNoEffect(int misc_reg) const
392{
393 assert(misc_reg < NumMiscRegs);
394
395 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
396 // registers are left unchanged
397 MiscReg val;
398
399 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR
400 || flat_idx == MISCREG_SCTLR_EL1) {
401 if (flat_idx == MISCREG_SPSR)
402 flat_idx = flattenMiscIndex(MISCREG_SPSR);
403 if (flat_idx == MISCREG_SCTLR_EL1)
404 flat_idx = flattenMiscIndex(MISCREG_SCTLR);
405 val = miscRegs[flat_idx];
406 } else
407 if (lookUpMiscReg[flat_idx].upper > 0)
408 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32))
409 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32));
410 else
411 val = miscRegs[lookUpMiscReg[flat_idx].lower];
412
413 return val;
414}
415
416
417MiscReg
418ISA::readMiscReg(int misc_reg, ThreadContext *tc)
419{
420 CPSR cpsr = 0;
421 PCState pc = 0;
422 SCR scr = 0;
423
424 if (misc_reg == MISCREG_CPSR) {
425 cpsr = miscRegs[misc_reg];
426 pc = tc->pcState();
427 cpsr.j = pc.jazelle() ? 1 : 0;
428 cpsr.t = pc.thumb() ? 1 : 0;
429 return cpsr;
430 }
431
432#ifndef NDEBUG
433 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
434 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
435 warn("Unimplemented system register %s read.\n",
436 miscRegName[misc_reg]);
437 else
438 panic("Unimplemented system register %s read.\n",
439 miscRegName[misc_reg]);
440 }
441#endif
442
443 switch (unflattenMiscReg(misc_reg)) {
444 case MISCREG_HCR:
445 {
446 if (!haveVirtualization)
447 return 0;
448 else
449 return readMiscRegNoEffect(MISCREG_HCR);
450 }
451 case MISCREG_CPACR:
452 {
453 const uint32_t ones = (uint32_t)(-1);
454 CPACR cpacrMask = 0;
455 // Only cp10, cp11, and ase are implemented, nothing else should
456 // be readable? (straight copy from the write code)
457 cpacrMask.cp10 = ones;
458 cpacrMask.cp11 = ones;
459 cpacrMask.asedis = ones;
460
461 // Security Extensions may limit the readability of CPACR
462 if (haveSecurity) {
463 scr = readMiscRegNoEffect(MISCREG_SCR);
464 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
465 if (scr.ns && (cpsr.mode != MODE_MON)) {
466 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
467 // NB: Skipping the full loop, here
468 if (!nsacr.cp10) cpacrMask.cp10 = 0;
469 if (!nsacr.cp11) cpacrMask.cp11 = 0;
470 }
471 }
472 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
473 val &= cpacrMask;
474 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
475 miscRegName[misc_reg], val);
476 return val;
477 }
478 case MISCREG_MPIDR:
479 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
480 scr = readMiscRegNoEffect(MISCREG_SCR);
481 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
482 return getMPIDR(system, tc);
483 } else {
484 return readMiscReg(MISCREG_VMPIDR, tc);
485 }
486 break;
487 case MISCREG_MPIDR_EL1:
488 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
489 return getMPIDR(system, tc) & 0xffffffff;
490 case MISCREG_VMPIDR:
491 // top bit defined as RES1
492 return readMiscRegNoEffect(misc_reg) | 0x80000000;
493 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
494 case MISCREG_ID_DFR0: // not implemented, so alias MIDR
495 case MISCREG_REVIDR: // not implemented, so alias MIDR
496 case MISCREG_MIDR:
497 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
498 scr = readMiscRegNoEffect(MISCREG_SCR);
499 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
500 return readMiscRegNoEffect(misc_reg);
501 } else {
502 return readMiscRegNoEffect(MISCREG_VPIDR);
503 }
504 break;
505 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
506 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
507 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
508 case MISCREG_AIDR: // AUX ID set to 0
509 case MISCREG_TCMTR: // No TCM's
510 return 0;
511
512 case MISCREG_CLIDR:
513 warn_once("The clidr register always reports 0 caches.\n");
514 warn_once("clidr LoUIS field of 0b001 to match current "
515 "ARM implementations.\n");
516 return 0x00200000;
517 case MISCREG_CCSIDR:
518 warn_once("The ccsidr register isn't implemented and "
519 "always reads as 0.\n");
520 break;
521 case MISCREG_CTR:
522 {
523 //all caches have the same line size in gem5
524 //4 byte words in ARM
525 unsigned lineSizeWords =
526 tc->getSystemPtr()->cacheLineSize() / 4;
527 unsigned log2LineSizeWords = 0;
528
529 while (lineSizeWords >>= 1) {
530 ++log2LineSizeWords;
531 }
532
533 CTR ctr = 0;
534 //log2 of minimun i-cache line size (words)
535 ctr.iCacheLineSize = log2LineSizeWords;
536 //b11 - gem5 uses pipt
537 ctr.l1IndexPolicy = 0x3;
538 //log2 of minimum d-cache line size (words)
539 ctr.dCacheLineSize = log2LineSizeWords;
540 //log2 of max reservation size (words)
541 ctr.erg = log2LineSizeWords;
542 //log2 of max writeback size (words)
543 ctr.cwg = log2LineSizeWords;
544 //b100 - gem5 format is ARMv7
545 ctr.format = 0x4;
546
547 return ctr;
548 }
549 case MISCREG_ACTLR:
550 warn("Not doing anything for miscreg ACTLR\n");
551 break;
552 case MISCREG_PMCR:
553 case MISCREG_PMCCNTR:
554 case MISCREG_PMSELR:
555 warn("Not doing anything for read to miscreg %s\n",
556 miscRegName[misc_reg]);
557 break;
558 case MISCREG_CPSR_Q:
559 panic("shouldn't be reading this register seperately\n");
560 case MISCREG_FPSCR_QC:
561 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
562 case MISCREG_FPSCR_EXC:
563 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
564 case MISCREG_FPSR:
565 {
566 const uint32_t ones = (uint32_t)(-1);
567 FPSCR fpscrMask = 0;
568 fpscrMask.ioc = ones;
569 fpscrMask.dzc = ones;
570 fpscrMask.ofc = ones;
571 fpscrMask.ufc = ones;
572 fpscrMask.ixc = ones;
573 fpscrMask.idc = ones;
574 fpscrMask.qc = ones;
575 fpscrMask.v = ones;
576 fpscrMask.c = ones;
577 fpscrMask.z = ones;
578 fpscrMask.n = ones;
579 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
580 }
581 case MISCREG_FPCR:
582 {
583 const uint32_t ones = (uint32_t)(-1);
584 FPSCR fpscrMask = 0;
585 fpscrMask.ioe = ones;
586 fpscrMask.dze = ones;
587 fpscrMask.ofe = ones;
588 fpscrMask.ufe = ones;
589 fpscrMask.ixe = ones;
590 fpscrMask.ide = ones;
591 fpscrMask.len = ones;
592 fpscrMask.stride = ones;
593 fpscrMask.rMode = ones;
594 fpscrMask.fz = ones;
595 fpscrMask.dn = ones;
596 fpscrMask.ahp = ones;
597 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
598 }
599 case MISCREG_NZCV:
600 {
601 CPSR cpsr = 0;
|
602 cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
603 cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
604 cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
| 602 cpsr.nz = tc->readCCReg(CCREG_NZ);
603 cpsr.c = tc->readCCReg(CCREG_C);
604 cpsr.v = tc->readCCReg(CCREG_V);
|
605 return cpsr;
606 }
607 case MISCREG_DAIF:
608 {
609 CPSR cpsr = 0;
610 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
611 return cpsr;
612 }
613 case MISCREG_SP_EL0:
614 {
615 return tc->readIntReg(INTREG_SP0);
616 }
617 case MISCREG_SP_EL1:
618 {
619 return tc->readIntReg(INTREG_SP1);
620 }
621 case MISCREG_SP_EL2:
622 {
623 return tc->readIntReg(INTREG_SP2);
624 }
625 case MISCREG_SPSEL:
626 {
627 return miscRegs[MISCREG_CPSR] & 0x1;
628 }
629 case MISCREG_CURRENTEL:
630 {
631 return miscRegs[MISCREG_CPSR] & 0xc;
632 }
633 case MISCREG_L2CTLR:
634 {
635 // mostly unimplemented, just set NumCPUs field from sim and return
636 L2CTLR l2ctlr = 0;
637 // b00:1CPU to b11:4CPUs
638 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
639 return l2ctlr;
640 }
641 case MISCREG_DBGDIDR:
642 /* For now just implement the version number.
643 * Return 0 as we don't support debug architecture yet.
644 */
645 return 0;
646 case MISCREG_DBGDSCRint:
647 return 0;
648 case MISCREG_ISR:
649 return tc->getCpuPtr()->getInterruptController()->getISR(
650 readMiscRegNoEffect(MISCREG_HCR),
651 readMiscRegNoEffect(MISCREG_CPSR),
652 readMiscRegNoEffect(MISCREG_SCR));
653 case MISCREG_ISR_EL1:
654 return tc->getCpuPtr()->getInterruptController()->getISR(
655 readMiscRegNoEffect(MISCREG_HCR_EL2),
656 readMiscRegNoEffect(MISCREG_CPSR),
657 readMiscRegNoEffect(MISCREG_SCR_EL3));
658 case MISCREG_DCZID_EL0:
659 return 0x04; // DC ZVA clear 64-byte chunks
660 case MISCREG_HCPTR:
661 {
662 MiscReg val = readMiscRegNoEffect(misc_reg);
663 // The trap bit associated with CP14 is defined as RAZ
664 val &= ~(1 << 14);
665 // If a CP bit in NSACR is 0 then the corresponding bit in
666 // HCPTR is RAO/WI
667 bool secure_lookup = haveSecurity &&
668 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
669 readMiscRegNoEffect(MISCREG_CPSR));
670 if (!secure_lookup) {
671 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
672 val |= (mask ^ 0x7FFF) & 0xBFFF;
673 }
674 // Set the bits for unimplemented coprocessors to RAO/WI
675 val |= 0x33FF;
676 return (val);
677 }
678 case MISCREG_HDFAR: // alias for secure DFAR
679 return readMiscRegNoEffect(MISCREG_DFAR_S);
680 case MISCREG_HIFAR: // alias for secure IFAR
681 return readMiscRegNoEffect(MISCREG_IFAR_S);
682 case MISCREG_HVBAR: // bottom bits reserved
683 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
684 case MISCREG_SCTLR: // Some bits hardwired
685 // The FI field (bit 21) is common between S/NS versions of the register
686 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
687 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
688 case MISCREG_SCTLR_EL1:
689 // The FI field (bit 21) is common between S/NS versions of the register
690 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
691 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
692 case MISCREG_SCTLR_EL3:
693 // The FI field (bit 21) is common between S/NS versions of the register
694 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
695 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
696 case MISCREG_HSCTLR: // FI comes from SCTLR
697 {
698 uint32_t mask = 1 << 27;
699 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
700 (readMiscRegNoEffect(MISCREG_SCTLR) & mask);
701 }
702 case MISCREG_SCR:
703 {
704 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
705 if (cpsr.width) {
706 return readMiscRegNoEffect(MISCREG_SCR);
707 } else {
708 return readMiscRegNoEffect(MISCREG_SCR_EL3);
709 }
710 }
711 // Generic Timer registers
712 case MISCREG_CNTFRQ:
713 case MISCREG_CNTFRQ_EL0:
714 inform_once("Read CNTFREQ_EL0 frequency\n");
715 return getSystemCounter(tc)->freq();
716 case MISCREG_CNTPCT:
717 case MISCREG_CNTPCT_EL0:
718 return getSystemCounter(tc)->value();
719 case MISCREG_CNTVCT:
720 return getSystemCounter(tc)->value();
721 case MISCREG_CNTVCT_EL0:
722 return getSystemCounter(tc)->value();
723 case MISCREG_CNTP_CVAL:
724 case MISCREG_CNTP_CVAL_EL0:
725 return getArchTimer(tc, tc->cpuId())->compareValue();
726 case MISCREG_CNTP_TVAL:
727 case MISCREG_CNTP_TVAL_EL0:
728 return getArchTimer(tc, tc->cpuId())->timerValue();
729 case MISCREG_CNTP_CTL:
730 case MISCREG_CNTP_CTL_EL0:
731 return getArchTimer(tc, tc->cpuId())->control();
732 // PL1 phys. timer, secure
733 // AArch64
734 // case MISCREG_CNTPS_CVAL_EL1:
735 // case MISCREG_CNTPS_TVAL_EL1:
736 // case MISCREG_CNTPS_CTL_EL1:
737 // PL2 phys. timer, non-secure
738 // AArch32
739 // case MISCREG_CNTHCTL:
740 // case MISCREG_CNTHP_CVAL:
741 // case MISCREG_CNTHP_TVAL:
742 // case MISCREG_CNTHP_CTL:
743 // AArch64
744 // case MISCREG_CNTHCTL_EL2:
745 // case MISCREG_CNTHP_CVAL_EL2:
746 // case MISCREG_CNTHP_TVAL_EL2:
747 // case MISCREG_CNTHP_CTL_EL2:
748 // Virtual timer
749 // AArch32
750 // case MISCREG_CNTV_CVAL:
751 // case MISCREG_CNTV_TVAL:
752 // case MISCREG_CNTV_CTL:
753 // AArch64
754 // case MISCREG_CNTV_CVAL_EL2:
755 // case MISCREG_CNTV_TVAL_EL2:
756 // case MISCREG_CNTV_CTL_EL2:
757 default:
758 break;
759
760 }
761 return readMiscRegNoEffect(misc_reg);
762}
763
764void
765ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
766{
767 assert(misc_reg < NumMiscRegs);
768
769 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
770 // registers are left unchanged
771
772 int flat_idx2 = lookUpMiscReg[flat_idx].upper;
773
774 if (flat_idx2 > 0) {
775 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0);
776 miscRegs[flat_idx2] = bits(val, 63, 32);
777 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
778 misc_reg, flat_idx, flat_idx2, val);
779 } else {
780 if (flat_idx == MISCREG_SPSR)
781 flat_idx = flattenMiscIndex(MISCREG_SPSR);
782 else if (flat_idx == MISCREG_SCTLR_EL1)
783 flat_idx = flattenMiscIndex(MISCREG_SCTLR);
784 else
785 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
786 lookUpMiscReg[flat_idx].lower : flat_idx;
787 miscRegs[flat_idx] = val;
788 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
789 misc_reg, flat_idx, val);
790 }
791}
792
793void
794ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
795{
796
797 MiscReg newVal = val;
798 int x;
799 bool secure_lookup;
800 bool hyp;
801 System *sys;
802 ThreadContext *oc;
803 uint8_t target_el;
804 uint16_t asid;
805 SCR scr;
806
807 if (misc_reg == MISCREG_CPSR) {
808 updateRegMap(val);
809
810
811 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
812 int old_mode = old_cpsr.mode;
813 CPSR cpsr = val;
814 if (old_mode != cpsr.mode) {
815 tc->getITBPtr()->invalidateMiscReg();
816 tc->getDTBPtr()->invalidateMiscReg();
817 }
818
819 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
820 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
821 PCState pc = tc->pcState();
822 pc.nextThumb(cpsr.t);
823 pc.nextJazelle(cpsr.j);
824
825 // Follow slightly different semantics if a CheckerCPU object
826 // is connected
827 CheckerCPU *checker = tc->getCheckerCpuPtr();
828 if (checker) {
829 tc->pcStateNoRecord(pc);
830 } else {
831 tc->pcState(pc);
832 }
833 } else {
834#ifndef NDEBUG
835 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
836 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
837 warn("Unimplemented system register %s write with %#x.\n",
838 miscRegName[misc_reg], val);
839 else
840 panic("Unimplemented system register %s write with %#x.\n",
841 miscRegName[misc_reg], val);
842 }
843#endif
844 switch (unflattenMiscReg(misc_reg)) {
845 case MISCREG_CPACR:
846 {
847
848 const uint32_t ones = (uint32_t)(-1);
849 CPACR cpacrMask = 0;
850 // Only cp10, cp11, and ase are implemented, nothing else should
851 // be writable
852 cpacrMask.cp10 = ones;
853 cpacrMask.cp11 = ones;
854 cpacrMask.asedis = ones;
855
856 // Security Extensions may limit the writability of CPACR
857 if (haveSecurity) {
858 scr = readMiscRegNoEffect(MISCREG_SCR);
859 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
860 if (scr.ns && (cpsr.mode != MODE_MON)) {
861 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
862 // NB: Skipping the full loop, here
863 if (!nsacr.cp10) cpacrMask.cp10 = 0;
864 if (!nsacr.cp11) cpacrMask.cp11 = 0;
865 }
866 }
867
868 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
869 newVal &= cpacrMask;
870 newVal |= old_val & ~cpacrMask;
871 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
872 miscRegName[misc_reg], newVal);
873 }
874 break;
875 case MISCREG_CPACR_EL1:
876 {
877 const uint32_t ones = (uint32_t)(-1);
878 CPACR cpacrMask = 0;
879 cpacrMask.tta = ones;
880 cpacrMask.fpen = ones;
881 newVal &= cpacrMask;
882 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
883 miscRegName[misc_reg], newVal);
884 }
885 break;
886 case MISCREG_CPTR_EL2:
887 {
888 const uint32_t ones = (uint32_t)(-1);
889 CPTR cptrMask = 0;
890 cptrMask.tcpac = ones;
891 cptrMask.tta = ones;
892 cptrMask.tfp = ones;
893 newVal &= cptrMask;
894 cptrMask = 0;
895 cptrMask.res1_13_12_el2 = ones;
896 cptrMask.res1_9_0_el2 = ones;
897 newVal |= cptrMask;
898 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
899 miscRegName[misc_reg], newVal);
900 }
901 break;
902 case MISCREG_CPTR_EL3:
903 {
904 const uint32_t ones = (uint32_t)(-1);
905 CPTR cptrMask = 0;
906 cptrMask.tcpac = ones;
907 cptrMask.tta = ones;
908 cptrMask.tfp = ones;
909 newVal &= cptrMask;
910 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
911 miscRegName[misc_reg], newVal);
912 }
913 break;
914 case MISCREG_CSSELR:
915 warn_once("The csselr register isn't implemented.\n");
916 return;
917
918 case MISCREG_DC_ZVA_Xt:
919 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
920 return;
921
922 case MISCREG_FPSCR:
923 {
924 const uint32_t ones = (uint32_t)(-1);
925 FPSCR fpscrMask = 0;
926 fpscrMask.ioc = ones;
927 fpscrMask.dzc = ones;
928 fpscrMask.ofc = ones;
929 fpscrMask.ufc = ones;
930 fpscrMask.ixc = ones;
931 fpscrMask.idc = ones;
932 fpscrMask.ioe = ones;
933 fpscrMask.dze = ones;
934 fpscrMask.ofe = ones;
935 fpscrMask.ufe = ones;
936 fpscrMask.ixe = ones;
937 fpscrMask.ide = ones;
938 fpscrMask.len = ones;
939 fpscrMask.stride = ones;
940 fpscrMask.rMode = ones;
941 fpscrMask.fz = ones;
942 fpscrMask.dn = ones;
943 fpscrMask.ahp = ones;
944 fpscrMask.qc = ones;
945 fpscrMask.v = ones;
946 fpscrMask.c = ones;
947 fpscrMask.z = ones;
948 fpscrMask.n = ones;
949 newVal = (newVal & (uint32_t)fpscrMask) |
950 (readMiscRegNoEffect(MISCREG_FPSCR) &
951 ~(uint32_t)fpscrMask);
952 tc->getDecoderPtr()->setContext(newVal);
953 }
954 break;
955 case MISCREG_FPSR:
956 {
957 const uint32_t ones = (uint32_t)(-1);
958 FPSCR fpscrMask = 0;
959 fpscrMask.ioc = ones;
960 fpscrMask.dzc = ones;
961 fpscrMask.ofc = ones;
962 fpscrMask.ufc = ones;
963 fpscrMask.ixc = ones;
964 fpscrMask.idc = ones;
965 fpscrMask.qc = ones;
966 fpscrMask.v = ones;
967 fpscrMask.c = ones;
968 fpscrMask.z = ones;
969 fpscrMask.n = ones;
970 newVal = (newVal & (uint32_t)fpscrMask) |
971 (readMiscRegNoEffect(MISCREG_FPSCR) &
972 ~(uint32_t)fpscrMask);
973 misc_reg = MISCREG_FPSCR;
974 }
975 break;
976 case MISCREG_FPCR:
977 {
978 const uint32_t ones = (uint32_t)(-1);
979 FPSCR fpscrMask = 0;
980 fpscrMask.ioe = ones;
981 fpscrMask.dze = ones;
982 fpscrMask.ofe = ones;
983 fpscrMask.ufe = ones;
984 fpscrMask.ixe = ones;
985 fpscrMask.ide = ones;
986 fpscrMask.len = ones;
987 fpscrMask.stride = ones;
988 fpscrMask.rMode = ones;
989 fpscrMask.fz = ones;
990 fpscrMask.dn = ones;
991 fpscrMask.ahp = ones;
992 newVal = (newVal & (uint32_t)fpscrMask) |
993 (readMiscRegNoEffect(MISCREG_FPSCR) &
994 ~(uint32_t)fpscrMask);
995 misc_reg = MISCREG_FPSCR;
996 }
997 break;
998 case MISCREG_CPSR_Q:
999 {
1000 assert(!(newVal & ~CpsrMaskQ));
1001 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1002 misc_reg = MISCREG_CPSR;
1003 }
1004 break;
1005 case MISCREG_FPSCR_QC:
1006 {
1007 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1008 (newVal & FpscrQcMask);
1009 misc_reg = MISCREG_FPSCR;
1010 }
1011 break;
1012 case MISCREG_FPSCR_EXC:
1013 {
1014 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1015 (newVal & FpscrExcMask);
1016 misc_reg = MISCREG_FPSCR;
1017 }
1018 break;
1019 case MISCREG_FPEXC:
1020 {
1021 // vfpv3 architecture, section B.6.1 of DDI04068
1022 // bit 29 - valid only if fpexc[31] is 0
1023 const uint32_t fpexcMask = 0x60000000;
1024 newVal = (newVal & fpexcMask) |
1025 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1026 }
1027 break;
1028 case MISCREG_HCR:
1029 {
1030 if (!haveVirtualization)
1031 return;
1032 }
1033 break;
1034 case MISCREG_IFSR:
1035 {
1036 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1037 const uint32_t ifsrMask =
1038 mask(31, 13) | mask(11, 11) | mask(8, 6);
1039 newVal = newVal & ~ifsrMask;
1040 }
1041 break;
1042 case MISCREG_DFSR:
1043 {
1044 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1045 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1046 newVal = newVal & ~dfsrMask;
1047 }
1048 break;
1049 case MISCREG_AMAIR0:
1050 case MISCREG_AMAIR1:
1051 {
1052 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1053 // Valid only with LPAE
1054 if (!haveLPAE)
1055 return;
1056 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1057 }
1058 break;
1059 case MISCREG_SCR:
1060 tc->getITBPtr()->invalidateMiscReg();
1061 tc->getDTBPtr()->invalidateMiscReg();
1062 break;
1063 case MISCREG_SCTLR:
1064 {
1065 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1066 MiscRegIndex sctlr_idx;
1067 scr = readMiscRegNoEffect(MISCREG_SCR);
1068 if (haveSecurity && !scr.ns) {
1069 sctlr_idx = MISCREG_SCTLR_S;
1070 } else {
1071 sctlr_idx = MISCREG_SCTLR_NS;
1072 // The FI field (bit 21) is common between S/NS versions
1073 // of the register, we store this in the secure copy of
1074 // the reg
1075 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21);
1076 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
1077 }
1078 SCTLR sctlr = miscRegs[sctlr_idx];
1079 SCTLR new_sctlr = newVal;
1080 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1081 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1082 tc->getITBPtr()->invalidateMiscReg();
1083 tc->getDTBPtr()->invalidateMiscReg();
1084
1085 // Check if all CPUs are booted with caches enabled
1086 // so we can stop enforcing coherency of some kernel
1087 // structures manually.
1088 sys = tc->getSystemPtr();
1089 for (x = 0; x < sys->numContexts(); x++) {
1090 oc = sys->getThreadContext(x);
1091 // @todo: double check this for security
1092 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
1093 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
1094 return;
1095 }
1096
1097 for (x = 0; x < sys->numContexts(); x++) {
1098 oc = sys->getThreadContext(x);
1099 oc->getDTBPtr()->allCpusCaching();
1100 oc->getITBPtr()->allCpusCaching();
1101
1102 // If CheckerCPU is connected, need to notify it.
1103 CheckerCPU *checker = oc->getCheckerCpuPtr();
1104 if (checker) {
1105 checker->getDTBPtr()->allCpusCaching();
1106 checker->getITBPtr()->allCpusCaching();
1107 }
1108 }
1109 return;
1110 }
1111
1112 case MISCREG_MIDR:
1113 case MISCREG_ID_PFR0:
1114 case MISCREG_ID_PFR1:
1115 case MISCREG_ID_MMFR0:
1116 case MISCREG_ID_MMFR1:
1117 case MISCREG_ID_MMFR2:
1118 case MISCREG_ID_MMFR3:
1119 case MISCREG_ID_ISAR0:
1120 case MISCREG_ID_ISAR1:
1121 case MISCREG_ID_ISAR2:
1122 case MISCREG_ID_ISAR3:
1123 case MISCREG_ID_ISAR4:
1124 case MISCREG_ID_ISAR5:
1125
1126 case MISCREG_MPIDR:
1127 case MISCREG_FPSID:
1128 case MISCREG_TLBTR:
1129 case MISCREG_MVFR0:
1130 case MISCREG_MVFR1:
1131
1132 case MISCREG_ID_AA64AFR0_EL1:
1133 case MISCREG_ID_AA64AFR1_EL1:
1134 case MISCREG_ID_AA64DFR0_EL1:
1135 case MISCREG_ID_AA64DFR1_EL1:
1136 case MISCREG_ID_AA64ISAR0_EL1:
1137 case MISCREG_ID_AA64ISAR1_EL1:
1138 case MISCREG_ID_AA64MMFR0_EL1:
1139 case MISCREG_ID_AA64MMFR1_EL1:
1140 case MISCREG_ID_AA64PFR0_EL1:
1141 case MISCREG_ID_AA64PFR1_EL1:
1142 // ID registers are constants.
1143 return;
1144
1145 // TLBI all entries, EL0&1 inner sharable (ignored)
1146 case MISCREG_TLBIALLIS:
1147 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1148 assert32(tc);
1149 target_el = 1; // el 0 and 1 are handled together
1150 scr = readMiscReg(MISCREG_SCR, tc);
1151 secure_lookup = haveSecurity && !scr.ns;
1152 sys = tc->getSystemPtr();
1153 for (x = 0; x < sys->numContexts(); x++) {
1154 oc = sys->getThreadContext(x);
1155 assert(oc->getITBPtr() && oc->getDTBPtr());
1156 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1157 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1158
1159 // If CheckerCPU is connected, need to notify it of a flush
1160 CheckerCPU *checker = oc->getCheckerCpuPtr();
1161 if (checker) {
1162 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1163 target_el);
1164 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1165 target_el);
1166 }
1167 }
1168 return;
1169 // TLBI all entries, EL0&1, instruction side
1170 case MISCREG_ITLBIALL:
1171 assert32(tc);
1172 target_el = 1; // el 0 and 1 are handled together
1173 scr = readMiscReg(MISCREG_SCR, tc);
1174 secure_lookup = haveSecurity && !scr.ns;
1175 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1176 return;
1177 // TLBI all entries, EL0&1, data side
1178 case MISCREG_DTLBIALL:
1179 assert32(tc);
1180 target_el = 1; // el 0 and 1 are handled together
1181 scr = readMiscReg(MISCREG_SCR, tc);
1182 secure_lookup = haveSecurity && !scr.ns;
1183 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1184 return;
1185 // TLBI based on VA, EL0&1 inner sharable (ignored)
1186 case MISCREG_TLBIMVAIS:
1187 case MISCREG_TLBIMVA:
1188 assert32(tc);
1189 target_el = 1; // el 0 and 1 are handled together
1190 scr = readMiscReg(MISCREG_SCR, tc);
1191 secure_lookup = haveSecurity && !scr.ns;
1192 sys = tc->getSystemPtr();
1193 for (x = 0; x < sys->numContexts(); x++) {
1194 oc = sys->getThreadContext(x);
1195 assert(oc->getITBPtr() && oc->getDTBPtr());
1196 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1197 bits(newVal, 7,0),
1198 secure_lookup, target_el);
1199 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1200 bits(newVal, 7,0),
1201 secure_lookup, target_el);
1202
1203 CheckerCPU *checker = oc->getCheckerCpuPtr();
1204 if (checker) {
1205 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1206 bits(newVal, 7,0), secure_lookup, target_el);
1207 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1208 bits(newVal, 7,0), secure_lookup, target_el);
1209 }
1210 }
1211 return;
1212 // TLBI by ASID, EL0&1, inner sharable
1213 case MISCREG_TLBIASIDIS:
1214 case MISCREG_TLBIASID:
1215 assert32(tc);
1216 target_el = 1; // el 0 and 1 are handled together
1217 scr = readMiscReg(MISCREG_SCR, tc);
1218 secure_lookup = haveSecurity && !scr.ns;
1219 sys = tc->getSystemPtr();
1220 for (x = 0; x < sys->numContexts(); x++) {
1221 oc = sys->getThreadContext(x);
1222 assert(oc->getITBPtr() && oc->getDTBPtr());
1223 oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1224 secure_lookup, target_el);
1225 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1226 secure_lookup, target_el);
1227 CheckerCPU *checker = oc->getCheckerCpuPtr();
1228 if (checker) {
1229 checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1230 secure_lookup, target_el);
1231 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1232 secure_lookup, target_el);
1233 }
1234 }
1235 return;
1236 // TLBI by address, EL0&1, inner sharable (ignored)
1237 case MISCREG_TLBIMVAAIS:
1238 case MISCREG_TLBIMVAA:
1239 assert32(tc);
1240 target_el = 1; // el 0 and 1 are handled together
1241 scr = readMiscReg(MISCREG_SCR, tc);
1242 secure_lookup = haveSecurity && !scr.ns;
1243 hyp = 0;
1244 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1245 return;
1246 // TLBI by address, EL2, hypervisor mode
1247 case MISCREG_TLBIMVAH:
1248 case MISCREG_TLBIMVAHIS:
1249 assert32(tc);
1250 target_el = 1; // aarch32, use hyp bit
1251 scr = readMiscReg(MISCREG_SCR, tc);
1252 secure_lookup = haveSecurity && !scr.ns;
1253 hyp = 1;
1254 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1255 return;
1256 // TLBI by address and asid, EL0&1, instruction side only
1257 case MISCREG_ITLBIMVA:
1258 assert32(tc);
1259 target_el = 1; // el 0 and 1 are handled together
1260 scr = readMiscReg(MISCREG_SCR, tc);
1261 secure_lookup = haveSecurity && !scr.ns;
1262 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1263 bits(newVal, 7,0), secure_lookup, target_el);
1264 return;
1265 // TLBI by address and asid, EL0&1, data side only
1266 case MISCREG_DTLBIMVA:
1267 assert32(tc);
1268 target_el = 1; // el 0 and 1 are handled together
1269 scr = readMiscReg(MISCREG_SCR, tc);
1270 secure_lookup = haveSecurity && !scr.ns;
1271 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1272 bits(newVal, 7,0), secure_lookup, target_el);
1273 return;
1274 // TLBI by ASID, EL0&1, instrution side only
1275 case MISCREG_ITLBIASID:
1276 assert32(tc);
1277 target_el = 1; // el 0 and 1 are handled together
1278 scr = readMiscReg(MISCREG_SCR, tc);
1279 secure_lookup = haveSecurity && !scr.ns;
1280 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1281 target_el);
1282 return;
1283 // TLBI by ASID EL0&1 data size only
1284 case MISCREG_DTLBIASID:
1285 assert32(tc);
1286 target_el = 1; // el 0 and 1 are handled together
1287 scr = readMiscReg(MISCREG_SCR, tc);
1288 secure_lookup = haveSecurity && !scr.ns;
1289 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1290 target_el);
1291 return;
1292 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1293 case MISCREG_TLBIALLNSNH:
1294 case MISCREG_TLBIALLNSNHIS:
1295 assert32(tc);
1296 target_el = 1; // el 0 and 1 are handled together
1297 hyp = 0;
1298 tlbiALLN(tc, hyp, target_el);
1299 return;
1300 // TLBI all entries, EL2, hyp,
1301 case MISCREG_TLBIALLH:
1302 case MISCREG_TLBIALLHIS:
1303 assert32(tc);
1304 target_el = 1; // aarch32, use hyp bit
1305 hyp = 1;
1306 tlbiALLN(tc, hyp, target_el);
1307 return;
1308 // AArch64 TLBI: invalidate all entries EL3
1309 case MISCREG_TLBI_ALLE3IS:
1310 case MISCREG_TLBI_ALLE3:
1311 assert64(tc);
1312 target_el = 3;
1313 secure_lookup = true;
1314 tlbiALL(tc, secure_lookup, target_el);
1315 return;
1316 // @todo: uncomment this to enable Virtualization
1317 // case MISCREG_TLBI_ALLE2IS:
1318 // case MISCREG_TLBI_ALLE2:
1319 // TLBI all entries, EL0&1
1320 case MISCREG_TLBI_ALLE1IS:
1321 case MISCREG_TLBI_ALLE1:
1322 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1323 case MISCREG_TLBI_VMALLE1IS:
1324 case MISCREG_TLBI_VMALLE1:
1325 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1326 case MISCREG_TLBI_VMALLS12E1IS:
1327 case MISCREG_TLBI_VMALLS12E1:
1328 // @todo: handle VMID and stage 2 to enable Virtualization
1329 assert64(tc);
1330 target_el = 1; // el 0 and 1 are handled together
1331 scr = readMiscReg(MISCREG_SCR, tc);
1332 secure_lookup = haveSecurity && !scr.ns;
1333 tlbiALL(tc, secure_lookup, target_el);
1334 return;
1335 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1336 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1337 // from the last level of translation table walks
1338 // @todo: handle VMID to enable Virtualization
1339 // TLBI all entries, EL0&1
1340 case MISCREG_TLBI_VAE3IS_Xt:
1341 case MISCREG_TLBI_VAE3_Xt:
1342 // TLBI by VA, EL3 regime stage 1, last level walk
1343 case MISCREG_TLBI_VALE3IS_Xt:
1344 case MISCREG_TLBI_VALE3_Xt:
1345 assert64(tc);
1346 target_el = 3;
1347 asid = 0xbeef; // does not matter, tlbi is global
1348 secure_lookup = true;
1349 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1350 return;
1351 // TLBI by VA, EL2
1352 case MISCREG_TLBI_VAE2IS_Xt:
1353 case MISCREG_TLBI_VAE2_Xt:
1354 // TLBI by VA, EL2, stage1 last level walk
1355 case MISCREG_TLBI_VALE2IS_Xt:
1356 case MISCREG_TLBI_VALE2_Xt:
1357 assert64(tc);
1358 target_el = 2;
1359 asid = 0xbeef; // does not matter, tlbi is global
1360 scr = readMiscReg(MISCREG_SCR, tc);
1361 secure_lookup = haveSecurity && !scr.ns;
1362 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1363 return;
1364 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1365 case MISCREG_TLBI_VAE1IS_Xt:
1366 case MISCREG_TLBI_VAE1_Xt:
1367 case MISCREG_TLBI_VALE1IS_Xt:
1368 case MISCREG_TLBI_VALE1_Xt:
1369 assert64(tc);
1370 asid = bits(newVal, 63, 48);
1371 target_el = 1; // el 0 and 1 are handled together
1372 scr = readMiscReg(MISCREG_SCR, tc);
1373 secure_lookup = haveSecurity && !scr.ns;
1374 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1375 return;
1376 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1377 // @todo: handle VMID to enable Virtualization
1378 case MISCREG_TLBI_ASIDE1IS_Xt:
1379 case MISCREG_TLBI_ASIDE1_Xt:
1380 assert64(tc);
1381 target_el = 1; // el 0 and 1 are handled together
1382 scr = readMiscReg(MISCREG_SCR, tc);
1383 secure_lookup = haveSecurity && !scr.ns;
1384 sys = tc->getSystemPtr();
1385 for (x = 0; x < sys->numContexts(); x++) {
1386 oc = sys->getThreadContext(x);
1387 assert(oc->getITBPtr() && oc->getDTBPtr());
1388 asid = bits(newVal, 63, 48);
1389 if (haveLargeAsid64)
1390 asid &= mask(8);
1391 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1392 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1393 CheckerCPU *checker = oc->getCheckerCpuPtr();
1394 if (checker) {
1395 checker->getITBPtr()->flushAsid(asid,
1396 secure_lookup, target_el);
1397 checker->getDTBPtr()->flushAsid(asid,
1398 secure_lookup, target_el);
1399 }
1400 }
1401 return;
1402 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1403 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1404 // entries from the last level of translation table walks
1405 // @todo: handle VMID to enable Virtualization
1406 case MISCREG_TLBI_VAAE1IS_Xt:
1407 case MISCREG_TLBI_VAAE1_Xt:
1408 case MISCREG_TLBI_VAALE1IS_Xt:
1409 case MISCREG_TLBI_VAALE1_Xt:
1410 assert64(tc);
1411 target_el = 1; // el 0 and 1 are handled together
1412 scr = readMiscReg(MISCREG_SCR, tc);
1413 secure_lookup = haveSecurity && !scr.ns;
1414 sys = tc->getSystemPtr();
1415 for (x = 0; x < sys->numContexts(); x++) {
1416 // @todo: extra controls on TLBI broadcast?
1417 oc = sys->getThreadContext(x);
1418 assert(oc->getITBPtr() && oc->getDTBPtr());
1419 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1420 oc->getITBPtr()->flushMva(va,
1421 secure_lookup, false, target_el);
1422 oc->getDTBPtr()->flushMva(va,
1423 secure_lookup, false, target_el);
1424
1425 CheckerCPU *checker = oc->getCheckerCpuPtr();
1426 if (checker) {
1427 checker->getITBPtr()->flushMva(va,
1428 secure_lookup, false, target_el);
1429 checker->getDTBPtr()->flushMva(va,
1430 secure_lookup, false, target_el);
1431 }
1432 }
1433 return;
1434 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1435 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1436 case MISCREG_TLBI_IPAS2LE1_Xt:
1437 case MISCREG_TLBI_IPAS2E1IS_Xt:
1438 case MISCREG_TLBI_IPAS2E1_Xt:
1439 assert64(tc);
1440 // @todo: implement these as part of Virtualization
1441 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1442 return;
1443 case MISCREG_ACTLR:
1444 warn("Not doing anything for write of miscreg ACTLR\n");
1445 break;
1446 case MISCREG_PMCR:
1447 {
1448 // Performance counters not implemented. Instead, interpret
1449 // a reset command to this register to reset the simulator
1450 // statistics.
1451 // PMCR_E | PMCR_P | PMCR_C
1452 const int ResetAndEnableCounters = 0x7;
1453 if (newVal == ResetAndEnableCounters) {
1454 inform("Resetting all simobject stats\n");
1455 Stats::schedStatEvent(false, true);
1456 break;
1457 }
1458 }
1459 case MISCREG_PMCCNTR:
1460 case MISCREG_PMSELR:
1461 warn("Not doing anything for write to miscreg %s\n",
1462 miscRegName[misc_reg]);
1463 break;
1464 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1465 {
1466 HSTR hstrMask = 0;
1467 hstrMask.tjdbx = 1;
1468 newVal &= ~((uint32_t) hstrMask);
1469 break;
1470 }
1471 case MISCREG_HCPTR:
1472 {
1473 // If a CP bit in NSACR is 0 then the corresponding bit in
1474 // HCPTR is RAO/WI. Same applies to NSASEDIS
1475 secure_lookup = haveSecurity &&
1476 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1477 readMiscRegNoEffect(MISCREG_CPSR));
1478 if (!secure_lookup) {
1479 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1480 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1481 newVal = (newVal & ~mask) | (oldValue & mask);
1482 }
1483 break;
1484 }
1485 case MISCREG_HDFAR: // alias for secure DFAR
1486 misc_reg = MISCREG_DFAR_S;
1487 break;
1488 case MISCREG_HIFAR: // alias for secure IFAR
1489 misc_reg = MISCREG_IFAR_S;
1490 break;
1491 case MISCREG_ATS1CPR:
1492 case MISCREG_ATS1CPW:
1493 case MISCREG_ATS1CUR:
1494 case MISCREG_ATS1CUW:
1495 case MISCREG_ATS12NSOPR:
1496 case MISCREG_ATS12NSOPW:
1497 case MISCREG_ATS12NSOUR:
1498 case MISCREG_ATS12NSOUW:
1499 case MISCREG_ATS1HR:
1500 case MISCREG_ATS1HW:
1501 {
1502 RequestPtr req = new Request;
1503 unsigned flags = 0;
1504 BaseTLB::Mode mode = BaseTLB::Read;
1505 TLB::ArmTranslationType tranType = TLB::NormalTran;
1506 Fault fault;
1507 switch(misc_reg) {
1508 case MISCREG_ATS1CPR:
1509 flags = TLB::MustBeOne;
1510 tranType = TLB::S1CTran;
1511 mode = BaseTLB::Read;
1512 break;
1513 case MISCREG_ATS1CPW:
1514 flags = TLB::MustBeOne;
1515 tranType = TLB::S1CTran;
1516 mode = BaseTLB::Write;
1517 break;
1518 case MISCREG_ATS1CUR:
1519 flags = TLB::MustBeOne | TLB::UserMode;
1520 tranType = TLB::S1CTran;
1521 mode = BaseTLB::Read;
1522 break;
1523 case MISCREG_ATS1CUW:
1524 flags = TLB::MustBeOne | TLB::UserMode;
1525 tranType = TLB::S1CTran;
1526 mode = BaseTLB::Write;
1527 break;
1528 case MISCREG_ATS12NSOPR:
1529 if (!haveSecurity)
1530 panic("Security Extensions required for ATS12NSOPR");
1531 flags = TLB::MustBeOne;
1532 tranType = TLB::S1S2NsTran;
1533 mode = BaseTLB::Read;
1534 break;
1535 case MISCREG_ATS12NSOPW:
1536 if (!haveSecurity)
1537 panic("Security Extensions required for ATS12NSOPW");
1538 flags = TLB::MustBeOne;
1539 tranType = TLB::S1S2NsTran;
1540 mode = BaseTLB::Write;
1541 break;
1542 case MISCREG_ATS12NSOUR:
1543 if (!haveSecurity)
1544 panic("Security Extensions required for ATS12NSOUR");
1545 flags = TLB::MustBeOne | TLB::UserMode;
1546 tranType = TLB::S1S2NsTran;
1547 mode = BaseTLB::Read;
1548 break;
1549 case MISCREG_ATS12NSOUW:
1550 if (!haveSecurity)
1551 panic("Security Extensions required for ATS12NSOUW");
1552 flags = TLB::MustBeOne | TLB::UserMode;
1553 tranType = TLB::S1S2NsTran;
1554 mode = BaseTLB::Write;
1555 break;
1556 case MISCREG_ATS1HR: // only really useful from secure mode.
1557 flags = TLB::MustBeOne;
1558 tranType = TLB::HypMode;
1559 mode = BaseTLB::Read;
1560 break;
1561 case MISCREG_ATS1HW:
1562 flags = TLB::MustBeOne;
1563 tranType = TLB::HypMode;
1564 mode = BaseTLB::Write;
1565 break;
1566 }
1567 // If we're in timing mode then doing the translation in
1568 // functional mode then we're slightly distorting performance
1569 // results obtained from simulations. The translation should be
1570 // done in the same mode the core is running in. NOTE: This
1571 // can't be an atomic translation because that causes problems
1572 // with unexpected atomic snoop requests.
1573 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1574 req->setVirt(0, val, 1, flags, Request::funcMasterId,
1575 tc->pcState().pc());
1576 req->setThreadContext(tc->contextId(), tc->threadId());
1577 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType);
1578 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1579 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1580
1581 MiscReg newVal;
1582 if (fault == NoFault) {
1583 Addr paddr = req->getPaddr();
1584 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1585 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1586 newVal = (paddr & mask(39, 12)) |
1587 (tc->getDTBPtr()->getAttr());
1588 } else {
1589 newVal = (paddr & 0xfffff000) |
1590 (tc->getDTBPtr()->getAttr());
1591 }
1592 DPRINTF(MiscRegs,
1593 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1594 val, newVal);
1595 } else {
1596 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1597 // Set fault bit and FSR
1598 FSR fsr = armFault->getFsr(tc);
1599
1600 newVal = ((fsr >> 9) & 1) << 11;
1601 if (newVal) {
1602 // LPAE - rearange fault status
1603 newVal |= ((fsr >> 0) & 0x3f) << 1;
1604 } else {
1605 // VMSA - rearange fault status
1606 newVal |= ((fsr >> 0) & 0xf) << 1;
1607 newVal |= ((fsr >> 10) & 0x1) << 5;
1608 newVal |= ((fsr >> 12) & 0x1) << 6;
1609 }
1610 newVal |= 0x1; // F bit
1611 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1612 newVal |= armFault->isStage2() ? 0x200 : 0;
1613 DPRINTF(MiscRegs,
1614 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1615 val, fsr, newVal);
1616 }
1617 delete req;
1618 setMiscRegNoEffect(MISCREG_PAR, newVal);
1619 return;
1620 }
1621 case MISCREG_TTBCR:
1622 {
1623 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1624 const uint32_t ones = (uint32_t)(-1);
1625 TTBCR ttbcrMask = 0;
1626 TTBCR ttbcrNew = newVal;
1627
1628 // ARM DDI 0406C.b, ARMv7-32
1629 ttbcrMask.n = ones; // T0SZ
1630 if (haveSecurity) {
1631 ttbcrMask.pd0 = ones;
1632 ttbcrMask.pd1 = ones;
1633 }
1634 ttbcrMask.epd0 = ones;
1635 ttbcrMask.irgn0 = ones;
1636 ttbcrMask.orgn0 = ones;
1637 ttbcrMask.sh0 = ones;
1638 ttbcrMask.ps = ones; // T1SZ
1639 ttbcrMask.a1 = ones;
1640 ttbcrMask.epd1 = ones;
1641 ttbcrMask.irgn1 = ones;
1642 ttbcrMask.orgn1 = ones;
1643 ttbcrMask.sh1 = ones;
1644 if (haveLPAE)
1645 ttbcrMask.eae = ones;
1646
1647 if (haveLPAE && ttbcrNew.eae) {
1648 newVal = newVal & ttbcrMask;
1649 } else {
1650 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1651 }
1652 }
1653 case MISCREG_TTBR0:
1654 case MISCREG_TTBR1:
1655 {
1656 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1657 if (haveLPAE) {
1658 if (ttbcr.eae) {
1659 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1660 // ARMv8 AArch32 bit 63-56 only
1661 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1662 newVal = (newVal & (~ttbrMask));
1663 }
1664 }
1665 }
1666 case MISCREG_CONTEXTIDR:
1667 case MISCREG_PRRR:
1668 case MISCREG_NMRR:
1669 case MISCREG_MAIR0:
1670 case MISCREG_MAIR1:
1671 case MISCREG_DACR:
1672 case MISCREG_VTTBR:
1673 case MISCREG_SCR_EL3:
1674 case MISCREG_SCTLR_EL1:
1675 case MISCREG_SCTLR_EL2:
1676 case MISCREG_SCTLR_EL3:
1677 case MISCREG_TCR_EL1:
1678 case MISCREG_TCR_EL2:
1679 case MISCREG_TCR_EL3:
1680 case MISCREG_TTBR0_EL1:
1681 case MISCREG_TTBR1_EL1:
1682 case MISCREG_TTBR0_EL2:
1683 case MISCREG_TTBR0_EL3:
1684 tc->getITBPtr()->invalidateMiscReg();
1685 tc->getDTBPtr()->invalidateMiscReg();
1686 break;
1687 case MISCREG_NZCV:
1688 {
1689 CPSR cpsr = val;
1690
| 605 return cpsr;
606 }
607 case MISCREG_DAIF:
608 {
609 CPSR cpsr = 0;
610 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
611 return cpsr;
612 }
613 case MISCREG_SP_EL0:
614 {
615 return tc->readIntReg(INTREG_SP0);
616 }
617 case MISCREG_SP_EL1:
618 {
619 return tc->readIntReg(INTREG_SP1);
620 }
621 case MISCREG_SP_EL2:
622 {
623 return tc->readIntReg(INTREG_SP2);
624 }
625 case MISCREG_SPSEL:
626 {
627 return miscRegs[MISCREG_CPSR] & 0x1;
628 }
629 case MISCREG_CURRENTEL:
630 {
631 return miscRegs[MISCREG_CPSR] & 0xc;
632 }
633 case MISCREG_L2CTLR:
634 {
635 // mostly unimplemented, just set NumCPUs field from sim and return
636 L2CTLR l2ctlr = 0;
637 // b00:1CPU to b11:4CPUs
638 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
639 return l2ctlr;
640 }
641 case MISCREG_DBGDIDR:
642 /* For now just implement the version number.
643 * Return 0 as we don't support debug architecture yet.
644 */
645 return 0;
646 case MISCREG_DBGDSCRint:
647 return 0;
648 case MISCREG_ISR:
649 return tc->getCpuPtr()->getInterruptController()->getISR(
650 readMiscRegNoEffect(MISCREG_HCR),
651 readMiscRegNoEffect(MISCREG_CPSR),
652 readMiscRegNoEffect(MISCREG_SCR));
653 case MISCREG_ISR_EL1:
654 return tc->getCpuPtr()->getInterruptController()->getISR(
655 readMiscRegNoEffect(MISCREG_HCR_EL2),
656 readMiscRegNoEffect(MISCREG_CPSR),
657 readMiscRegNoEffect(MISCREG_SCR_EL3));
658 case MISCREG_DCZID_EL0:
659 return 0x04; // DC ZVA clear 64-byte chunks
660 case MISCREG_HCPTR:
661 {
662 MiscReg val = readMiscRegNoEffect(misc_reg);
663 // The trap bit associated with CP14 is defined as RAZ
664 val &= ~(1 << 14);
665 // If a CP bit in NSACR is 0 then the corresponding bit in
666 // HCPTR is RAO/WI
667 bool secure_lookup = haveSecurity &&
668 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
669 readMiscRegNoEffect(MISCREG_CPSR));
670 if (!secure_lookup) {
671 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
672 val |= (mask ^ 0x7FFF) & 0xBFFF;
673 }
674 // Set the bits for unimplemented coprocessors to RAO/WI
675 val |= 0x33FF;
676 return (val);
677 }
678 case MISCREG_HDFAR: // alias for secure DFAR
679 return readMiscRegNoEffect(MISCREG_DFAR_S);
680 case MISCREG_HIFAR: // alias for secure IFAR
681 return readMiscRegNoEffect(MISCREG_IFAR_S);
682 case MISCREG_HVBAR: // bottom bits reserved
683 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
684 case MISCREG_SCTLR: // Some bits hardwired
685 // The FI field (bit 21) is common between S/NS versions of the register
686 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
687 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
688 case MISCREG_SCTLR_EL1:
689 // The FI field (bit 21) is common between S/NS versions of the register
690 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
691 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
692 case MISCREG_SCTLR_EL3:
693 // The FI field (bit 21) is common between S/NS versions of the register
694 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
695 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
696 case MISCREG_HSCTLR: // FI comes from SCTLR
697 {
698 uint32_t mask = 1 << 27;
699 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
700 (readMiscRegNoEffect(MISCREG_SCTLR) & mask);
701 }
702 case MISCREG_SCR:
703 {
704 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
705 if (cpsr.width) {
706 return readMiscRegNoEffect(MISCREG_SCR);
707 } else {
708 return readMiscRegNoEffect(MISCREG_SCR_EL3);
709 }
710 }
711 // Generic Timer registers
712 case MISCREG_CNTFRQ:
713 case MISCREG_CNTFRQ_EL0:
714 inform_once("Read CNTFREQ_EL0 frequency\n");
715 return getSystemCounter(tc)->freq();
716 case MISCREG_CNTPCT:
717 case MISCREG_CNTPCT_EL0:
718 return getSystemCounter(tc)->value();
719 case MISCREG_CNTVCT:
720 return getSystemCounter(tc)->value();
721 case MISCREG_CNTVCT_EL0:
722 return getSystemCounter(tc)->value();
723 case MISCREG_CNTP_CVAL:
724 case MISCREG_CNTP_CVAL_EL0:
725 return getArchTimer(tc, tc->cpuId())->compareValue();
726 case MISCREG_CNTP_TVAL:
727 case MISCREG_CNTP_TVAL_EL0:
728 return getArchTimer(tc, tc->cpuId())->timerValue();
729 case MISCREG_CNTP_CTL:
730 case MISCREG_CNTP_CTL_EL0:
731 return getArchTimer(tc, tc->cpuId())->control();
732 // PL1 phys. timer, secure
733 // AArch64
734 // case MISCREG_CNTPS_CVAL_EL1:
735 // case MISCREG_CNTPS_TVAL_EL1:
736 // case MISCREG_CNTPS_CTL_EL1:
737 // PL2 phys. timer, non-secure
738 // AArch32
739 // case MISCREG_CNTHCTL:
740 // case MISCREG_CNTHP_CVAL:
741 // case MISCREG_CNTHP_TVAL:
742 // case MISCREG_CNTHP_CTL:
743 // AArch64
744 // case MISCREG_CNTHCTL_EL2:
745 // case MISCREG_CNTHP_CVAL_EL2:
746 // case MISCREG_CNTHP_TVAL_EL2:
747 // case MISCREG_CNTHP_CTL_EL2:
748 // Virtual timer
749 // AArch32
750 // case MISCREG_CNTV_CVAL:
751 // case MISCREG_CNTV_TVAL:
752 // case MISCREG_CNTV_CTL:
753 // AArch64
754 // case MISCREG_CNTV_CVAL_EL2:
755 // case MISCREG_CNTV_TVAL_EL2:
756 // case MISCREG_CNTV_CTL_EL2:
757 default:
758 break;
759
760 }
761 return readMiscRegNoEffect(misc_reg);
762}
763
764void
765ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
766{
767 assert(misc_reg < NumMiscRegs);
768
769 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
770 // registers are left unchanged
771
772 int flat_idx2 = lookUpMiscReg[flat_idx].upper;
773
774 if (flat_idx2 > 0) {
775 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0);
776 miscRegs[flat_idx2] = bits(val, 63, 32);
777 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
778 misc_reg, flat_idx, flat_idx2, val);
779 } else {
780 if (flat_idx == MISCREG_SPSR)
781 flat_idx = flattenMiscIndex(MISCREG_SPSR);
782 else if (flat_idx == MISCREG_SCTLR_EL1)
783 flat_idx = flattenMiscIndex(MISCREG_SCTLR);
784 else
785 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
786 lookUpMiscReg[flat_idx].lower : flat_idx;
787 miscRegs[flat_idx] = val;
788 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
789 misc_reg, flat_idx, val);
790 }
791}
792
793void
794ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
795{
796
797 MiscReg newVal = val;
798 int x;
799 bool secure_lookup;
800 bool hyp;
801 System *sys;
802 ThreadContext *oc;
803 uint8_t target_el;
804 uint16_t asid;
805 SCR scr;
806
807 if (misc_reg == MISCREG_CPSR) {
808 updateRegMap(val);
809
810
811 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
812 int old_mode = old_cpsr.mode;
813 CPSR cpsr = val;
814 if (old_mode != cpsr.mode) {
815 tc->getITBPtr()->invalidateMiscReg();
816 tc->getDTBPtr()->invalidateMiscReg();
817 }
818
819 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
820 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
821 PCState pc = tc->pcState();
822 pc.nextThumb(cpsr.t);
823 pc.nextJazelle(cpsr.j);
824
825 // Follow slightly different semantics if a CheckerCPU object
826 // is connected
827 CheckerCPU *checker = tc->getCheckerCpuPtr();
828 if (checker) {
829 tc->pcStateNoRecord(pc);
830 } else {
831 tc->pcState(pc);
832 }
833 } else {
834#ifndef NDEBUG
835 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
836 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
837 warn("Unimplemented system register %s write with %#x.\n",
838 miscRegName[misc_reg], val);
839 else
840 panic("Unimplemented system register %s write with %#x.\n",
841 miscRegName[misc_reg], val);
842 }
843#endif
844 switch (unflattenMiscReg(misc_reg)) {
845 case MISCREG_CPACR:
846 {
847
848 const uint32_t ones = (uint32_t)(-1);
849 CPACR cpacrMask = 0;
850 // Only cp10, cp11, and ase are implemented, nothing else should
851 // be writable
852 cpacrMask.cp10 = ones;
853 cpacrMask.cp11 = ones;
854 cpacrMask.asedis = ones;
855
856 // Security Extensions may limit the writability of CPACR
857 if (haveSecurity) {
858 scr = readMiscRegNoEffect(MISCREG_SCR);
859 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
860 if (scr.ns && (cpsr.mode != MODE_MON)) {
861 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
862 // NB: Skipping the full loop, here
863 if (!nsacr.cp10) cpacrMask.cp10 = 0;
864 if (!nsacr.cp11) cpacrMask.cp11 = 0;
865 }
866 }
867
868 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
869 newVal &= cpacrMask;
870 newVal |= old_val & ~cpacrMask;
871 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
872 miscRegName[misc_reg], newVal);
873 }
874 break;
875 case MISCREG_CPACR_EL1:
876 {
877 const uint32_t ones = (uint32_t)(-1);
878 CPACR cpacrMask = 0;
879 cpacrMask.tta = ones;
880 cpacrMask.fpen = ones;
881 newVal &= cpacrMask;
882 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
883 miscRegName[misc_reg], newVal);
884 }
885 break;
886 case MISCREG_CPTR_EL2:
887 {
888 const uint32_t ones = (uint32_t)(-1);
889 CPTR cptrMask = 0;
890 cptrMask.tcpac = ones;
891 cptrMask.tta = ones;
892 cptrMask.tfp = ones;
893 newVal &= cptrMask;
894 cptrMask = 0;
895 cptrMask.res1_13_12_el2 = ones;
896 cptrMask.res1_9_0_el2 = ones;
897 newVal |= cptrMask;
898 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
899 miscRegName[misc_reg], newVal);
900 }
901 break;
902 case MISCREG_CPTR_EL3:
903 {
904 const uint32_t ones = (uint32_t)(-1);
905 CPTR cptrMask = 0;
906 cptrMask.tcpac = ones;
907 cptrMask.tta = ones;
908 cptrMask.tfp = ones;
909 newVal &= cptrMask;
910 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
911 miscRegName[misc_reg], newVal);
912 }
913 break;
914 case MISCREG_CSSELR:
915 warn_once("The csselr register isn't implemented.\n");
916 return;
917
918 case MISCREG_DC_ZVA_Xt:
919 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
920 return;
921
922 case MISCREG_FPSCR:
923 {
924 const uint32_t ones = (uint32_t)(-1);
925 FPSCR fpscrMask = 0;
926 fpscrMask.ioc = ones;
927 fpscrMask.dzc = ones;
928 fpscrMask.ofc = ones;
929 fpscrMask.ufc = ones;
930 fpscrMask.ixc = ones;
931 fpscrMask.idc = ones;
932 fpscrMask.ioe = ones;
933 fpscrMask.dze = ones;
934 fpscrMask.ofe = ones;
935 fpscrMask.ufe = ones;
936 fpscrMask.ixe = ones;
937 fpscrMask.ide = ones;
938 fpscrMask.len = ones;
939 fpscrMask.stride = ones;
940 fpscrMask.rMode = ones;
941 fpscrMask.fz = ones;
942 fpscrMask.dn = ones;
943 fpscrMask.ahp = ones;
944 fpscrMask.qc = ones;
945 fpscrMask.v = ones;
946 fpscrMask.c = ones;
947 fpscrMask.z = ones;
948 fpscrMask.n = ones;
949 newVal = (newVal & (uint32_t)fpscrMask) |
950 (readMiscRegNoEffect(MISCREG_FPSCR) &
951 ~(uint32_t)fpscrMask);
952 tc->getDecoderPtr()->setContext(newVal);
953 }
954 break;
955 case MISCREG_FPSR:
956 {
957 const uint32_t ones = (uint32_t)(-1);
958 FPSCR fpscrMask = 0;
959 fpscrMask.ioc = ones;
960 fpscrMask.dzc = ones;
961 fpscrMask.ofc = ones;
962 fpscrMask.ufc = ones;
963 fpscrMask.ixc = ones;
964 fpscrMask.idc = ones;
965 fpscrMask.qc = ones;
966 fpscrMask.v = ones;
967 fpscrMask.c = ones;
968 fpscrMask.z = ones;
969 fpscrMask.n = ones;
970 newVal = (newVal & (uint32_t)fpscrMask) |
971 (readMiscRegNoEffect(MISCREG_FPSCR) &
972 ~(uint32_t)fpscrMask);
973 misc_reg = MISCREG_FPSCR;
974 }
975 break;
976 case MISCREG_FPCR:
977 {
978 const uint32_t ones = (uint32_t)(-1);
979 FPSCR fpscrMask = 0;
980 fpscrMask.ioe = ones;
981 fpscrMask.dze = ones;
982 fpscrMask.ofe = ones;
983 fpscrMask.ufe = ones;
984 fpscrMask.ixe = ones;
985 fpscrMask.ide = ones;
986 fpscrMask.len = ones;
987 fpscrMask.stride = ones;
988 fpscrMask.rMode = ones;
989 fpscrMask.fz = ones;
990 fpscrMask.dn = ones;
991 fpscrMask.ahp = ones;
992 newVal = (newVal & (uint32_t)fpscrMask) |
993 (readMiscRegNoEffect(MISCREG_FPSCR) &
994 ~(uint32_t)fpscrMask);
995 misc_reg = MISCREG_FPSCR;
996 }
997 break;
998 case MISCREG_CPSR_Q:
999 {
1000 assert(!(newVal & ~CpsrMaskQ));
1001 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1002 misc_reg = MISCREG_CPSR;
1003 }
1004 break;
1005 case MISCREG_FPSCR_QC:
1006 {
1007 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1008 (newVal & FpscrQcMask);
1009 misc_reg = MISCREG_FPSCR;
1010 }
1011 break;
1012 case MISCREG_FPSCR_EXC:
1013 {
1014 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1015 (newVal & FpscrExcMask);
1016 misc_reg = MISCREG_FPSCR;
1017 }
1018 break;
1019 case MISCREG_FPEXC:
1020 {
1021 // vfpv3 architecture, section B.6.1 of DDI04068
1022 // bit 29 - valid only if fpexc[31] is 0
1023 const uint32_t fpexcMask = 0x60000000;
1024 newVal = (newVal & fpexcMask) |
1025 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1026 }
1027 break;
1028 case MISCREG_HCR:
1029 {
1030 if (!haveVirtualization)
1031 return;
1032 }
1033 break;
1034 case MISCREG_IFSR:
1035 {
1036 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1037 const uint32_t ifsrMask =
1038 mask(31, 13) | mask(11, 11) | mask(8, 6);
1039 newVal = newVal & ~ifsrMask;
1040 }
1041 break;
1042 case MISCREG_DFSR:
1043 {
1044 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1045 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1046 newVal = newVal & ~dfsrMask;
1047 }
1048 break;
1049 case MISCREG_AMAIR0:
1050 case MISCREG_AMAIR1:
1051 {
1052 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1053 // Valid only with LPAE
1054 if (!haveLPAE)
1055 return;
1056 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1057 }
1058 break;
1059 case MISCREG_SCR:
1060 tc->getITBPtr()->invalidateMiscReg();
1061 tc->getDTBPtr()->invalidateMiscReg();
1062 break;
1063 case MISCREG_SCTLR:
1064 {
1065 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1066 MiscRegIndex sctlr_idx;
1067 scr = readMiscRegNoEffect(MISCREG_SCR);
1068 if (haveSecurity && !scr.ns) {
1069 sctlr_idx = MISCREG_SCTLR_S;
1070 } else {
1071 sctlr_idx = MISCREG_SCTLR_NS;
1072 // The FI field (bit 21) is common between S/NS versions
1073 // of the register, we store this in the secure copy of
1074 // the reg
1075 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21);
1076 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
1077 }
1078 SCTLR sctlr = miscRegs[sctlr_idx];
1079 SCTLR new_sctlr = newVal;
1080 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1081 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1082 tc->getITBPtr()->invalidateMiscReg();
1083 tc->getDTBPtr()->invalidateMiscReg();
1084
1085 // Check if all CPUs are booted with caches enabled
1086 // so we can stop enforcing coherency of some kernel
1087 // structures manually.
1088 sys = tc->getSystemPtr();
1089 for (x = 0; x < sys->numContexts(); x++) {
1090 oc = sys->getThreadContext(x);
1091 // @todo: double check this for security
1092 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
1093 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
1094 return;
1095 }
1096
1097 for (x = 0; x < sys->numContexts(); x++) {
1098 oc = sys->getThreadContext(x);
1099 oc->getDTBPtr()->allCpusCaching();
1100 oc->getITBPtr()->allCpusCaching();
1101
1102 // If CheckerCPU is connected, need to notify it.
1103 CheckerCPU *checker = oc->getCheckerCpuPtr();
1104 if (checker) {
1105 checker->getDTBPtr()->allCpusCaching();
1106 checker->getITBPtr()->allCpusCaching();
1107 }
1108 }
1109 return;
1110 }
1111
1112 case MISCREG_MIDR:
1113 case MISCREG_ID_PFR0:
1114 case MISCREG_ID_PFR1:
1115 case MISCREG_ID_MMFR0:
1116 case MISCREG_ID_MMFR1:
1117 case MISCREG_ID_MMFR2:
1118 case MISCREG_ID_MMFR3:
1119 case MISCREG_ID_ISAR0:
1120 case MISCREG_ID_ISAR1:
1121 case MISCREG_ID_ISAR2:
1122 case MISCREG_ID_ISAR3:
1123 case MISCREG_ID_ISAR4:
1124 case MISCREG_ID_ISAR5:
1125
1126 case MISCREG_MPIDR:
1127 case MISCREG_FPSID:
1128 case MISCREG_TLBTR:
1129 case MISCREG_MVFR0:
1130 case MISCREG_MVFR1:
1131
1132 case MISCREG_ID_AA64AFR0_EL1:
1133 case MISCREG_ID_AA64AFR1_EL1:
1134 case MISCREG_ID_AA64DFR0_EL1:
1135 case MISCREG_ID_AA64DFR1_EL1:
1136 case MISCREG_ID_AA64ISAR0_EL1:
1137 case MISCREG_ID_AA64ISAR1_EL1:
1138 case MISCREG_ID_AA64MMFR0_EL1:
1139 case MISCREG_ID_AA64MMFR1_EL1:
1140 case MISCREG_ID_AA64PFR0_EL1:
1141 case MISCREG_ID_AA64PFR1_EL1:
1142 // ID registers are constants.
1143 return;
1144
1145 // TLBI all entries, EL0&1 inner sharable (ignored)
1146 case MISCREG_TLBIALLIS:
1147 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1148 assert32(tc);
1149 target_el = 1; // el 0 and 1 are handled together
1150 scr = readMiscReg(MISCREG_SCR, tc);
1151 secure_lookup = haveSecurity && !scr.ns;
1152 sys = tc->getSystemPtr();
1153 for (x = 0; x < sys->numContexts(); x++) {
1154 oc = sys->getThreadContext(x);
1155 assert(oc->getITBPtr() && oc->getDTBPtr());
1156 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1157 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1158
1159 // If CheckerCPU is connected, need to notify it of a flush
1160 CheckerCPU *checker = oc->getCheckerCpuPtr();
1161 if (checker) {
1162 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1163 target_el);
1164 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1165 target_el);
1166 }
1167 }
1168 return;
1169 // TLBI all entries, EL0&1, instruction side
1170 case MISCREG_ITLBIALL:
1171 assert32(tc);
1172 target_el = 1; // el 0 and 1 are handled together
1173 scr = readMiscReg(MISCREG_SCR, tc);
1174 secure_lookup = haveSecurity && !scr.ns;
1175 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1176 return;
1177 // TLBI all entries, EL0&1, data side
1178 case MISCREG_DTLBIALL:
1179 assert32(tc);
1180 target_el = 1; // el 0 and 1 are handled together
1181 scr = readMiscReg(MISCREG_SCR, tc);
1182 secure_lookup = haveSecurity && !scr.ns;
1183 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1184 return;
1185 // TLBI based on VA, EL0&1 inner sharable (ignored)
1186 case MISCREG_TLBIMVAIS:
1187 case MISCREG_TLBIMVA:
1188 assert32(tc);
1189 target_el = 1; // el 0 and 1 are handled together
1190 scr = readMiscReg(MISCREG_SCR, tc);
1191 secure_lookup = haveSecurity && !scr.ns;
1192 sys = tc->getSystemPtr();
1193 for (x = 0; x < sys->numContexts(); x++) {
1194 oc = sys->getThreadContext(x);
1195 assert(oc->getITBPtr() && oc->getDTBPtr());
1196 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1197 bits(newVal, 7,0),
1198 secure_lookup, target_el);
1199 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1200 bits(newVal, 7,0),
1201 secure_lookup, target_el);
1202
1203 CheckerCPU *checker = oc->getCheckerCpuPtr();
1204 if (checker) {
1205 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1206 bits(newVal, 7,0), secure_lookup, target_el);
1207 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1208 bits(newVal, 7,0), secure_lookup, target_el);
1209 }
1210 }
1211 return;
1212 // TLBI by ASID, EL0&1, inner sharable
1213 case MISCREG_TLBIASIDIS:
1214 case MISCREG_TLBIASID:
1215 assert32(tc);
1216 target_el = 1; // el 0 and 1 are handled together
1217 scr = readMiscReg(MISCREG_SCR, tc);
1218 secure_lookup = haveSecurity && !scr.ns;
1219 sys = tc->getSystemPtr();
1220 for (x = 0; x < sys->numContexts(); x++) {
1221 oc = sys->getThreadContext(x);
1222 assert(oc->getITBPtr() && oc->getDTBPtr());
1223 oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1224 secure_lookup, target_el);
1225 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1226 secure_lookup, target_el);
1227 CheckerCPU *checker = oc->getCheckerCpuPtr();
1228 if (checker) {
1229 checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1230 secure_lookup, target_el);
1231 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1232 secure_lookup, target_el);
1233 }
1234 }
1235 return;
1236 // TLBI by address, EL0&1, inner sharable (ignored)
1237 case MISCREG_TLBIMVAAIS:
1238 case MISCREG_TLBIMVAA:
1239 assert32(tc);
1240 target_el = 1; // el 0 and 1 are handled together
1241 scr = readMiscReg(MISCREG_SCR, tc);
1242 secure_lookup = haveSecurity && !scr.ns;
1243 hyp = 0;
1244 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1245 return;
1246 // TLBI by address, EL2, hypervisor mode
1247 case MISCREG_TLBIMVAH:
1248 case MISCREG_TLBIMVAHIS:
1249 assert32(tc);
1250 target_el = 1; // aarch32, use hyp bit
1251 scr = readMiscReg(MISCREG_SCR, tc);
1252 secure_lookup = haveSecurity && !scr.ns;
1253 hyp = 1;
1254 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1255 return;
1256 // TLBI by address and asid, EL0&1, instruction side only
1257 case MISCREG_ITLBIMVA:
1258 assert32(tc);
1259 target_el = 1; // el 0 and 1 are handled together
1260 scr = readMiscReg(MISCREG_SCR, tc);
1261 secure_lookup = haveSecurity && !scr.ns;
1262 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1263 bits(newVal, 7,0), secure_lookup, target_el);
1264 return;
1265 // TLBI by address and asid, EL0&1, data side only
1266 case MISCREG_DTLBIMVA:
1267 assert32(tc);
1268 target_el = 1; // el 0 and 1 are handled together
1269 scr = readMiscReg(MISCREG_SCR, tc);
1270 secure_lookup = haveSecurity && !scr.ns;
1271 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1272 bits(newVal, 7,0), secure_lookup, target_el);
1273 return;
1274 // TLBI by ASID, EL0&1, instrution side only
1275 case MISCREG_ITLBIASID:
1276 assert32(tc);
1277 target_el = 1; // el 0 and 1 are handled together
1278 scr = readMiscReg(MISCREG_SCR, tc);
1279 secure_lookup = haveSecurity && !scr.ns;
1280 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1281 target_el);
1282 return;
1283 // TLBI by ASID EL0&1 data size only
1284 case MISCREG_DTLBIASID:
1285 assert32(tc);
1286 target_el = 1; // el 0 and 1 are handled together
1287 scr = readMiscReg(MISCREG_SCR, tc);
1288 secure_lookup = haveSecurity && !scr.ns;
1289 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1290 target_el);
1291 return;
1292 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1293 case MISCREG_TLBIALLNSNH:
1294 case MISCREG_TLBIALLNSNHIS:
1295 assert32(tc);
1296 target_el = 1; // el 0 and 1 are handled together
1297 hyp = 0;
1298 tlbiALLN(tc, hyp, target_el);
1299 return;
1300 // TLBI all entries, EL2, hyp,
1301 case MISCREG_TLBIALLH:
1302 case MISCREG_TLBIALLHIS:
1303 assert32(tc);
1304 target_el = 1; // aarch32, use hyp bit
1305 hyp = 1;
1306 tlbiALLN(tc, hyp, target_el);
1307 return;
1308 // AArch64 TLBI: invalidate all entries EL3
1309 case MISCREG_TLBI_ALLE3IS:
1310 case MISCREG_TLBI_ALLE3:
1311 assert64(tc);
1312 target_el = 3;
1313 secure_lookup = true;
1314 tlbiALL(tc, secure_lookup, target_el);
1315 return;
1316 // @todo: uncomment this to enable Virtualization
1317 // case MISCREG_TLBI_ALLE2IS:
1318 // case MISCREG_TLBI_ALLE2:
1319 // TLBI all entries, EL0&1
1320 case MISCREG_TLBI_ALLE1IS:
1321 case MISCREG_TLBI_ALLE1:
1322 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1323 case MISCREG_TLBI_VMALLE1IS:
1324 case MISCREG_TLBI_VMALLE1:
1325 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1326 case MISCREG_TLBI_VMALLS12E1IS:
1327 case MISCREG_TLBI_VMALLS12E1:
1328 // @todo: handle VMID and stage 2 to enable Virtualization
1329 assert64(tc);
1330 target_el = 1; // el 0 and 1 are handled together
1331 scr = readMiscReg(MISCREG_SCR, tc);
1332 secure_lookup = haveSecurity && !scr.ns;
1333 tlbiALL(tc, secure_lookup, target_el);
1334 return;
1335 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1336 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1337 // from the last level of translation table walks
1338 // @todo: handle VMID to enable Virtualization
1339 // TLBI all entries, EL0&1
1340 case MISCREG_TLBI_VAE3IS_Xt:
1341 case MISCREG_TLBI_VAE3_Xt:
1342 // TLBI by VA, EL3 regime stage 1, last level walk
1343 case MISCREG_TLBI_VALE3IS_Xt:
1344 case MISCREG_TLBI_VALE3_Xt:
1345 assert64(tc);
1346 target_el = 3;
1347 asid = 0xbeef; // does not matter, tlbi is global
1348 secure_lookup = true;
1349 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1350 return;
1351 // TLBI by VA, EL2
1352 case MISCREG_TLBI_VAE2IS_Xt:
1353 case MISCREG_TLBI_VAE2_Xt:
1354 // TLBI by VA, EL2, stage1 last level walk
1355 case MISCREG_TLBI_VALE2IS_Xt:
1356 case MISCREG_TLBI_VALE2_Xt:
1357 assert64(tc);
1358 target_el = 2;
1359 asid = 0xbeef; // does not matter, tlbi is global
1360 scr = readMiscReg(MISCREG_SCR, tc);
1361 secure_lookup = haveSecurity && !scr.ns;
1362 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1363 return;
1364 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1365 case MISCREG_TLBI_VAE1IS_Xt:
1366 case MISCREG_TLBI_VAE1_Xt:
1367 case MISCREG_TLBI_VALE1IS_Xt:
1368 case MISCREG_TLBI_VALE1_Xt:
1369 assert64(tc);
1370 asid = bits(newVal, 63, 48);
1371 target_el = 1; // el 0 and 1 are handled together
1372 scr = readMiscReg(MISCREG_SCR, tc);
1373 secure_lookup = haveSecurity && !scr.ns;
1374 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1375 return;
1376 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1377 // @todo: handle VMID to enable Virtualization
1378 case MISCREG_TLBI_ASIDE1IS_Xt:
1379 case MISCREG_TLBI_ASIDE1_Xt:
1380 assert64(tc);
1381 target_el = 1; // el 0 and 1 are handled together
1382 scr = readMiscReg(MISCREG_SCR, tc);
1383 secure_lookup = haveSecurity && !scr.ns;
1384 sys = tc->getSystemPtr();
1385 for (x = 0; x < sys->numContexts(); x++) {
1386 oc = sys->getThreadContext(x);
1387 assert(oc->getITBPtr() && oc->getDTBPtr());
1388 asid = bits(newVal, 63, 48);
1389 if (haveLargeAsid64)
1390 asid &= mask(8);
1391 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1392 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1393 CheckerCPU *checker = oc->getCheckerCpuPtr();
1394 if (checker) {
1395 checker->getITBPtr()->flushAsid(asid,
1396 secure_lookup, target_el);
1397 checker->getDTBPtr()->flushAsid(asid,
1398 secure_lookup, target_el);
1399 }
1400 }
1401 return;
1402 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1403 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1404 // entries from the last level of translation table walks
1405 // @todo: handle VMID to enable Virtualization
1406 case MISCREG_TLBI_VAAE1IS_Xt:
1407 case MISCREG_TLBI_VAAE1_Xt:
1408 case MISCREG_TLBI_VAALE1IS_Xt:
1409 case MISCREG_TLBI_VAALE1_Xt:
1410 assert64(tc);
1411 target_el = 1; // el 0 and 1 are handled together
1412 scr = readMiscReg(MISCREG_SCR, tc);
1413 secure_lookup = haveSecurity && !scr.ns;
1414 sys = tc->getSystemPtr();
1415 for (x = 0; x < sys->numContexts(); x++) {
1416 // @todo: extra controls on TLBI broadcast?
1417 oc = sys->getThreadContext(x);
1418 assert(oc->getITBPtr() && oc->getDTBPtr());
1419 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1420 oc->getITBPtr()->flushMva(va,
1421 secure_lookup, false, target_el);
1422 oc->getDTBPtr()->flushMva(va,
1423 secure_lookup, false, target_el);
1424
1425 CheckerCPU *checker = oc->getCheckerCpuPtr();
1426 if (checker) {
1427 checker->getITBPtr()->flushMva(va,
1428 secure_lookup, false, target_el);
1429 checker->getDTBPtr()->flushMva(va,
1430 secure_lookup, false, target_el);
1431 }
1432 }
1433 return;
1434 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1435 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1436 case MISCREG_TLBI_IPAS2LE1_Xt:
1437 case MISCREG_TLBI_IPAS2E1IS_Xt:
1438 case MISCREG_TLBI_IPAS2E1_Xt:
1439 assert64(tc);
1440 // @todo: implement these as part of Virtualization
1441 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1442 return;
1443 case MISCREG_ACTLR:
1444 warn("Not doing anything for write of miscreg ACTLR\n");
1445 break;
1446 case MISCREG_PMCR:
1447 {
1448 // Performance counters not implemented. Instead, interpret
1449 // a reset command to this register to reset the simulator
1450 // statistics.
1451 // PMCR_E | PMCR_P | PMCR_C
1452 const int ResetAndEnableCounters = 0x7;
1453 if (newVal == ResetAndEnableCounters) {
1454 inform("Resetting all simobject stats\n");
1455 Stats::schedStatEvent(false, true);
1456 break;
1457 }
1458 }
1459 case MISCREG_PMCCNTR:
1460 case MISCREG_PMSELR:
1461 warn("Not doing anything for write to miscreg %s\n",
1462 miscRegName[misc_reg]);
1463 break;
1464 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1465 {
1466 HSTR hstrMask = 0;
1467 hstrMask.tjdbx = 1;
1468 newVal &= ~((uint32_t) hstrMask);
1469 break;
1470 }
1471 case MISCREG_HCPTR:
1472 {
1473 // If a CP bit in NSACR is 0 then the corresponding bit in
1474 // HCPTR is RAO/WI. Same applies to NSASEDIS
1475 secure_lookup = haveSecurity &&
1476 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1477 readMiscRegNoEffect(MISCREG_CPSR));
1478 if (!secure_lookup) {
1479 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1480 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1481 newVal = (newVal & ~mask) | (oldValue & mask);
1482 }
1483 break;
1484 }
1485 case MISCREG_HDFAR: // alias for secure DFAR
1486 misc_reg = MISCREG_DFAR_S;
1487 break;
1488 case MISCREG_HIFAR: // alias for secure IFAR
1489 misc_reg = MISCREG_IFAR_S;
1490 break;
1491 case MISCREG_ATS1CPR:
1492 case MISCREG_ATS1CPW:
1493 case MISCREG_ATS1CUR:
1494 case MISCREG_ATS1CUW:
1495 case MISCREG_ATS12NSOPR:
1496 case MISCREG_ATS12NSOPW:
1497 case MISCREG_ATS12NSOUR:
1498 case MISCREG_ATS12NSOUW:
1499 case MISCREG_ATS1HR:
1500 case MISCREG_ATS1HW:
1501 {
1502 RequestPtr req = new Request;
1503 unsigned flags = 0;
1504 BaseTLB::Mode mode = BaseTLB::Read;
1505 TLB::ArmTranslationType tranType = TLB::NormalTran;
1506 Fault fault;
1507 switch(misc_reg) {
1508 case MISCREG_ATS1CPR:
1509 flags = TLB::MustBeOne;
1510 tranType = TLB::S1CTran;
1511 mode = BaseTLB::Read;
1512 break;
1513 case MISCREG_ATS1CPW:
1514 flags = TLB::MustBeOne;
1515 tranType = TLB::S1CTran;
1516 mode = BaseTLB::Write;
1517 break;
1518 case MISCREG_ATS1CUR:
1519 flags = TLB::MustBeOne | TLB::UserMode;
1520 tranType = TLB::S1CTran;
1521 mode = BaseTLB::Read;
1522 break;
1523 case MISCREG_ATS1CUW:
1524 flags = TLB::MustBeOne | TLB::UserMode;
1525 tranType = TLB::S1CTran;
1526 mode = BaseTLB::Write;
1527 break;
1528 case MISCREG_ATS12NSOPR:
1529 if (!haveSecurity)
1530 panic("Security Extensions required for ATS12NSOPR");
1531 flags = TLB::MustBeOne;
1532 tranType = TLB::S1S2NsTran;
1533 mode = BaseTLB::Read;
1534 break;
1535 case MISCREG_ATS12NSOPW:
1536 if (!haveSecurity)
1537 panic("Security Extensions required for ATS12NSOPW");
1538 flags = TLB::MustBeOne;
1539 tranType = TLB::S1S2NsTran;
1540 mode = BaseTLB::Write;
1541 break;
1542 case MISCREG_ATS12NSOUR:
1543 if (!haveSecurity)
1544 panic("Security Extensions required for ATS12NSOUR");
1545 flags = TLB::MustBeOne | TLB::UserMode;
1546 tranType = TLB::S1S2NsTran;
1547 mode = BaseTLB::Read;
1548 break;
1549 case MISCREG_ATS12NSOUW:
1550 if (!haveSecurity)
1551 panic("Security Extensions required for ATS12NSOUW");
1552 flags = TLB::MustBeOne | TLB::UserMode;
1553 tranType = TLB::S1S2NsTran;
1554 mode = BaseTLB::Write;
1555 break;
1556 case MISCREG_ATS1HR: // only really useful from secure mode.
1557 flags = TLB::MustBeOne;
1558 tranType = TLB::HypMode;
1559 mode = BaseTLB::Read;
1560 break;
1561 case MISCREG_ATS1HW:
1562 flags = TLB::MustBeOne;
1563 tranType = TLB::HypMode;
1564 mode = BaseTLB::Write;
1565 break;
1566 }
1567 // If we're in timing mode then doing the translation in
1568 // functional mode then we're slightly distorting performance
1569 // results obtained from simulations. The translation should be
1570 // done in the same mode the core is running in. NOTE: This
1571 // can't be an atomic translation because that causes problems
1572 // with unexpected atomic snoop requests.
1573 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1574 req->setVirt(0, val, 1, flags, Request::funcMasterId,
1575 tc->pcState().pc());
1576 req->setThreadContext(tc->contextId(), tc->threadId());
1577 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType);
1578 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1579 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1580
1581 MiscReg newVal;
1582 if (fault == NoFault) {
1583 Addr paddr = req->getPaddr();
1584 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1585 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1586 newVal = (paddr & mask(39, 12)) |
1587 (tc->getDTBPtr()->getAttr());
1588 } else {
1589 newVal = (paddr & 0xfffff000) |
1590 (tc->getDTBPtr()->getAttr());
1591 }
1592 DPRINTF(MiscRegs,
1593 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1594 val, newVal);
1595 } else {
1596 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1597 // Set fault bit and FSR
1598 FSR fsr = armFault->getFsr(tc);
1599
1600 newVal = ((fsr >> 9) & 1) << 11;
1601 if (newVal) {
1602 // LPAE - rearange fault status
1603 newVal |= ((fsr >> 0) & 0x3f) << 1;
1604 } else {
1605 // VMSA - rearange fault status
1606 newVal |= ((fsr >> 0) & 0xf) << 1;
1607 newVal |= ((fsr >> 10) & 0x1) << 5;
1608 newVal |= ((fsr >> 12) & 0x1) << 6;
1609 }
1610 newVal |= 0x1; // F bit
1611 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1612 newVal |= armFault->isStage2() ? 0x200 : 0;
1613 DPRINTF(MiscRegs,
1614 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1615 val, fsr, newVal);
1616 }
1617 delete req;
1618 setMiscRegNoEffect(MISCREG_PAR, newVal);
1619 return;
1620 }
1621 case MISCREG_TTBCR:
1622 {
1623 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1624 const uint32_t ones = (uint32_t)(-1);
1625 TTBCR ttbcrMask = 0;
1626 TTBCR ttbcrNew = newVal;
1627
1628 // ARM DDI 0406C.b, ARMv7-32
1629 ttbcrMask.n = ones; // T0SZ
1630 if (haveSecurity) {
1631 ttbcrMask.pd0 = ones;
1632 ttbcrMask.pd1 = ones;
1633 }
1634 ttbcrMask.epd0 = ones;
1635 ttbcrMask.irgn0 = ones;
1636 ttbcrMask.orgn0 = ones;
1637 ttbcrMask.sh0 = ones;
1638 ttbcrMask.ps = ones; // T1SZ
1639 ttbcrMask.a1 = ones;
1640 ttbcrMask.epd1 = ones;
1641 ttbcrMask.irgn1 = ones;
1642 ttbcrMask.orgn1 = ones;
1643 ttbcrMask.sh1 = ones;
1644 if (haveLPAE)
1645 ttbcrMask.eae = ones;
1646
1647 if (haveLPAE && ttbcrNew.eae) {
1648 newVal = newVal & ttbcrMask;
1649 } else {
1650 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1651 }
1652 }
1653 case MISCREG_TTBR0:
1654 case MISCREG_TTBR1:
1655 {
1656 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1657 if (haveLPAE) {
1658 if (ttbcr.eae) {
1659 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1660 // ARMv8 AArch32 bit 63-56 only
1661 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1662 newVal = (newVal & (~ttbrMask));
1663 }
1664 }
1665 }
1666 case MISCREG_CONTEXTIDR:
1667 case MISCREG_PRRR:
1668 case MISCREG_NMRR:
1669 case MISCREG_MAIR0:
1670 case MISCREG_MAIR1:
1671 case MISCREG_DACR:
1672 case MISCREG_VTTBR:
1673 case MISCREG_SCR_EL3:
1674 case MISCREG_SCTLR_EL1:
1675 case MISCREG_SCTLR_EL2:
1676 case MISCREG_SCTLR_EL3:
1677 case MISCREG_TCR_EL1:
1678 case MISCREG_TCR_EL2:
1679 case MISCREG_TCR_EL3:
1680 case MISCREG_TTBR0_EL1:
1681 case MISCREG_TTBR1_EL1:
1682 case MISCREG_TTBR0_EL2:
1683 case MISCREG_TTBR0_EL3:
1684 tc->getITBPtr()->invalidateMiscReg();
1685 tc->getDTBPtr()->invalidateMiscReg();
1686 break;
1687 case MISCREG_NZCV:
1688 {
1689 CPSR cpsr = val;
1690
|
1691 tc->setIntReg(INTREG_CONDCODES_NZ, cpsr.nz);
1692 tc->setIntReg(INTREG_CONDCODES_C, cpsr.c);
1693 tc->setIntReg(INTREG_CONDCODES_V, cpsr.v);
| 1691 tc->setCCReg(CCREG_NZ, cpsr.nz);
1692 tc->setCCReg(CCREG_C, cpsr.c);
1693 tc->setCCReg(CCREG_V, cpsr.v);
|
1694 }
1695 break;
1696 case MISCREG_DAIF:
1697 {
1698 CPSR cpsr = miscRegs[MISCREG_CPSR];
1699 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1700 newVal = cpsr;
1701 misc_reg = MISCREG_CPSR;
1702 }
1703 break;
1704 case MISCREG_SP_EL0:
1705 tc->setIntReg(INTREG_SP0, newVal);
1706 break;
1707 case MISCREG_SP_EL1:
1708 tc->setIntReg(INTREG_SP1, newVal);
1709 break;
1710 case MISCREG_SP_EL2:
1711 tc->setIntReg(INTREG_SP2, newVal);
1712 break;
1713 case MISCREG_SPSEL:
1714 {
1715 CPSR cpsr = miscRegs[MISCREG_CPSR];
1716 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1717 newVal = cpsr;
1718 misc_reg = MISCREG_CPSR;
1719 }
1720 break;
1721 case MISCREG_CURRENTEL:
1722 {
1723 CPSR cpsr = miscRegs[MISCREG_CPSR];
1724 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1725 newVal = cpsr;
1726 misc_reg = MISCREG_CPSR;
1727 }
1728 break;
1729 case MISCREG_AT_S1E1R_Xt:
1730 case MISCREG_AT_S1E1W_Xt:
1731 case MISCREG_AT_S1E0R_Xt:
1732 case MISCREG_AT_S1E0W_Xt:
1733 case MISCREG_AT_S1E2R_Xt:
1734 case MISCREG_AT_S1E2W_Xt:
1735 case MISCREG_AT_S12E1R_Xt:
1736 case MISCREG_AT_S12E1W_Xt:
1737 case MISCREG_AT_S12E0R_Xt:
1738 case MISCREG_AT_S12E0W_Xt:
1739 case MISCREG_AT_S1E3R_Xt:
1740 case MISCREG_AT_S1E3W_Xt:
1741 {
1742 RequestPtr req = new Request;
1743 unsigned flags = 0;
1744 BaseTLB::Mode mode = BaseTLB::Read;
1745 TLB::ArmTranslationType tranType = TLB::NormalTran;
1746 Fault fault;
1747 switch(misc_reg) {
1748 case MISCREG_AT_S1E1R_Xt:
1749 flags = TLB::MustBeOne;
1750 tranType = TLB::S1CTran;
1751 mode = BaseTLB::Read;
1752 break;
1753 case MISCREG_AT_S1E1W_Xt:
1754 flags = TLB::MustBeOne;
1755 tranType = TLB::S1CTran;
1756 mode = BaseTLB::Write;
1757 break;
1758 case MISCREG_AT_S1E0R_Xt:
1759 flags = TLB::MustBeOne | TLB::UserMode;
1760 tranType = TLB::S1CTran;
1761 mode = BaseTLB::Read;
1762 break;
1763 case MISCREG_AT_S1E0W_Xt:
1764 flags = TLB::MustBeOne | TLB::UserMode;
1765 tranType = TLB::S1CTran;
1766 mode = BaseTLB::Write;
1767 break;
1768 case MISCREG_AT_S1E2R_Xt:
1769 flags = TLB::MustBeOne;
1770 tranType = TLB::HypMode;
1771 mode = BaseTLB::Read;
1772 break;
1773 case MISCREG_AT_S1E2W_Xt:
1774 flags = TLB::MustBeOne;
1775 tranType = TLB::HypMode;
1776 mode = BaseTLB::Write;
1777 break;
1778 case MISCREG_AT_S12E0R_Xt:
1779 flags = TLB::MustBeOne | TLB::UserMode;
1780 tranType = TLB::S1S2NsTran;
1781 mode = BaseTLB::Read;
1782 break;
1783 case MISCREG_AT_S12E0W_Xt:
1784 flags = TLB::MustBeOne | TLB::UserMode;
1785 tranType = TLB::S1S2NsTran;
1786 mode = BaseTLB::Write;
1787 break;
1788 case MISCREG_AT_S12E1R_Xt:
1789 flags = TLB::MustBeOne;
1790 tranType = TLB::S1S2NsTran;
1791 mode = BaseTLB::Read;
1792 break;
1793 case MISCREG_AT_S12E1W_Xt:
1794 flags = TLB::MustBeOne;
1795 tranType = TLB::S1S2NsTran;
1796 mode = BaseTLB::Write;
1797 break;
1798 case MISCREG_AT_S1E3R_Xt:
1799 flags = TLB::MustBeOne;
1800 tranType = TLB::HypMode; // There is no TZ mode defined.
1801 mode = BaseTLB::Read;
1802 break;
1803 case MISCREG_AT_S1E3W_Xt:
1804 flags = TLB::MustBeOne;
1805 tranType = TLB::HypMode; // There is no TZ mode defined.
1806 mode = BaseTLB::Write;
1807 break;
1808 }
1809 // If we're in timing mode then doing the translation in
1810 // functional mode then we're slightly distorting performance
1811 // results obtained from simulations. The translation should be
1812 // done in the same mode the core is running in. NOTE: This
1813 // can't be an atomic translation because that causes problems
1814 // with unexpected atomic snoop requests.
1815 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1816 req->setVirt(0, val, 1, flags, Request::funcMasterId,
1817 tc->pcState().pc());
1818 req->setThreadContext(tc->contextId(), tc->threadId());
1819 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1820 tranType);
1821
1822 MiscReg newVal;
1823 if (fault == NoFault) {
1824 Addr paddr = req->getPaddr();
1825 uint64_t attr = tc->getDTBPtr()->getAttr();
1826 uint64_t attr1 = attr >> 56;
1827 if (!attr1 || attr1 ==0x44) {
1828 attr |= 0x100;
1829 attr &= ~ uint64_t(0x80);
1830 }
1831 newVal = (paddr & mask(47, 12)) | attr;
1832 DPRINTF(MiscRegs,
1833 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1834 val, newVal);
1835 } else {
1836 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1837 // Set fault bit and FSR
1838 FSR fsr = armFault->getFsr(tc);
1839
1840 newVal = ((fsr >> 9) & 1) << 11;
1841 // rearange fault status
1842 newVal |= ((fsr >> 0) & 0x3f) << 1;
1843 newVal |= 0x1; // F bit
1844 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1845 newVal |= armFault->isStage2() ? 0x200 : 0;
1846 DPRINTF(MiscRegs,
1847 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1848 val, fsr, newVal);
1849 }
1850 delete req;
1851 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1852 return;
1853 }
1854 case MISCREG_SPSR_EL3:
1855 case MISCREG_SPSR_EL2:
1856 case MISCREG_SPSR_EL1:
1857 // Force bits 23:21 to 0
1858 newVal = val & ~(0x7 << 21);
1859 break;
1860 case MISCREG_L2CTLR:
1861 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1862 miscRegName[misc_reg], uint32_t(val));
1863 break;
1864
1865 // Generic Timer registers
1866 case MISCREG_CNTFRQ:
1867 case MISCREG_CNTFRQ_EL0:
1868 getSystemCounter(tc)->setFreq(val);
1869 break;
1870 case MISCREG_CNTP_CVAL:
1871 case MISCREG_CNTP_CVAL_EL0:
1872 getArchTimer(tc, tc->cpuId())->setCompareValue(val);
1873 break;
1874 case MISCREG_CNTP_TVAL:
1875 case MISCREG_CNTP_TVAL_EL0:
1876 getArchTimer(tc, tc->cpuId())->setTimerValue(val);
1877 break;
1878 case MISCREG_CNTP_CTL:
1879 case MISCREG_CNTP_CTL_EL0:
1880 getArchTimer(tc, tc->cpuId())->setControl(val);
1881 break;
1882 // PL1 phys. timer, secure
1883 // AArch64
1884 case MISCREG_CNTPS_CVAL_EL1:
1885 case MISCREG_CNTPS_TVAL_EL1:
1886 case MISCREG_CNTPS_CTL_EL1:
1887 // PL2 phys. timer, non-secure
1888 // AArch32
1889 case MISCREG_CNTHCTL:
1890 case MISCREG_CNTHP_CVAL:
1891 case MISCREG_CNTHP_TVAL:
1892 case MISCREG_CNTHP_CTL:
1893 // AArch64
1894 case MISCREG_CNTHCTL_EL2:
1895 case MISCREG_CNTHP_CVAL_EL2:
1896 case MISCREG_CNTHP_TVAL_EL2:
1897 case MISCREG_CNTHP_CTL_EL2:
1898 // Virtual timer
1899 // AArch32
1900 case MISCREG_CNTV_CVAL:
1901 case MISCREG_CNTV_TVAL:
1902 case MISCREG_CNTV_CTL:
1903 // AArch64
1904 // case MISCREG_CNTV_CVAL_EL2:
1905 // case MISCREG_CNTV_TVAL_EL2:
1906 // case MISCREG_CNTV_CTL_EL2:
1907 break;
1908 }
1909 }
1910 setMiscRegNoEffect(misc_reg, newVal);
1911}
1912
1913void
1914ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
1915 uint8_t target_el)
1916{
1917 if (haveLargeAsid64)
1918 asid &= mask(8);
1919 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1920 System *sys = tc->getSystemPtr();
1921 for (int x = 0; x < sys->numContexts(); x++) {
1922 ThreadContext *oc = sys->getThreadContext(x);
1923 assert(oc->getITBPtr() && oc->getDTBPtr());
1924 oc->getITBPtr()->flushMvaAsid(va, asid,
1925 secure_lookup, target_el);
1926 oc->getDTBPtr()->flushMvaAsid(va, asid,
1927 secure_lookup, target_el);
1928
1929 CheckerCPU *checker = oc->getCheckerCpuPtr();
1930 if (checker) {
1931 checker->getITBPtr()->flushMvaAsid(
1932 va, asid, secure_lookup, target_el);
1933 checker->getDTBPtr()->flushMvaAsid(
1934 va, asid, secure_lookup, target_el);
1935 }
1936 }
1937}
1938
1939void
1940ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1941{
1942 System *sys = tc->getSystemPtr();
1943 for (int x = 0; x < sys->numContexts(); x++) {
1944 ThreadContext *oc = sys->getThreadContext(x);
1945 assert(oc->getITBPtr() && oc->getDTBPtr());
1946 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1947 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1948
1949 // If CheckerCPU is connected, need to notify it of a flush
1950 CheckerCPU *checker = oc->getCheckerCpuPtr();
1951 if (checker) {
1952 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1953 target_el);
1954 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1955 target_el);
1956 }
1957 }
1958}
1959
1960void
1961ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1962{
1963 System *sys = tc->getSystemPtr();
1964 for (int x = 0; x < sys->numContexts(); x++) {
1965 ThreadContext *oc = sys->getThreadContext(x);
1966 assert(oc->getITBPtr() && oc->getDTBPtr());
1967 oc->getITBPtr()->flushAllNs(hyp, target_el);
1968 oc->getDTBPtr()->flushAllNs(hyp, target_el);
1969
1970 CheckerCPU *checker = oc->getCheckerCpuPtr();
1971 if (checker) {
1972 checker->getITBPtr()->flushAllNs(hyp, target_el);
1973 checker->getDTBPtr()->flushAllNs(hyp, target_el);
1974 }
1975 }
1976}
1977
1978void
1979ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1980 uint8_t target_el)
1981{
1982 System *sys = tc->getSystemPtr();
1983 for (int x = 0; x < sys->numContexts(); x++) {
1984 ThreadContext *oc = sys->getThreadContext(x);
1985 assert(oc->getITBPtr() && oc->getDTBPtr());
1986 oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
1987 secure_lookup, hyp, target_el);
1988 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1989 secure_lookup, hyp, target_el);
1990
1991 CheckerCPU *checker = oc->getCheckerCpuPtr();
1992 if (checker) {
1993 checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
1994 secure_lookup, hyp, target_el);
1995 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1996 secure_lookup, hyp, target_el);
1997 }
1998 }
1999}
2000
2001::GenericTimer::SystemCounter *
2002ISA::getSystemCounter(ThreadContext *tc)
2003{
2004 ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())->
2005 getSystemCounter();
2006 if (cnt == NULL) {
2007 panic("System counter not available\n");
2008 }
2009 return cnt;
2010}
2011
2012::GenericTimer::ArchTimer *
2013ISA::getArchTimer(ThreadContext *tc, int cpu_id)
2014{
2015 ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())->
2016 getArchTimer(cpu_id);
2017 if (timer == NULL) {
2018 panic("Architected timer not available\n");
2019 }
2020 return timer;
2021}
2022
2023}
2024
2025ArmISA::ISA *
2026ArmISAParams::create()
2027{
2028 return new ArmISA::ISA(this);
2029}
| 1694 }
1695 break;
1696 case MISCREG_DAIF:
1697 {
1698 CPSR cpsr = miscRegs[MISCREG_CPSR];
1699 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1700 newVal = cpsr;
1701 misc_reg = MISCREG_CPSR;
1702 }
1703 break;
1704 case MISCREG_SP_EL0:
1705 tc->setIntReg(INTREG_SP0, newVal);
1706 break;
1707 case MISCREG_SP_EL1:
1708 tc->setIntReg(INTREG_SP1, newVal);
1709 break;
1710 case MISCREG_SP_EL2:
1711 tc->setIntReg(INTREG_SP2, newVal);
1712 break;
1713 case MISCREG_SPSEL:
1714 {
1715 CPSR cpsr = miscRegs[MISCREG_CPSR];
1716 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1717 newVal = cpsr;
1718 misc_reg = MISCREG_CPSR;
1719 }
1720 break;
1721 case MISCREG_CURRENTEL:
1722 {
1723 CPSR cpsr = miscRegs[MISCREG_CPSR];
1724 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1725 newVal = cpsr;
1726 misc_reg = MISCREG_CPSR;
1727 }
1728 break;
1729 case MISCREG_AT_S1E1R_Xt:
1730 case MISCREG_AT_S1E1W_Xt:
1731 case MISCREG_AT_S1E0R_Xt:
1732 case MISCREG_AT_S1E0W_Xt:
1733 case MISCREG_AT_S1E2R_Xt:
1734 case MISCREG_AT_S1E2W_Xt:
1735 case MISCREG_AT_S12E1R_Xt:
1736 case MISCREG_AT_S12E1W_Xt:
1737 case MISCREG_AT_S12E0R_Xt:
1738 case MISCREG_AT_S12E0W_Xt:
1739 case MISCREG_AT_S1E3R_Xt:
1740 case MISCREG_AT_S1E3W_Xt:
1741 {
1742 RequestPtr req = new Request;
1743 unsigned flags = 0;
1744 BaseTLB::Mode mode = BaseTLB::Read;
1745 TLB::ArmTranslationType tranType = TLB::NormalTran;
1746 Fault fault;
1747 switch(misc_reg) {
1748 case MISCREG_AT_S1E1R_Xt:
1749 flags = TLB::MustBeOne;
1750 tranType = TLB::S1CTran;
1751 mode = BaseTLB::Read;
1752 break;
1753 case MISCREG_AT_S1E1W_Xt:
1754 flags = TLB::MustBeOne;
1755 tranType = TLB::S1CTran;
1756 mode = BaseTLB::Write;
1757 break;
1758 case MISCREG_AT_S1E0R_Xt:
1759 flags = TLB::MustBeOne | TLB::UserMode;
1760 tranType = TLB::S1CTran;
1761 mode = BaseTLB::Read;
1762 break;
1763 case MISCREG_AT_S1E0W_Xt:
1764 flags = TLB::MustBeOne | TLB::UserMode;
1765 tranType = TLB::S1CTran;
1766 mode = BaseTLB::Write;
1767 break;
1768 case MISCREG_AT_S1E2R_Xt:
1769 flags = TLB::MustBeOne;
1770 tranType = TLB::HypMode;
1771 mode = BaseTLB::Read;
1772 break;
1773 case MISCREG_AT_S1E2W_Xt:
1774 flags = TLB::MustBeOne;
1775 tranType = TLB::HypMode;
1776 mode = BaseTLB::Write;
1777 break;
1778 case MISCREG_AT_S12E0R_Xt:
1779 flags = TLB::MustBeOne | TLB::UserMode;
1780 tranType = TLB::S1S2NsTran;
1781 mode = BaseTLB::Read;
1782 break;
1783 case MISCREG_AT_S12E0W_Xt:
1784 flags = TLB::MustBeOne | TLB::UserMode;
1785 tranType = TLB::S1S2NsTran;
1786 mode = BaseTLB::Write;
1787 break;
1788 case MISCREG_AT_S12E1R_Xt:
1789 flags = TLB::MustBeOne;
1790 tranType = TLB::S1S2NsTran;
1791 mode = BaseTLB::Read;
1792 break;
1793 case MISCREG_AT_S12E1W_Xt:
1794 flags = TLB::MustBeOne;
1795 tranType = TLB::S1S2NsTran;
1796 mode = BaseTLB::Write;
1797 break;
1798 case MISCREG_AT_S1E3R_Xt:
1799 flags = TLB::MustBeOne;
1800 tranType = TLB::HypMode; // There is no TZ mode defined.
1801 mode = BaseTLB::Read;
1802 break;
1803 case MISCREG_AT_S1E3W_Xt:
1804 flags = TLB::MustBeOne;
1805 tranType = TLB::HypMode; // There is no TZ mode defined.
1806 mode = BaseTLB::Write;
1807 break;
1808 }
1809 // If we're in timing mode then doing the translation in
1810 // functional mode then we're slightly distorting performance
1811 // results obtained from simulations. The translation should be
1812 // done in the same mode the core is running in. NOTE: This
1813 // can't be an atomic translation because that causes problems
1814 // with unexpected atomic snoop requests.
1815 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1816 req->setVirt(0, val, 1, flags, Request::funcMasterId,
1817 tc->pcState().pc());
1818 req->setThreadContext(tc->contextId(), tc->threadId());
1819 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1820 tranType);
1821
1822 MiscReg newVal;
1823 if (fault == NoFault) {
1824 Addr paddr = req->getPaddr();
1825 uint64_t attr = tc->getDTBPtr()->getAttr();
1826 uint64_t attr1 = attr >> 56;
1827 if (!attr1 || attr1 ==0x44) {
1828 attr |= 0x100;
1829 attr &= ~ uint64_t(0x80);
1830 }
1831 newVal = (paddr & mask(47, 12)) | attr;
1832 DPRINTF(MiscRegs,
1833 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1834 val, newVal);
1835 } else {
1836 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1837 // Set fault bit and FSR
1838 FSR fsr = armFault->getFsr(tc);
1839
1840 newVal = ((fsr >> 9) & 1) << 11;
1841 // rearange fault status
1842 newVal |= ((fsr >> 0) & 0x3f) << 1;
1843 newVal |= 0x1; // F bit
1844 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1845 newVal |= armFault->isStage2() ? 0x200 : 0;
1846 DPRINTF(MiscRegs,
1847 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1848 val, fsr, newVal);
1849 }
1850 delete req;
1851 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1852 return;
1853 }
1854 case MISCREG_SPSR_EL3:
1855 case MISCREG_SPSR_EL2:
1856 case MISCREG_SPSR_EL1:
1857 // Force bits 23:21 to 0
1858 newVal = val & ~(0x7 << 21);
1859 break;
1860 case MISCREG_L2CTLR:
1861 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1862 miscRegName[misc_reg], uint32_t(val));
1863 break;
1864
1865 // Generic Timer registers
1866 case MISCREG_CNTFRQ:
1867 case MISCREG_CNTFRQ_EL0:
1868 getSystemCounter(tc)->setFreq(val);
1869 break;
1870 case MISCREG_CNTP_CVAL:
1871 case MISCREG_CNTP_CVAL_EL0:
1872 getArchTimer(tc, tc->cpuId())->setCompareValue(val);
1873 break;
1874 case MISCREG_CNTP_TVAL:
1875 case MISCREG_CNTP_TVAL_EL0:
1876 getArchTimer(tc, tc->cpuId())->setTimerValue(val);
1877 break;
1878 case MISCREG_CNTP_CTL:
1879 case MISCREG_CNTP_CTL_EL0:
1880 getArchTimer(tc, tc->cpuId())->setControl(val);
1881 break;
1882 // PL1 phys. timer, secure
1883 // AArch64
1884 case MISCREG_CNTPS_CVAL_EL1:
1885 case MISCREG_CNTPS_TVAL_EL1:
1886 case MISCREG_CNTPS_CTL_EL1:
1887 // PL2 phys. timer, non-secure
1888 // AArch32
1889 case MISCREG_CNTHCTL:
1890 case MISCREG_CNTHP_CVAL:
1891 case MISCREG_CNTHP_TVAL:
1892 case MISCREG_CNTHP_CTL:
1893 // AArch64
1894 case MISCREG_CNTHCTL_EL2:
1895 case MISCREG_CNTHP_CVAL_EL2:
1896 case MISCREG_CNTHP_TVAL_EL2:
1897 case MISCREG_CNTHP_CTL_EL2:
1898 // Virtual timer
1899 // AArch32
1900 case MISCREG_CNTV_CVAL:
1901 case MISCREG_CNTV_TVAL:
1902 case MISCREG_CNTV_CTL:
1903 // AArch64
1904 // case MISCREG_CNTV_CVAL_EL2:
1905 // case MISCREG_CNTV_TVAL_EL2:
1906 // case MISCREG_CNTV_CTL_EL2:
1907 break;
1908 }
1909 }
1910 setMiscRegNoEffect(misc_reg, newVal);
1911}
1912
1913void
1914ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
1915 uint8_t target_el)
1916{
1917 if (haveLargeAsid64)
1918 asid &= mask(8);
1919 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1920 System *sys = tc->getSystemPtr();
1921 for (int x = 0; x < sys->numContexts(); x++) {
1922 ThreadContext *oc = sys->getThreadContext(x);
1923 assert(oc->getITBPtr() && oc->getDTBPtr());
1924 oc->getITBPtr()->flushMvaAsid(va, asid,
1925 secure_lookup, target_el);
1926 oc->getDTBPtr()->flushMvaAsid(va, asid,
1927 secure_lookup, target_el);
1928
1929 CheckerCPU *checker = oc->getCheckerCpuPtr();
1930 if (checker) {
1931 checker->getITBPtr()->flushMvaAsid(
1932 va, asid, secure_lookup, target_el);
1933 checker->getDTBPtr()->flushMvaAsid(
1934 va, asid, secure_lookup, target_el);
1935 }
1936 }
1937}
1938
1939void
1940ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1941{
1942 System *sys = tc->getSystemPtr();
1943 for (int x = 0; x < sys->numContexts(); x++) {
1944 ThreadContext *oc = sys->getThreadContext(x);
1945 assert(oc->getITBPtr() && oc->getDTBPtr());
1946 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1947 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1948
1949 // If CheckerCPU is connected, need to notify it of a flush
1950 CheckerCPU *checker = oc->getCheckerCpuPtr();
1951 if (checker) {
1952 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1953 target_el);
1954 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1955 target_el);
1956 }
1957 }
1958}
1959
1960void
1961ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1962{
1963 System *sys = tc->getSystemPtr();
1964 for (int x = 0; x < sys->numContexts(); x++) {
1965 ThreadContext *oc = sys->getThreadContext(x);
1966 assert(oc->getITBPtr() && oc->getDTBPtr());
1967 oc->getITBPtr()->flushAllNs(hyp, target_el);
1968 oc->getDTBPtr()->flushAllNs(hyp, target_el);
1969
1970 CheckerCPU *checker = oc->getCheckerCpuPtr();
1971 if (checker) {
1972 checker->getITBPtr()->flushAllNs(hyp, target_el);
1973 checker->getDTBPtr()->flushAllNs(hyp, target_el);
1974 }
1975 }
1976}
1977
1978void
1979ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1980 uint8_t target_el)
1981{
1982 System *sys = tc->getSystemPtr();
1983 for (int x = 0; x < sys->numContexts(); x++) {
1984 ThreadContext *oc = sys->getThreadContext(x);
1985 assert(oc->getITBPtr() && oc->getDTBPtr());
1986 oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
1987 secure_lookup, hyp, target_el);
1988 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1989 secure_lookup, hyp, target_el);
1990
1991 CheckerCPU *checker = oc->getCheckerCpuPtr();
1992 if (checker) {
1993 checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
1994 secure_lookup, hyp, target_el);
1995 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1996 secure_lookup, hyp, target_el);
1997 }
1998 }
1999}
2000
2001::GenericTimer::SystemCounter *
2002ISA::getSystemCounter(ThreadContext *tc)
2003{
2004 ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())->
2005 getSystemCounter();
2006 if (cnt == NULL) {
2007 panic("System counter not available\n");
2008 }
2009 return cnt;
2010}
2011
2012::GenericTimer::ArchTimer *
2013ISA::getArchTimer(ThreadContext *tc, int cpu_id)
2014{
2015 ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())->
2016 getArchTimer(cpu_id);
2017 if (timer == NULL) {
2018 panic("Architected timer not available\n");
2019 }
2020 return timer;
2021}
2022
2023}
2024
2025ArmISA::ISA *
2026ArmISAParams::create()
2027{
2028 return new ArmISA::ISA(this);
2029}
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