isa.cc (7427:1267715c2112) | isa.cc (7436:b578349f9371) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 103 unchanged lines hidden (view full) --- 112 mvfr1.advSimdInteger = 1; 113 mvfr1.advSimdSinglePrecision = 1; 114 mvfr1.advSimdHalfPrecision = 1; 115 mvfr1.vfpHalfPrecision = 1; 116 miscRegs[MISCREG_MVFR1] = mvfr1; 117 118 miscRegs[MISCREG_MPIDR] = 0; 119 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 103 unchanged lines hidden (view full) --- 112 mvfr1.advSimdInteger = 1; 113 mvfr1.advSimdSinglePrecision = 1; 114 mvfr1.advSimdHalfPrecision = 1; 115 mvfr1.vfpHalfPrecision = 1; 116 miscRegs[MISCREG_MVFR1] = mvfr1; 117 118 miscRegs[MISCREG_MPIDR] = 0; 119 |
120 // Reset values of PRRR and NMRR are implementation dependent 121 122 miscRegs[MISCREG_PRRR] = 123 (1 << 19) | // 19 124 (0 << 18) | // 18 125 (0 << 17) | // 17 126 (1 << 16) | // 16 127 (2 << 14) | // 15:14 128 (0 << 12) | // 13:12 129 (2 << 10) | // 11:10 130 (2 << 8) | // 9:8 131 (2 << 6) | // 7:6 132 (2 << 4) | // 5:4 133 (1 << 2) | // 3:2 134 0; // 1:0 135 miscRegs[MISCREG_NMRR] = 136 (1 << 30) | // 31:30 137 (0 << 26) | // 27:26 138 (0 << 24) | // 25:24 139 (3 << 22) | // 23:22 140 (2 << 20) | // 21:20 141 (0 << 18) | // 19:18 142 (0 << 16) | // 17:16 143 (1 << 14) | // 15:14 144 (0 << 12) | // 13:12 145 (2 << 10) | // 11:10 146 (0 << 8) | // 9:8 147 (3 << 6) | // 7:6 148 (2 << 4) | // 5:4 149 (0 << 2) | // 3:2 150 0; // 1:0 151 |
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120 //XXX We need to initialize the rest of the state. 121} 122 123MiscReg 124ISA::readMiscRegNoEffect(int misc_reg) 125{ 126 assert(misc_reg < NumMiscRegs); 127 if (misc_reg == MISCREG_SPSR) { --- 229 unchanged lines hidden (view full) --- 357 bits(newVal, 7,0)); 358 return; 359 case MISCREG_ITLBIASID: 360 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 361 return; 362 case MISCREG_DTLBIASID: 363 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 364 return; | 152 //XXX We need to initialize the rest of the state. 153} 154 155MiscReg 156ISA::readMiscRegNoEffect(int misc_reg) 157{ 158 assert(misc_reg < NumMiscRegs); 159 if (misc_reg == MISCREG_SPSR) { --- 229 unchanged lines hidden (view full) --- 389 bits(newVal, 7,0)); 390 return; 391 case MISCREG_ITLBIASID: 392 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 393 return; 394 case MISCREG_DTLBIASID: 395 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 396 return; |
397 case MISCREG_V2PCWPR: 398 case MISCREG_V2PCWPW: 399 case MISCREG_V2PCWUR: 400 case MISCREG_V2PCWUW: 401 case MISCREG_V2POWPR: 402 case MISCREG_V2POWPW: 403 case MISCREG_V2POWUR: 404 case MISCREG_V2POWUW: 405 { 406 RequestPtr req = new Request; 407 unsigned flags; 408 BaseTLB::Mode mode; 409 Fault fault; 410 switch(misc_reg) { 411 case MISCREG_V2PCWPR: 412 flags = TLB::MustBeOne; 413 mode = BaseTLB::Read; 414 break; 415 case MISCREG_V2PCWPW: 416 flags = TLB::MustBeOne; 417 mode = BaseTLB::Write; 418 break; 419 case MISCREG_V2PCWUR: 420 flags = TLB::MustBeOne | TLB::UserMode; 421 mode = BaseTLB::Read; 422 break; 423 case MISCREG_V2PCWUW: 424 flags = TLB::MustBeOne | TLB::UserMode; 425 mode = BaseTLB::Write; 426 break; 427 case MISCREG_V2POWPR: 428 case MISCREG_V2POWPW: 429 case MISCREG_V2POWUR: 430 case MISCREG_V2POWUW: 431 panic("Security Extensions not implemented!"); 432 } 433 req->setVirt(0, val, 1, flags, tc->readPC()); 434 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 435 if (fault == NoFault) { 436 miscRegs[MISCREG_PAR] = 437 (req->getPaddr() & 0xfffff000) | 438 (tc->getDTBPtr()->getAttr() ); 439 DPRINTF(MiscRegs, 440 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 441 val, miscRegs[MISCREG_PAR]); 442 } 443 else { 444 // Set fault bit and FSR 445 FSR fsr = miscRegs[MISCREG_DFSR]; 446 miscRegs[MISCREG_PAR] = 447 (fsr.ext << 6) | 448 (fsr.fsHigh << 5) | 449 (fsr.fsLow << 1) | 450 0x1; // F bit 451 } 452 return; 453 } |
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365 } 366 } 367 setMiscRegNoEffect(misc_reg, newVal); 368} 369 370} | 454 } 455 } 456 setMiscRegNoEffect(misc_reg, newVal); 457} 458 459} |