isa.cc (13114:777d445423d6) | isa.cc (13116:d3c3e2533928) |
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1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 305 unchanged lines hidden (view full) --- 314 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 315 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 316 317 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 318 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 319 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 320 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 321 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 305 unchanged lines hidden (view full) --- 314 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 315 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 316 317 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 318 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 319 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 320 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 321 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; |
322 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; |
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322 323 miscRegs[MISCREG_ID_DFR0_EL1] = 324 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 325 326 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 327 328 // Enforce consistency with system-level settings... 329 --- 667 unchanged lines hidden (view full) --- 997 case MISCREG_ID_AA64AFR0_EL1: 998 case MISCREG_ID_AA64AFR1_EL1: 999 case MISCREG_ID_AA64DFR0_EL1: 1000 case MISCREG_ID_AA64DFR1_EL1: 1001 case MISCREG_ID_AA64ISAR0_EL1: 1002 case MISCREG_ID_AA64ISAR1_EL1: 1003 case MISCREG_ID_AA64MMFR0_EL1: 1004 case MISCREG_ID_AA64MMFR1_EL1: | 323 324 miscRegs[MISCREG_ID_DFR0_EL1] = 325 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 326 327 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 328 329 // Enforce consistency with system-level settings... 330 --- 667 unchanged lines hidden (view full) --- 998 case MISCREG_ID_AA64AFR0_EL1: 999 case MISCREG_ID_AA64AFR1_EL1: 1000 case MISCREG_ID_AA64DFR0_EL1: 1001 case MISCREG_ID_AA64DFR1_EL1: 1002 case MISCREG_ID_AA64ISAR0_EL1: 1003 case MISCREG_ID_AA64ISAR1_EL1: 1004 case MISCREG_ID_AA64MMFR0_EL1: 1005 case MISCREG_ID_AA64MMFR1_EL1: |
1006 case MISCREG_ID_AA64MMFR2_EL1: |
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1005 case MISCREG_ID_AA64PFR0_EL1: 1006 case MISCREG_ID_AA64PFR1_EL1: 1007 // ID registers are constants. 1008 return; 1009 1010 // TLB Invalidate All 1011 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1012 { --- 972 unchanged lines hidden --- | 1007 case MISCREG_ID_AA64PFR0_EL1: 1008 case MISCREG_ID_AA64PFR1_EL1: 1009 // ID registers are constants. 1010 return; 1011 1012 // TLB Invalidate All 1013 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1014 { --- 972 unchanged lines hidden --- |