isa.cc (12749:223c83ed9979) | isa.cc (12763:37c243ed1112) |
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1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 690 unchanged lines hidden (view full) --- 699 getDTBPtr(tc)->invalidateMiscReg(); 700 } 701 702 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 703 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 704 PCState pc = tc->pcState(); 705 pc.nextThumb(cpsr.t); 706 pc.nextJazelle(cpsr.j); | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 690 unchanged lines hidden (view full) --- 699 getDTBPtr(tc)->invalidateMiscReg(); 700 } 701 702 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 703 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 704 PCState pc = tc->pcState(); 705 pc.nextThumb(cpsr.t); 706 pc.nextJazelle(cpsr.j); |
707 pc.illegalExec(cpsr.il == 1); |
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707 708 // Follow slightly different semantics if a CheckerCPU object 709 // is connected 710 CheckerCPU *checker = tc->getCheckerCpuPtr(); 711 if (checker) { 712 tc->pcStateNoRecord(pc); 713 } else { 714 tc->pcState(pc); --- 1237 unchanged lines hidden --- | 708 709 // Follow slightly different semantics if a CheckerCPU object 710 // is connected 711 CheckerCPU *checker = tc->getCheckerCpuPtr(); 712 if (checker) { 713 tc->pcStateNoRecord(pc); 714 } else { 715 tc->pcState(pc); --- 1237 unchanged lines hidden --- |