1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/system.hh"
43#include "cpu/checker/cpu.hh"
44#include "debug/Arm.hh"
45#include "debug/MiscRegs.hh"
46#include "params/ArmISA.hh"
47#include "sim/faults.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51namespace ArmISA
52{
53
54ISA::ISA(Params *p)
55 : SimObject(p)
56{
57 SCTLR sctlr;
58 sctlr = 0;
59 miscRegs[MISCREG_SCTLR_RST] = sctlr;
60 clear();
61}
62
63const ArmISAParams *
64ISA::params() const
65{
66 return dynamic_cast<const Params *>(_params);
67}
68
69void
70ISA::clear()
71{
72 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
73 uint32_t midr = miscRegs[MISCREG_MIDR];
74 memset(miscRegs, 0, sizeof(miscRegs));
75 CPSR cpsr = 0;
76 cpsr.mode = MODE_USER;
77 miscRegs[MISCREG_CPSR] = cpsr;
78 updateRegMap(cpsr);
79
80 SCTLR sctlr = 0;
81 sctlr.te = (bool)sctlr_rst.te;
82 sctlr.nmfi = (bool)sctlr_rst.nmfi;
83 sctlr.v = (bool)sctlr_rst.v;
84 sctlr.u = 1;
85 sctlr.xp = 1;
86 sctlr.rao2 = 1;
87 sctlr.rao3 = 1;
88 sctlr.rao4 = 1;
89 miscRegs[MISCREG_SCTLR] = sctlr;
90 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
91
92 // Preserve MIDR across reset
93 miscRegs[MISCREG_MIDR] = midr;
94
95 /* Start with an event in the mailbox */
96 miscRegs[MISCREG_SEV_MAILBOX] = 1;
97
98 // Separate Instruction and Data TLBs.
99 miscRegs[MISCREG_TLBTR] = 1;
100
101 MVFR0 mvfr0 = 0;
102 mvfr0.advSimdRegisters = 2;
103 mvfr0.singlePrecision = 2;
104 mvfr0.doublePrecision = 2;
105 mvfr0.vfpExceptionTrapping = 0;
106 mvfr0.divide = 1;
107 mvfr0.squareRoot = 1;
108 mvfr0.shortVectors = 1;
109 mvfr0.roundingModes = 1;
110 miscRegs[MISCREG_MVFR0] = mvfr0;
111
112 MVFR1 mvfr1 = 0;
113 mvfr1.flushToZero = 1;
114 mvfr1.defaultNaN = 1;
115 mvfr1.advSimdLoadStore = 1;
116 mvfr1.advSimdInteger = 1;
117 mvfr1.advSimdSinglePrecision = 1;
118 mvfr1.advSimdHalfPrecision = 1;
119 mvfr1.vfpHalfPrecision = 1;
120 miscRegs[MISCREG_MVFR1] = mvfr1;
121
122 // Reset values of PRRR and NMRR are implementation dependent
123
124 miscRegs[MISCREG_PRRR] =
125 (1 << 19) | // 19
126 (0 << 18) | // 18
127 (0 << 17) | // 17
128 (1 << 16) | // 16
129 (2 << 14) | // 15:14
130 (0 << 12) | // 13:12
131 (2 << 10) | // 11:10
132 (2 << 8) | // 9:8
133 (2 << 6) | // 7:6
134 (2 << 4) | // 5:4
135 (1 << 2) | // 3:2
136 0; // 1:0
137 miscRegs[MISCREG_NMRR] =
138 (1 << 30) | // 31:30
139 (0 << 26) | // 27:26
140 (0 << 24) | // 25:24
141 (3 << 22) | // 23:22
142 (2 << 20) | // 21:20
143 (0 << 18) | // 19:18
144 (0 << 16) | // 17:16
145 (1 << 14) | // 15:14
146 (0 << 12) | // 13:12
147 (2 << 10) | // 11:10
148 (0 << 8) | // 9:8
149 (3 << 6) | // 7:6
150 (2 << 4) | // 5:4
151 (0 << 2) | // 3:2
152 0; // 1:0
153
154 miscRegs[MISCREG_CPACR] = 0;
155 miscRegs[MISCREG_FPSID] = 0x410430A0;
156
157 // See section B4.1.84 of ARM ARM
158 // All values are latest for ARMv7-A profile
159 miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
160 miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
161 miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
162 miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
163 miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
164 miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
165
166 //XXX We need to initialize the rest of the state.
167}
168
169MiscReg
170ISA::readMiscRegNoEffect(int misc_reg)
171{
172 assert(misc_reg < NumMiscRegs);
173
174 int flat_idx;
175 if (misc_reg == MISCREG_SPSR)
176 flat_idx = flattenMiscIndex(misc_reg);
177 else
178 flat_idx = misc_reg;
179 MiscReg val = miscRegs[flat_idx];
180
181 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
182 misc_reg, flat_idx, val);
183 return val;
184}
185
186
187MiscReg
188ISA::readMiscReg(int misc_reg, ThreadContext *tc)
189{
190 ArmSystem *arm_sys;
191
192 if (misc_reg == MISCREG_CPSR) {
193 CPSR cpsr = miscRegs[misc_reg];
194 PCState pc = tc->pcState();
195 cpsr.j = pc.jazelle() ? 1 : 0;
196 cpsr.t = pc.thumb() ? 1 : 0;
197 return cpsr;
198 }
199 if (misc_reg >= MISCREG_CP15_UNIMP_START)
200 panic("Unimplemented CP15 register %s read.\n",
201 miscRegName[misc_reg]);
202
203 switch (misc_reg) {
204 case MISCREG_MPIDR:
205 arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr());
206 assert(arm_sys);
207
208 if (arm_sys->multiProc) {
209 return 0x80000000 | // multiprocessor extensions available
210 tc->cpuId();
211 } else {
212 return 0x80000000 | // multiprocessor extensions available
213 0x40000000 | // in up system
214 tc->cpuId();
215 }
216 break;
217 case MISCREG_ID_MMFR0:
218 return 0x03; // VMSAv7 support
219 case MISCREG_ID_MMFR2:
220 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
221 // | all TLB maintenance | no Harvard
222 case MISCREG_ID_MMFR3:
223 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
224 // BP Maint | Cache Maint Set/way | Cache Maint MVA
225 case MISCREG_CLIDR:
226 warn_once("The clidr register always reports 0 caches.\n");
227 warn_once("clidr LoUIS field of 0b001 to match current "
228 "ARM implementations.\n");
229 return 0x00200000;
230 case MISCREG_CCSIDR:
231 warn_once("The ccsidr register isn't implemented and "
232 "always reads as 0.\n");
233 break;
234 case MISCREG_ID_PFR0:
235 warn("Returning thumbEE disabled for now since we don't support CP14"
236 "config registers and jumping to ThumbEE vectors\n");
237 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
238 case MISCREG_ID_PFR1:
239 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
240 case MISCREG_CTR:
241 {
242 //all caches have the same line size in gem5
243 //4 byte words in ARM
244 unsigned lineSizeWords =
245 tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
246 unsigned log2LineSizeWords = 0;
247
248 while (lineSizeWords >>= 1) {
249 ++log2LineSizeWords;
250 }
251
252 CTR ctr = 0;
253 //log2 of minimun i-cache line size (words)
254 ctr.iCacheLineSize = log2LineSizeWords;
255 //b11 - gem5 uses pipt
256 ctr.l1IndexPolicy = 0x3;
257 //log2 of minimum d-cache line size (words)
258 ctr.dCacheLineSize = log2LineSizeWords;
259 //log2 of max reservation size (words)
260 ctr.erg = log2LineSizeWords;
261 //log2 of max writeback size (words)
262 ctr.cwg = log2LineSizeWords;
263 //b100 - gem5 format is ARMv7
264 ctr.format = 0x4;
265
266 return ctr;
267 }
268 case MISCREG_ACTLR:
269 warn("Not doing anything for miscreg ACTLR\n");
270 break;
271 case MISCREG_PMCR:
272 case MISCREG_PMCCNTR:
273 case MISCREG_PMSELR:
274 warn("Not doing anything for read to miscreg %s\n",
275 miscRegName[misc_reg]);
276 break;
277 case MISCREG_CPSR_Q:
278 panic("shouldn't be reading this register seperately\n");
279 case MISCREG_FPSCR_QC:
280 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
281 case MISCREG_FPSCR_EXC:
282 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
283 case MISCREG_L2CTLR:
284 {
285 // mostly unimplemented, just set NumCPUs field from sim and return
286 L2CTLR l2ctlr = 0;
287 // b00:1CPU to b11:4CPUs
288 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
289 return l2ctlr;
290 }
291 case MISCREG_DBGDIDR:
292 /* For now just implement the version number.
293 * Return 0 as we don't support debug architecture yet.
294 */
295 return 0;
296 case MISCREG_DBGDSCR_INT:
297 return 0;
298 }
299 return readMiscRegNoEffect(misc_reg);
300}
301
302void
303ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
304{
305 assert(misc_reg < NumMiscRegs);
306
307 int flat_idx;
308 if (misc_reg == MISCREG_SPSR)
309 flat_idx = flattenMiscIndex(misc_reg);
310 else
311 flat_idx = misc_reg;
312 miscRegs[flat_idx] = val;
313
314 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
315 flat_idx, val);
316}
317
318void
319ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
320{
321
322 MiscReg newVal = val;
323 int x;
324 System *sys;
325 ThreadContext *oc;
326
327 if (misc_reg == MISCREG_CPSR) {
328 updateRegMap(val);
329
330
331 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
332 int old_mode = old_cpsr.mode;
333 CPSR cpsr = val;
334 if (old_mode != cpsr.mode) {
335 tc->getITBPtr()->invalidateMiscReg();
336 tc->getDTBPtr()->invalidateMiscReg();
337 }
338
339 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
340 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
341 PCState pc = tc->pcState();
342 pc.nextThumb(cpsr.t);
343 pc.nextJazelle(cpsr.j);
344
345 // Follow slightly different semantics if a CheckerCPU object
346 // is connected
347 CheckerCPU *checker = tc->getCheckerCpuPtr();
348 if (checker) {
349 tc->pcStateNoRecord(pc);
350 } else {
351 tc->pcState(pc);
352 }
353 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
354 misc_reg < MISCREG_CP15_END) {
355 panic("Unimplemented CP15 register %s wrote with %#x.\n",
356 miscRegName[misc_reg], val);
357 } else {
358 switch (misc_reg) {
359 case MISCREG_CPACR:
360 {
361
362 const uint32_t ones = (uint32_t)(-1);
363 CPACR cpacrMask = 0;
364 // Only cp10, cp11, and ase are implemented, nothing else should
365 // be writable
366 cpacrMask.cp10 = ones;
367 cpacrMask.cp11 = ones;
368 cpacrMask.asedis = ones;
369 newVal &= cpacrMask;
370 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
371 miscRegName[misc_reg], newVal);
372 }
373 break;
374 case MISCREG_CSSELR:
375 warn_once("The csselr register isn't implemented.\n");
376 return;
377 case MISCREG_FPSCR:
378 {
379 const uint32_t ones = (uint32_t)(-1);
380 FPSCR fpscrMask = 0;
381 fpscrMask.ioc = ones;
382 fpscrMask.dzc = ones;
383 fpscrMask.ofc = ones;
384 fpscrMask.ufc = ones;
385 fpscrMask.ixc = ones;
386 fpscrMask.idc = ones;
387 fpscrMask.len = ones;
388 fpscrMask.stride = ones;
389 fpscrMask.rMode = ones;
390 fpscrMask.fz = ones;
391 fpscrMask.dn = ones;
392 fpscrMask.ahp = ones;
393 fpscrMask.qc = ones;
394 fpscrMask.v = ones;
395 fpscrMask.c = ones;
396 fpscrMask.z = ones;
397 fpscrMask.n = ones;
398 newVal = (newVal & (uint32_t)fpscrMask) |
399 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
400 tc->getDecoderPtr()->setContext(newVal);
401 }
402 break;
403 case MISCREG_CPSR_Q:
404 {
405 assert(!(newVal & ~CpsrMaskQ));
406 newVal = miscRegs[MISCREG_CPSR] | newVal;
407 misc_reg = MISCREG_CPSR;
408 }
409 break;
410 case MISCREG_FPSCR_QC:
411 {
412 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
413 misc_reg = MISCREG_FPSCR;
414 }
415 break;
416 case MISCREG_FPSCR_EXC:
417 {
418 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
419 misc_reg = MISCREG_FPSCR;
420 }
421 break;
422 case MISCREG_FPEXC:
423 {
424 // vfpv3 architecture, section B.6.1 of DDI04068
425 // bit 29 - valid only if fpexc[31] is 0
426 const uint32_t fpexcMask = 0x60000000;
427 newVal = (newVal & fpexcMask) |
428 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
429 }
430 break;
431 case MISCREG_SCTLR:
432 {
433 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
434 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
435 SCTLR new_sctlr = newVal;
436 new_sctlr.nmfi = (bool)sctlr.nmfi;
437 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
438 tc->getITBPtr()->invalidateMiscReg();
439 tc->getDTBPtr()->invalidateMiscReg();
440
441 // Check if all CPUs are booted with caches enabled
442 // so we can stop enforcing coherency of some kernel
443 // structures manually.
444 sys = tc->getSystemPtr();
445 for (x = 0; x < sys->numContexts(); x++) {
446 oc = sys->getThreadContext(x);
447 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
448 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
449 return;
450 }
451
452 for (x = 0; x < sys->numContexts(); x++) {
453 oc = sys->getThreadContext(x);
454 oc->getDTBPtr()->allCpusCaching();
455 oc->getITBPtr()->allCpusCaching();
456
457 // If CheckerCPU is connected, need to notify it.
458 CheckerCPU *checker = oc->getCheckerCpuPtr();
459 if (checker) {
460 checker->getDTBPtr()->allCpusCaching();
461 checker->getITBPtr()->allCpusCaching();
462 }
463 }
464 return;
465 }
466 case MISCREG_TLBTR:
467 case MISCREG_MVFR0:
468 case MISCREG_MVFR1:
469 case MISCREG_MPIDR:
470 case MISCREG_FPSID:
471 return;
472 case MISCREG_TLBIALLIS:
473 case MISCREG_TLBIALL:
474 sys = tc->getSystemPtr();
475 for (x = 0; x < sys->numContexts(); x++) {
476 oc = sys->getThreadContext(x);
477 assert(oc->getITBPtr() && oc->getDTBPtr());
478 oc->getITBPtr()->flushAll();
479 oc->getDTBPtr()->flushAll();
480
481 // If CheckerCPU is connected, need to notify it of a flush
482 CheckerCPU *checker = oc->getCheckerCpuPtr();
483 if (checker) {
484 checker->getITBPtr()->flushAll();
485 checker->getDTBPtr()->flushAll();
486 }
487 }
488 return;
489 case MISCREG_ITLBIALL:
490 tc->getITBPtr()->flushAll();
491 return;
492 case MISCREG_DTLBIALL:
493 tc->getDTBPtr()->flushAll();
494 return;
495 case MISCREG_TLBIMVAIS:
496 case MISCREG_TLBIMVA:
497 sys = tc->getSystemPtr();
498 for (x = 0; x < sys->numContexts(); x++) {
499 oc = sys->getThreadContext(x);
500 assert(oc->getITBPtr() && oc->getDTBPtr());
501 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
502 bits(newVal, 7,0));
503 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
504 bits(newVal, 7,0));
505
506 CheckerCPU *checker = oc->getCheckerCpuPtr();
507 if (checker) {
508 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
509 bits(newVal, 7,0));
510 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
511 bits(newVal, 7,0));
512 }
513 }
514 return;
515 case MISCREG_TLBIASIDIS:
516 case MISCREG_TLBIASID:
517 sys = tc->getSystemPtr();
518 for (x = 0; x < sys->numContexts(); x++) {
519 oc = sys->getThreadContext(x);
520 assert(oc->getITBPtr() && oc->getDTBPtr());
521 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
522 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
523 CheckerCPU *checker = oc->getCheckerCpuPtr();
524 if (checker) {
525 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
526 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
527 }
528 }
529 return;
530 case MISCREG_TLBIMVAAIS:
531 case MISCREG_TLBIMVAA:
532 sys = tc->getSystemPtr();
533 for (x = 0; x < sys->numContexts(); x++) {
534 oc = sys->getThreadContext(x);
535 assert(oc->getITBPtr() && oc->getDTBPtr());
536 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
537 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
538
539 CheckerCPU *checker = oc->getCheckerCpuPtr();
540 if (checker) {
541 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
542 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
543 }
544 }
545 return;
546 case MISCREG_ITLBIMVA:
547 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
548 bits(newVal, 7,0));
549 return;
550 case MISCREG_DTLBIMVA:
551 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
552 bits(newVal, 7,0));
553 return;
554 case MISCREG_ITLBIASID:
555 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
556 return;
557 case MISCREG_DTLBIASID:
558 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
559 return;
560 case MISCREG_ACTLR:
561 warn("Not doing anything for write of miscreg ACTLR\n");
562 break;
563 case MISCREG_PMCR:
564 {
565 // Performance counters not implemented. Instead, interpret
566 // a reset command to this register to reset the simulator
567 // statistics.
568 // PMCR_E | PMCR_P | PMCR_C
569 const int ResetAndEnableCounters = 0x7;
570 if (newVal == ResetAndEnableCounters) {
571 inform("Resetting all simobject stats\n");
572 Stats::schedStatEvent(false, true);
573 break;
574 }
575 }
576 case MISCREG_PMCCNTR:
577 case MISCREG_PMSELR:
578 warn("Not doing anything for write to miscreg %s\n",
579 miscRegName[misc_reg]);
580 break;
581 case MISCREG_V2PCWPR:
582 case MISCREG_V2PCWPW:
583 case MISCREG_V2PCWUR:
584 case MISCREG_V2PCWUW:
585 case MISCREG_V2POWPR:
586 case MISCREG_V2POWPW:
587 case MISCREG_V2POWUR:
588 case MISCREG_V2POWUW:
589 {
590 RequestPtr req = new Request;
591 unsigned flags;
592 BaseTLB::Mode mode;
593 Fault fault;
594 switch(misc_reg) {
595 case MISCREG_V2PCWPR:
596 flags = TLB::MustBeOne;
597 mode = BaseTLB::Read;
598 break;
599 case MISCREG_V2PCWPW:
600 flags = TLB::MustBeOne;
601 mode = BaseTLB::Write;
602 break;
603 case MISCREG_V2PCWUR:
604 flags = TLB::MustBeOne | TLB::UserMode;
605 mode = BaseTLB::Read;
606 break;
607 case MISCREG_V2PCWUW:
608 flags = TLB::MustBeOne | TLB::UserMode;
609 mode = BaseTLB::Write;
610 break;
611 default:
612 panic("Security Extensions not implemented!");
613 }
614 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
615 req->setVirt(0, val, 1, flags, tc->pcState().pc(),
616 Request::funcMasterId);
617 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
618 if (fault == NoFault) {
619 miscRegs[MISCREG_PAR] =
620 (req->getPaddr() & 0xfffff000) |
621 (tc->getDTBPtr()->getAttr() );
622 DPRINTF(MiscRegs,
623 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
624 val, miscRegs[MISCREG_PAR]);
625 }
626 else {
627 // Set fault bit and FSR
628 FSR fsr = miscRegs[MISCREG_DFSR];
629 miscRegs[MISCREG_PAR] =
630 (fsr.ext << 6) |
631 (fsr.fsHigh << 5) |
632 (fsr.fsLow << 1) |
633 0x1; // F bit
634 }
635 return;
636 }
637 case MISCREG_CONTEXTIDR:
638 case MISCREG_PRRR:
639 case MISCREG_NMRR:
640 case MISCREG_DACR:
641 tc->getITBPtr()->invalidateMiscReg();
642 tc->getDTBPtr()->invalidateMiscReg();
643 break;
644 case MISCREG_CPSR_MODE:
645 // This miscreg is used by copy*Regs to set the CPSR mode
646 // without updating other CPSR variables. It's used to
647 // make sure the register map is in such a state that we can
648 // see all of the registers for the copy.
649 updateRegMap(val);
650 return;
651 case MISCREG_L2CTLR:
652 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
653 miscRegName[misc_reg], uint32_t(val));
654 }
655 }
656 setMiscRegNoEffect(misc_reg, newVal);
657}
658
659}
660
661ArmISA::ISA *
662ArmISAParams::create()
663{
664 return new ArmISA::ISA(this);
665}