1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58
59ISA::ISA(Params *p)
60 : SimObject(p),
61 system(NULL),
62 _decoderFlavour(p->decoderFlavour),
63 _vecRegRenameMode(p->vecRegRenameMode),
64 pmu(p->pmu),
65 impdefAsNop(p->impdef_nop)
66{
67 miscRegs[MISCREG_SCTLR_RST] = 0;
68
69 // Hook up a dummy device if we haven't been configured with a
70 // real PMU. By using a dummy device, we don't need to check that
71 // the PMU exist every time we try to access a PMU register.
72 if (!pmu)
73 pmu = &dummyDevice;
74
75 // Give all ISA devices a pointer to this ISA
76 pmu->setISA(this);
77
78 system = dynamic_cast<ArmSystem *>(p->system);
79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
87 physAddrRange = system->physAddrRange();
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
92 physAddrRange = 32; // dummy value
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();
99}
100
101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
102
103const ArmISAParams *
104ISA::params() const
105{
106 return dynamic_cast<const Params *>(_params);
107}
108
109void
110ISA::clear()
111{
112 const Params *p(params());
113
114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
115 memset(miscRegs, 0, sizeof(miscRegs));
116
117 initID32(p);
118
119 // We always initialize AArch64 ID registers even
120 // if we are in AArch32. This is done since if we
121 // are in SE mode we don't know if our ArmProcess is
122 // AArch32 or AArch64
123 initID64(p);
124
125 if (FullSystem && system->highestELIs64()) {
126 // Initialize AArch64 state
127 clear64(p);
128 return;
129 }
130
131 // Initialize AArch32 state...
132
133 CPSR cpsr = 0;
134 cpsr.mode = MODE_USER;
135 miscRegs[MISCREG_CPSR] = cpsr;
136 updateRegMap(cpsr);
137
138 SCTLR sctlr = 0;
139 sctlr.te = (bool) sctlr_rst.te;
140 sctlr.nmfi = (bool) sctlr_rst.nmfi;
141 sctlr.v = (bool) sctlr_rst.v;
142 sctlr.u = 1;
143 sctlr.xp = 1;
144 sctlr.rao2 = 1;
145 sctlr.rao3 = 1;
146 sctlr.rao4 = 0xf; // SCTLR[6:3]
147 sctlr.uci = 1;
148 sctlr.dze = 1;
149 miscRegs[MISCREG_SCTLR_NS] = sctlr;
150 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
151 miscRegs[MISCREG_HCPTR] = 0;
152
153 // Start with an event in the mailbox
154 miscRegs[MISCREG_SEV_MAILBOX] = 1;
155
156 // Separate Instruction and Data TLBs
157 miscRegs[MISCREG_TLBTR] = 1;
158
159 MVFR0 mvfr0 = 0;
160 mvfr0.advSimdRegisters = 2;
161 mvfr0.singlePrecision = 2;
162 mvfr0.doublePrecision = 2;
163 mvfr0.vfpExceptionTrapping = 0;
164 mvfr0.divide = 1;
165 mvfr0.squareRoot = 1;
166 mvfr0.shortVectors = 1;
167 mvfr0.roundingModes = 1;
168 miscRegs[MISCREG_MVFR0] = mvfr0;
169
170 MVFR1 mvfr1 = 0;
171 mvfr1.flushToZero = 1;
172 mvfr1.defaultNaN = 1;
173 mvfr1.advSimdLoadStore = 1;
174 mvfr1.advSimdInteger = 1;
175 mvfr1.advSimdSinglePrecision = 1;
176 mvfr1.advSimdHalfPrecision = 1;
177 mvfr1.vfpHalfPrecision = 1;
178 miscRegs[MISCREG_MVFR1] = mvfr1;
179
180 // Reset values of PRRR and NMRR are implementation dependent
181
182 // @todo: PRRR and NMRR in secure state?
183 miscRegs[MISCREG_PRRR_NS] =
184 (1 << 19) | // 19
185 (0 << 18) | // 18
186 (0 << 17) | // 17
187 (1 << 16) | // 16
188 (2 << 14) | // 15:14
189 (0 << 12) | // 13:12
190 (2 << 10) | // 11:10
191 (2 << 8) | // 9:8
192 (2 << 6) | // 7:6
193 (2 << 4) | // 5:4
194 (1 << 2) | // 3:2
195 0; // 1:0
196 miscRegs[MISCREG_NMRR_NS] =
197 (1 << 30) | // 31:30
198 (0 << 26) | // 27:26
199 (0 << 24) | // 25:24
200 (3 << 22) | // 23:22
201 (2 << 20) | // 21:20
202 (0 << 18) | // 19:18
203 (0 << 16) | // 17:16
204 (1 << 14) | // 15:14
205 (0 << 12) | // 13:12
206 (2 << 10) | // 11:10
207 (0 << 8) | // 9:8
208 (3 << 6) | // 7:6
209 (2 << 4) | // 5:4
210 (0 << 2) | // 3:2
211 0; // 1:0
212
213 miscRegs[MISCREG_CPACR] = 0;
214
215 miscRegs[MISCREG_FPSID] = p->fpsid;
216
217 if (haveLPAE) {
218 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
219 ttbcr.eae = 0;
220 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
221 // Enforce consistency with system-level settings
222 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
223 }
224
225 if (haveSecurity) {
226 miscRegs[MISCREG_SCTLR_S] = sctlr;
227 miscRegs[MISCREG_SCR] = 0;
228 miscRegs[MISCREG_VBAR_S] = 0;
229 } else {
230 // we're always non-secure
231 miscRegs[MISCREG_SCR] = 1;
232 }
233
234 //XXX We need to initialize the rest of the state.
235}
236
237void
238ISA::clear64(const ArmISAParams *p)
239{
240 CPSR cpsr = 0;
241 Addr rvbar = system->resetAddr64();
242 switch (system->highestEL()) {
243 // Set initial EL to highest implemented EL using associated stack
244 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
245 // value
246 case EL3:
247 cpsr.mode = MODE_EL3H;
248 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
249 break;
250 case EL2:
251 cpsr.mode = MODE_EL2H;
252 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
253 break;
254 case EL1:
255 cpsr.mode = MODE_EL1H;
256 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
257 break;
258 default:
259 panic("Invalid highest implemented exception level");
260 break;
261 }
262
263 // Initialize rest of CPSR
264 cpsr.daif = 0xf; // Mask all interrupts
265 cpsr.ss = 0;
266 cpsr.il = 0;
267 miscRegs[MISCREG_CPSR] = cpsr;
268 updateRegMap(cpsr);
269
270 // Initialize other control registers
271 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
272 if (haveSecurity) {
273 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
274 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
275 } else if (haveVirtualization) {
276 // also MISCREG_SCTLR_EL2 (by mapping)
277 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
278 } else {
279 // also MISCREG_SCTLR_EL1 (by mapping)
280 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
281 // Always non-secure
282 miscRegs[MISCREG_SCR_EL3] = 1;
283 }
284}
285
286void
287ISA::initID32(const ArmISAParams *p)
288{
289 // Initialize configurable default values
290 miscRegs[MISCREG_MIDR] = p->midr;
291 miscRegs[MISCREG_MIDR_EL1] = p->midr;
292 miscRegs[MISCREG_VPIDR] = p->midr;
293
294 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
295 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
296 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
297 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
298 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
299 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
300
301 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
302 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
303 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
304 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
305}
306
307void
308ISA::initID64(const ArmISAParams *p)
309{
310 // Initialize configurable id registers
311 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
312 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
313 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
314 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
315 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
316
317 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
318 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
319 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
320 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
321 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
322 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
323
324 miscRegs[MISCREG_ID_DFR0_EL1] =
325 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
326
327 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
328
329 // Enforce consistency with system-level settings...
330
331 // EL3
332 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
333 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
334 haveSecurity ? 0x2 : 0x0);
335 // EL2
336 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
337 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
338 haveVirtualization ? 0x2 : 0x0);
339 // Large ASID support
340 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
341 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
342 haveLargeAsid64 ? 0x2 : 0x0);
343 // Physical address size
344 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
345 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
346 encodePhysAddrRange64(physAddrRange));
347}
348
349void
350ISA::startup(ThreadContext *tc)
351{
352 pmu->setThreadContext(tc);
353
354}
355
356
357MiscReg
358ISA::readMiscRegNoEffect(int misc_reg) const
359{
360 assert(misc_reg < NumMiscRegs);
361
362 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
363 const auto &map = getMiscIndices(misc_reg);
364 int lower = map.first, upper = map.second;
365 // NB!: apply architectural masks according to desired register,
366 // despite possibly getting value from different (mapped) register.
367 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
368 |(miscRegs[upper] << 32));
369 if (val & reg.res0()) {
370 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
371 miscRegName[misc_reg], val & reg.res0());
372 }
373 if ((val & reg.res1()) != reg.res1()) {
374 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
375 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
376 }
377 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
378}
379
380
381MiscReg
382ISA::readMiscReg(int misc_reg, ThreadContext *tc)
383{
384 CPSR cpsr = 0;
385 PCState pc = 0;
386 SCR scr = 0;
387
388 if (misc_reg == MISCREG_CPSR) {
389 cpsr = miscRegs[misc_reg];
390 pc = tc->pcState();
391 cpsr.j = pc.jazelle() ? 1 : 0;
392 cpsr.t = pc.thumb() ? 1 : 0;
393 return cpsr;
394 }
395
396#ifndef NDEBUG
397 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
398 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
399 warn("Unimplemented system register %s read.\n",
400 miscRegName[misc_reg]);
401 else
402 panic("Unimplemented system register %s read.\n",
403 miscRegName[misc_reg]);
404 }
405#endif
406
407 switch (unflattenMiscReg(misc_reg)) {
408 case MISCREG_HCR:
409 {
410 if (!haveVirtualization)
411 return 0;
412 else
413 return readMiscRegNoEffect(MISCREG_HCR);
414 }
415 case MISCREG_CPACR:
416 {
417 const uint32_t ones = (uint32_t)(-1);
418 CPACR cpacrMask = 0;
419 // Only cp10, cp11, and ase are implemented, nothing else should
420 // be readable? (straight copy from the write code)
421 cpacrMask.cp10 = ones;
422 cpacrMask.cp11 = ones;
423 cpacrMask.asedis = ones;
424
425 // Security Extensions may limit the readability of CPACR
426 if (haveSecurity) {
427 scr = readMiscRegNoEffect(MISCREG_SCR);
428 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
429 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
430 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
431 // NB: Skipping the full loop, here
432 if (!nsacr.cp10) cpacrMask.cp10 = 0;
433 if (!nsacr.cp11) cpacrMask.cp11 = 0;
434 }
435 }
436 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
437 val &= cpacrMask;
438 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
439 miscRegName[misc_reg], val);
440 return val;
441 }
442 case MISCREG_MPIDR:
443 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
444 scr = readMiscRegNoEffect(MISCREG_SCR);
445 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
446 return getMPIDR(system, tc);
447 } else {
448 return readMiscReg(MISCREG_VMPIDR, tc);
449 }
450 break;
451 case MISCREG_MPIDR_EL1:
452 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
453 return getMPIDR(system, tc) & 0xffffffff;
454 case MISCREG_VMPIDR:
455 // top bit defined as RES1
456 return readMiscRegNoEffect(misc_reg) | 0x80000000;
457 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
458 case MISCREG_REVIDR: // not implemented, so alias MIDR
459 case MISCREG_MIDR:
460 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
461 scr = readMiscRegNoEffect(MISCREG_SCR);
462 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
463 return readMiscRegNoEffect(misc_reg);
464 } else {
465 return readMiscRegNoEffect(MISCREG_VPIDR);
466 }
467 break;
468 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
469 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
470 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
471 case MISCREG_AIDR: // AUX ID set to 0
472 case MISCREG_TCMTR: // No TCM's
473 return 0;
474
475 case MISCREG_CLIDR:
476 warn_once("The clidr register always reports 0 caches.\n");
477 warn_once("clidr LoUIS field of 0b001 to match current "
478 "ARM implementations.\n");
479 return 0x00200000;
480 case MISCREG_CCSIDR:
481 warn_once("The ccsidr register isn't implemented and "
482 "always reads as 0.\n");
483 break;
484 case MISCREG_CTR: // AArch32, ARMv7, top bit set
485 case MISCREG_CTR_EL0: // AArch64
486 {
487 //all caches have the same line size in gem5
488 //4 byte words in ARM
489 unsigned lineSizeWords =
490 tc->getSystemPtr()->cacheLineSize() / 4;
491 unsigned log2LineSizeWords = 0;
492
493 while (lineSizeWords >>= 1) {
494 ++log2LineSizeWords;
495 }
496
497 CTR ctr = 0;
498 //log2 of minimun i-cache line size (words)
499 ctr.iCacheLineSize = log2LineSizeWords;
500 //b11 - gem5 uses pipt
501 ctr.l1IndexPolicy = 0x3;
502 //log2 of minimum d-cache line size (words)
503 ctr.dCacheLineSize = log2LineSizeWords;
504 //log2 of max reservation size (words)
505 ctr.erg = log2LineSizeWords;
506 //log2 of max writeback size (words)
507 ctr.cwg = log2LineSizeWords;
508 //b100 - gem5 format is ARMv7
509 ctr.format = 0x4;
510
511 return ctr;
512 }
513 case MISCREG_ACTLR:
514 warn("Not doing anything for miscreg ACTLR\n");
515 break;
516
517 case MISCREG_PMXEVTYPER_PMCCFILTR:
518 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
519 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
520 case MISCREG_PMCR ... MISCREG_PMOVSSET:
521 return pmu->readMiscReg(misc_reg);
522
523 case MISCREG_CPSR_Q:
524 panic("shouldn't be reading this register seperately\n");
525 case MISCREG_FPSCR_QC:
526 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
527 case MISCREG_FPSCR_EXC:
528 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
529 case MISCREG_FPSR:
530 {
531 const uint32_t ones = (uint32_t)(-1);
532 FPSCR fpscrMask = 0;
533 fpscrMask.ioc = ones;
534 fpscrMask.dzc = ones;
535 fpscrMask.ofc = ones;
536 fpscrMask.ufc = ones;
537 fpscrMask.ixc = ones;
538 fpscrMask.idc = ones;
539 fpscrMask.qc = ones;
540 fpscrMask.v = ones;
541 fpscrMask.c = ones;
542 fpscrMask.z = ones;
543 fpscrMask.n = ones;
544 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
545 }
546 case MISCREG_FPCR:
547 {
548 const uint32_t ones = (uint32_t)(-1);
549 FPSCR fpscrMask = 0;
550 fpscrMask.len = ones;
551 fpscrMask.stride = ones;
552 fpscrMask.rMode = ones;
553 fpscrMask.fz = ones;
554 fpscrMask.dn = ones;
555 fpscrMask.ahp = ones;
556 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
557 }
558 case MISCREG_NZCV:
559 {
560 CPSR cpsr = 0;
561 cpsr.nz = tc->readCCReg(CCREG_NZ);
562 cpsr.c = tc->readCCReg(CCREG_C);
563 cpsr.v = tc->readCCReg(CCREG_V);
564 return cpsr;
565 }
566 case MISCREG_DAIF:
567 {
568 CPSR cpsr = 0;
569 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
570 return cpsr;
571 }
572 case MISCREG_SP_EL0:
573 {
574 return tc->readIntReg(INTREG_SP0);
575 }
576 case MISCREG_SP_EL1:
577 {
578 return tc->readIntReg(INTREG_SP1);
579 }
580 case MISCREG_SP_EL2:
581 {
582 return tc->readIntReg(INTREG_SP2);
583 }
584 case MISCREG_SPSEL:
585 {
586 return miscRegs[MISCREG_CPSR] & 0x1;
587 }
588 case MISCREG_CURRENTEL:
589 {
590 return miscRegs[MISCREG_CPSR] & 0xc;
591 }
592 case MISCREG_L2CTLR:
593 {
594 // mostly unimplemented, just set NumCPUs field from sim and return
595 L2CTLR l2ctlr = 0;
596 // b00:1CPU to b11:4CPUs
597 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
598 return l2ctlr;
599 }
600 case MISCREG_DBGDIDR:
601 /* For now just implement the version number.
602 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
603 */
604 return 0x5 << 16;
605 case MISCREG_DBGDSCRint:
606 return 0;
607 case MISCREG_ISR:
608 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
609 readMiscRegNoEffect(MISCREG_HCR),
610 readMiscRegNoEffect(MISCREG_CPSR),
611 readMiscRegNoEffect(MISCREG_SCR));
612 case MISCREG_ISR_EL1:
613 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
614 readMiscRegNoEffect(MISCREG_HCR_EL2),
615 readMiscRegNoEffect(MISCREG_CPSR),
616 readMiscRegNoEffect(MISCREG_SCR_EL3));
617 case MISCREG_DCZID_EL0:
618 return 0x04; // DC ZVA clear 64-byte chunks
619 case MISCREG_HCPTR:
620 {
621 MiscReg val = readMiscRegNoEffect(misc_reg);
622 // The trap bit associated with CP14 is defined as RAZ
623 val &= ~(1 << 14);
624 // If a CP bit in NSACR is 0 then the corresponding bit in
625 // HCPTR is RAO/WI
626 bool secure_lookup = haveSecurity &&
627 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
628 readMiscRegNoEffect(MISCREG_CPSR));
629 if (!secure_lookup) {
630 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
631 val |= (mask ^ 0x7FFF) & 0xBFFF;
632 }
633 // Set the bits for unimplemented coprocessors to RAO/WI
634 val |= 0x33FF;
635 return (val);
636 }
637 case MISCREG_HDFAR: // alias for secure DFAR
638 return readMiscRegNoEffect(MISCREG_DFAR_S);
639 case MISCREG_HIFAR: // alias for secure IFAR
640 return readMiscRegNoEffect(MISCREG_IFAR_S);
641 case MISCREG_HVBAR: // bottom bits reserved
642 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
643 case MISCREG_SCTLR:
644 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
645 case MISCREG_SCTLR_EL1:
646 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
647 case MISCREG_SCTLR_EL2:
648 case MISCREG_SCTLR_EL3:
649 case MISCREG_HSCTLR:
650 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
651
652 case MISCREG_ID_PFR0:
653 // !ThumbEE | !Jazelle | Thumb | ARM
654 return 0x00000031;
655 case MISCREG_ID_PFR1:
656 { // Timer | Virti | !M Profile | TrustZone | ARMv4
657 bool haveTimer = (system->getGenericTimer() != NULL);
658 return 0x00000001
659 | (haveSecurity ? 0x00000010 : 0x0)
660 | (haveVirtualization ? 0x00001000 : 0x0)
661 | (haveTimer ? 0x00010000 : 0x0);
662 }
663 case MISCREG_ID_AA64PFR0_EL1:
664 return 0x0000000000000002 // AArch{64,32} supported at EL0
665 | 0x0000000000000020 // EL1
666 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
667 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
668 case MISCREG_ID_AA64PFR1_EL1:
669 return 0; // bits [63:0] RES0 (reserved for future use)
670
671 // Generic Timer registers
672 case MISCREG_CNTHV_CTL_EL2:
673 case MISCREG_CNTHV_CVAL_EL2:
674 case MISCREG_CNTHV_TVAL_EL2:
675 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
676 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
677 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
678 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
679 return getGenericTimer(tc).readMiscReg(misc_reg);
680
681 default:
682 break;
683
684 }
685 return readMiscRegNoEffect(misc_reg);
686}
687
688void
689ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
690{
691 assert(misc_reg < NumMiscRegs);
692
693 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
694 const auto &map = getMiscIndices(misc_reg);
695 int lower = map.first, upper = map.second;
696
697 auto v = (val & ~reg.wi()) | reg.rao();
698 if (upper > 0) {
699 miscRegs[lower] = bits(v, 31, 0);
700 miscRegs[upper] = bits(v, 63, 32);
701 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
702 misc_reg, lower, upper, v);
703 } else {
704 miscRegs[lower] = v;
705 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
706 misc_reg, lower, v);
707 }
708}
709
710void
711ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
712{
713
714 MiscReg newVal = val;
715 bool secure_lookup;
716 SCR scr;
717
718 if (misc_reg == MISCREG_CPSR) {
719 updateRegMap(val);
720
721
722 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
723 int old_mode = old_cpsr.mode;
724 CPSR cpsr = val;
725 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
726 getITBPtr(tc)->invalidateMiscReg();
727 getDTBPtr(tc)->invalidateMiscReg();
728 }
729
730 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
731 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
732 PCState pc = tc->pcState();
733 pc.nextThumb(cpsr.t);
734 pc.nextJazelle(cpsr.j);
735 pc.illegalExec(cpsr.il == 1);
736
737 // Follow slightly different semantics if a CheckerCPU object
738 // is connected
739 CheckerCPU *checker = tc->getCheckerCpuPtr();
740 if (checker) {
741 tc->pcStateNoRecord(pc);
742 } else {
743 tc->pcState(pc);
744 }
745 } else {
746#ifndef NDEBUG
747 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
748 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
749 warn("Unimplemented system register %s write with %#x.\n",
750 miscRegName[misc_reg], val);
751 else
752 panic("Unimplemented system register %s write with %#x.\n",
753 miscRegName[misc_reg], val);
754 }
755#endif
756 switch (unflattenMiscReg(misc_reg)) {
757 case MISCREG_CPACR:
758 {
759
760 const uint32_t ones = (uint32_t)(-1);
761 CPACR cpacrMask = 0;
762 // Only cp10, cp11, and ase are implemented, nothing else should
763 // be writable
764 cpacrMask.cp10 = ones;
765 cpacrMask.cp11 = ones;
766 cpacrMask.asedis = ones;
767
768 // Security Extensions may limit the writability of CPACR
769 if (haveSecurity) {
770 scr = readMiscRegNoEffect(MISCREG_SCR);
771 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
772 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
773 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
774 // NB: Skipping the full loop, here
775 if (!nsacr.cp10) cpacrMask.cp10 = 0;
776 if (!nsacr.cp11) cpacrMask.cp11 = 0;
777 }
778 }
779
780 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
781 newVal &= cpacrMask;
782 newVal |= old_val & ~cpacrMask;
783 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
784 miscRegName[misc_reg], newVal);
785 }
786 break;
787 case MISCREG_CPTR_EL2:
788 {
789 const uint32_t ones = (uint32_t)(-1);
790 CPTR cptrMask = 0;
791 cptrMask.tcpac = ones;
792 cptrMask.tta = ones;
793 cptrMask.tfp = ones;
794 newVal &= cptrMask;
795 cptrMask = 0;
796 cptrMask.res1_13_12_el2 = ones;
797 cptrMask.res1_9_0_el2 = ones;
798 newVal |= cptrMask;
799 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
800 miscRegName[misc_reg], newVal);
801 }
802 break;
803 case MISCREG_CPTR_EL3:
804 {
805 const uint32_t ones = (uint32_t)(-1);
806 CPTR cptrMask = 0;
807 cptrMask.tcpac = ones;
808 cptrMask.tta = ones;
809 cptrMask.tfp = ones;
810 newVal &= cptrMask;
811 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
812 miscRegName[misc_reg], newVal);
813 }
814 break;
815 case MISCREG_CSSELR:
816 warn_once("The csselr register isn't implemented.\n");
817 return;
818
819 case MISCREG_DC_ZVA_Xt:
820 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
821 return;
822
823 case MISCREG_FPSCR:
824 {
825 const uint32_t ones = (uint32_t)(-1);
826 FPSCR fpscrMask = 0;
827 fpscrMask.ioc = ones;
828 fpscrMask.dzc = ones;
829 fpscrMask.ofc = ones;
830 fpscrMask.ufc = ones;
831 fpscrMask.ixc = ones;
832 fpscrMask.idc = ones;
833 fpscrMask.ioe = ones;
834 fpscrMask.dze = ones;
835 fpscrMask.ofe = ones;
836 fpscrMask.ufe = ones;
837 fpscrMask.ixe = ones;
838 fpscrMask.ide = ones;
839 fpscrMask.len = ones;
840 fpscrMask.stride = ones;
841 fpscrMask.rMode = ones;
842 fpscrMask.fz = ones;
843 fpscrMask.dn = ones;
844 fpscrMask.ahp = ones;
845 fpscrMask.qc = ones;
846 fpscrMask.v = ones;
847 fpscrMask.c = ones;
848 fpscrMask.z = ones;
849 fpscrMask.n = ones;
850 newVal = (newVal & (uint32_t)fpscrMask) |
851 (readMiscRegNoEffect(MISCREG_FPSCR) &
852 ~(uint32_t)fpscrMask);
853 tc->getDecoderPtr()->setContext(newVal);
854 }
855 break;
856 case MISCREG_FPSR:
857 {
858 const uint32_t ones = (uint32_t)(-1);
859 FPSCR fpscrMask = 0;
860 fpscrMask.ioc = ones;
861 fpscrMask.dzc = ones;
862 fpscrMask.ofc = ones;
863 fpscrMask.ufc = ones;
864 fpscrMask.ixc = ones;
865 fpscrMask.idc = ones;
866 fpscrMask.qc = ones;
867 fpscrMask.v = ones;
868 fpscrMask.c = ones;
869 fpscrMask.z = ones;
870 fpscrMask.n = ones;
871 newVal = (newVal & (uint32_t)fpscrMask) |
872 (readMiscRegNoEffect(MISCREG_FPSCR) &
873 ~(uint32_t)fpscrMask);
874 misc_reg = MISCREG_FPSCR;
875 }
876 break;
877 case MISCREG_FPCR:
878 {
879 const uint32_t ones = (uint32_t)(-1);
880 FPSCR fpscrMask = 0;
881 fpscrMask.len = ones;
882 fpscrMask.stride = ones;
883 fpscrMask.rMode = ones;
884 fpscrMask.fz = ones;
885 fpscrMask.dn = ones;
886 fpscrMask.ahp = ones;
887 newVal = (newVal & (uint32_t)fpscrMask) |
888 (readMiscRegNoEffect(MISCREG_FPSCR) &
889 ~(uint32_t)fpscrMask);
890 misc_reg = MISCREG_FPSCR;
891 }
892 break;
893 case MISCREG_CPSR_Q:
894 {
895 assert(!(newVal & ~CpsrMaskQ));
896 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
897 misc_reg = MISCREG_CPSR;
898 }
899 break;
900 case MISCREG_FPSCR_QC:
901 {
902 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
903 (newVal & FpscrQcMask);
904 misc_reg = MISCREG_FPSCR;
905 }
906 break;
907 case MISCREG_FPSCR_EXC:
908 {
909 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
910 (newVal & FpscrExcMask);
911 misc_reg = MISCREG_FPSCR;
912 }
913 break;
914 case MISCREG_FPEXC:
915 {
916 // vfpv3 architecture, section B.6.1 of DDI04068
917 // bit 29 - valid only if fpexc[31] is 0
918 const uint32_t fpexcMask = 0x60000000;
919 newVal = (newVal & fpexcMask) |
920 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
921 }
922 break;
923 case MISCREG_HCR:
924 {
925 if (!haveVirtualization)
926 return;
927 }
928 break;
929 case MISCREG_IFSR:
930 {
931 // ARM ARM (ARM DDI 0406C.b) B4.1.96
932 const uint32_t ifsrMask =
933 mask(31, 13) | mask(11, 11) | mask(8, 6);
934 newVal = newVal & ~ifsrMask;
935 }
936 break;
937 case MISCREG_DFSR:
938 {
939 // ARM ARM (ARM DDI 0406C.b) B4.1.52
940 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
941 newVal = newVal & ~dfsrMask;
942 }
943 break;
944 case MISCREG_AMAIR0:
945 case MISCREG_AMAIR1:
946 {
947 // ARM ARM (ARM DDI 0406C.b) B4.1.5
948 // Valid only with LPAE
949 if (!haveLPAE)
950 return;
951 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
952 }
953 break;
954 case MISCREG_SCR:
955 getITBPtr(tc)->invalidateMiscReg();
956 getDTBPtr(tc)->invalidateMiscReg();
957 break;
958 case MISCREG_SCTLR:
959 {
960 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
961 scr = readMiscRegNoEffect(MISCREG_SCR);
962
963 MiscRegIndex sctlr_idx;
964 if (haveSecurity && !highestELIs64 && !scr.ns) {
965 sctlr_idx = MISCREG_SCTLR_S;
966 } else {
967 sctlr_idx = MISCREG_SCTLR_NS;
968 }
969
970 SCTLR sctlr = miscRegs[sctlr_idx];
971 SCTLR new_sctlr = newVal;
972 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
973 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
974 getITBPtr(tc)->invalidateMiscReg();
975 getDTBPtr(tc)->invalidateMiscReg();
976 }
977 case MISCREG_MIDR:
978 case MISCREG_ID_PFR0:
979 case MISCREG_ID_PFR1:
980 case MISCREG_ID_DFR0:
981 case MISCREG_ID_MMFR0:
982 case MISCREG_ID_MMFR1:
983 case MISCREG_ID_MMFR2:
984 case MISCREG_ID_MMFR3:
985 case MISCREG_ID_ISAR0:
986 case MISCREG_ID_ISAR1:
987 case MISCREG_ID_ISAR2:
988 case MISCREG_ID_ISAR3:
989 case MISCREG_ID_ISAR4:
990 case MISCREG_ID_ISAR5:
991
992 case MISCREG_MPIDR:
993 case MISCREG_FPSID:
994 case MISCREG_TLBTR:
995 case MISCREG_MVFR0:
996 case MISCREG_MVFR1:
997
998 case MISCREG_ID_AA64AFR0_EL1:
999 case MISCREG_ID_AA64AFR1_EL1:
1000 case MISCREG_ID_AA64DFR0_EL1:
1001 case MISCREG_ID_AA64DFR1_EL1:
1002 case MISCREG_ID_AA64ISAR0_EL1:
1003 case MISCREG_ID_AA64ISAR1_EL1:
1004 case MISCREG_ID_AA64MMFR0_EL1:
1005 case MISCREG_ID_AA64MMFR1_EL1:
1006 case MISCREG_ID_AA64MMFR2_EL1:
1007 case MISCREG_ID_AA64PFR0_EL1:
1008 case MISCREG_ID_AA64PFR1_EL1:
1009 // ID registers are constants.
1010 return;
1011
1012 // TLB Invalidate All
1013 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1014 {
1015 assert32(tc);
1016 scr = readMiscReg(MISCREG_SCR, tc);
1017
1018 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1019 tlbiOp(tc);
1020 return;
1021 }
1022 // TLB Invalidate All, Inner Shareable
1023 case MISCREG_TLBIALLIS:
1024 {
1025 assert32(tc);
1026 scr = readMiscReg(MISCREG_SCR, tc);
1027
1028 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1029 tlbiOp.broadcast(tc);
1030 return;
1031 }
1032 // Instruction TLB Invalidate All
1033 case MISCREG_ITLBIALL:
1034 {
1035 assert32(tc);
1036 scr = readMiscReg(MISCREG_SCR, tc);
1037
1038 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1039 tlbiOp(tc);
1040 return;
1041 }
1042 // Data TLB Invalidate All
1043 case MISCREG_DTLBIALL:
1044 {
1045 assert32(tc);
1046 scr = readMiscReg(MISCREG_SCR, tc);
1047
1048 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1049 tlbiOp(tc);
1050 return;
1051 }
1052 // TLB Invalidate by VA
1053 // mcr tlbimval(is) is invalidating all matching entries
1054 // regardless of the level of lookup, since in gem5 we cache
1055 // in the tlb the last level of lookup only.
1056 case MISCREG_TLBIMVA:
1057 case MISCREG_TLBIMVAL:
1058 {
1059 assert32(tc);
1060 scr = readMiscReg(MISCREG_SCR, tc);
1061
1062 TLBIMVA tlbiOp(EL1,
1063 haveSecurity && !scr.ns,
1064 mbits(newVal, 31, 12),
1065 bits(newVal, 7,0));
1066
1067 tlbiOp(tc);
1068 return;
1069 }
1070 // TLB Invalidate by VA, Inner Shareable
1071 case MISCREG_TLBIMVAIS:
1072 case MISCREG_TLBIMVALIS:
1073 {
1074 assert32(tc);
1075 scr = readMiscReg(MISCREG_SCR, tc);
1076
1077 TLBIMVA tlbiOp(EL1,
1078 haveSecurity && !scr.ns,
1079 mbits(newVal, 31, 12),
1080 bits(newVal, 7,0));
1081
1082 tlbiOp.broadcast(tc);
1083 return;
1084 }
1085 // TLB Invalidate by ASID match
1086 case MISCREG_TLBIASID:
1087 {
1088 assert32(tc);
1089 scr = readMiscReg(MISCREG_SCR, tc);
1090
1091 TLBIASID tlbiOp(EL1,
1092 haveSecurity && !scr.ns,
1093 bits(newVal, 7,0));
1094
1095 tlbiOp(tc);
1096 return;
1097 }
1098 // TLB Invalidate by ASID match, Inner Shareable
1099 case MISCREG_TLBIASIDIS:
1100 {
1101 assert32(tc);
1102 scr = readMiscReg(MISCREG_SCR, tc);
1103
1104 TLBIASID tlbiOp(EL1,
1105 haveSecurity && !scr.ns,
1106 bits(newVal, 7,0));
1107
1108 tlbiOp.broadcast(tc);
1109 return;
1110 }
1111 // mcr tlbimvaal(is) is invalidating all matching entries
1112 // regardless of the level of lookup, since in gem5 we cache
1113 // in the tlb the last level of lookup only.
1114 // TLB Invalidate by VA, All ASID
1115 case MISCREG_TLBIMVAA:
1116 case MISCREG_TLBIMVAAL:
1117 {
1118 assert32(tc);
1119 scr = readMiscReg(MISCREG_SCR, tc);
1120
1121 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1122 mbits(newVal, 31,12), false);
1123
1124 tlbiOp(tc);
1125 return;
1126 }
1127 // TLB Invalidate by VA, All ASID, Inner Shareable
1128 case MISCREG_TLBIMVAAIS:
1129 case MISCREG_TLBIMVAALIS:
1130 {
1131 assert32(tc);
1132 scr = readMiscReg(MISCREG_SCR, tc);
1133
1134 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1135 mbits(newVal, 31,12), false);
1136
1137 tlbiOp.broadcast(tc);
1138 return;
1139 }
1140 // mcr tlbimvalh(is) is invalidating all matching entries
1141 // regardless of the level of lookup, since in gem5 we cache
1142 // in the tlb the last level of lookup only.
1143 // TLB Invalidate by VA, Hyp mode
1144 case MISCREG_TLBIMVAH:
1145 case MISCREG_TLBIMVALH:
1146 {
1147 assert32(tc);
1148 scr = readMiscReg(MISCREG_SCR, tc);
1149
1150 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1151 mbits(newVal, 31,12), true);
1152
1153 tlbiOp(tc);
1154 return;
1155 }
1156 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1157 case MISCREG_TLBIMVAHIS:
1158 case MISCREG_TLBIMVALHIS:
1159 {
1160 assert32(tc);
1161 scr = readMiscReg(MISCREG_SCR, tc);
1162
1163 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1164 mbits(newVal, 31,12), true);
1165
1166 tlbiOp.broadcast(tc);
1167 return;
1168 }
1169 // mcr tlbiipas2l(is) is invalidating all matching entries
1170 // regardless of the level of lookup, since in gem5 we cache
1171 // in the tlb the last level of lookup only.
1172 // TLB Invalidate by Intermediate Physical Address, Stage 2
1173 case MISCREG_TLBIIPAS2:
1174 case MISCREG_TLBIIPAS2L:
1175 {
1176 assert32(tc);
1177 scr = readMiscReg(MISCREG_SCR, tc);
1178
1179 TLBIIPA tlbiOp(EL1,
1180 haveSecurity && !scr.ns,
1181 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1182
1183 tlbiOp(tc);
1184 return;
1185 }
1186 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1187 // Inner Shareable
1188 case MISCREG_TLBIIPAS2IS:
1189 case MISCREG_TLBIIPAS2LIS:
1190 {
1191 assert32(tc);
1192 scr = readMiscReg(MISCREG_SCR, tc);
1193
1194 TLBIIPA tlbiOp(EL1,
1195 haveSecurity && !scr.ns,
1196 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1197
1198 tlbiOp.broadcast(tc);
1199 return;
1200 }
1201 // Instruction TLB Invalidate by VA
1202 case MISCREG_ITLBIMVA:
1203 {
1204 assert32(tc);
1205 scr = readMiscReg(MISCREG_SCR, tc);
1206
1207 ITLBIMVA tlbiOp(EL1,
1208 haveSecurity && !scr.ns,
1209 mbits(newVal, 31, 12),
1210 bits(newVal, 7,0));
1211
1212 tlbiOp(tc);
1213 return;
1214 }
1215 // Data TLB Invalidate by VA
1216 case MISCREG_DTLBIMVA:
1217 {
1218 assert32(tc);
1219 scr = readMiscReg(MISCREG_SCR, tc);
1220
1221 DTLBIMVA tlbiOp(EL1,
1222 haveSecurity && !scr.ns,
1223 mbits(newVal, 31, 12),
1224 bits(newVal, 7,0));
1225
1226 tlbiOp(tc);
1227 return;
1228 }
1229 // Instruction TLB Invalidate by ASID match
1230 case MISCREG_ITLBIASID:
1231 {
1232 assert32(tc);
1233 scr = readMiscReg(MISCREG_SCR, tc);
1234
1235 ITLBIASID tlbiOp(EL1,
1236 haveSecurity && !scr.ns,
1237 bits(newVal, 7,0));
1238
1239 tlbiOp(tc);
1240 return;
1241 }
1242 // Data TLB Invalidate by ASID match
1243 case MISCREG_DTLBIASID:
1244 {
1245 assert32(tc);
1246 scr = readMiscReg(MISCREG_SCR, tc);
1247
1248 DTLBIASID tlbiOp(EL1,
1249 haveSecurity && !scr.ns,
1250 bits(newVal, 7,0));
1251
1252 tlbiOp(tc);
1253 return;
1254 }
1255 // TLB Invalidate All, Non-Secure Non-Hyp
1256 case MISCREG_TLBIALLNSNH:
1257 {
1258 assert32(tc);
1259
1260 TLBIALLN tlbiOp(EL1, false);
1261 tlbiOp(tc);
1262 return;
1263 }
1264 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1265 case MISCREG_TLBIALLNSNHIS:
1266 {
1267 assert32(tc);
1268
1269 TLBIALLN tlbiOp(EL1, false);
1270 tlbiOp.broadcast(tc);
1271 return;
1272 }
1273 // TLB Invalidate All, Hyp mode
1274 case MISCREG_TLBIALLH:
1275 {
1276 assert32(tc);
1277
1278 TLBIALLN tlbiOp(EL1, true);
1279 tlbiOp(tc);
1280 return;
1281 }
1282 // TLB Invalidate All, Hyp mode, Inner Shareable
1283 case MISCREG_TLBIALLHIS:
1284 {
1285 assert32(tc);
1286
1287 TLBIALLN tlbiOp(EL1, true);
1288 tlbiOp.broadcast(tc);
1289 return;
1290 }
1291 // AArch64 TLB Invalidate All, EL3
1292 case MISCREG_TLBI_ALLE3:
1293 {
1294 assert64(tc);
1295
1296 TLBIALL tlbiOp(EL3, true);
1297 tlbiOp(tc);
1298 return;
1299 }
1300 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1301 case MISCREG_TLBI_ALLE3IS:
1302 {
1303 assert64(tc);
1304
1305 TLBIALL tlbiOp(EL3, true);
1306 tlbiOp.broadcast(tc);
1307 return;
1308 }
1309 // @todo: uncomment this to enable Virtualization
1310 // case MISCREG_TLBI_ALLE2IS:
1311 // case MISCREG_TLBI_ALLE2:
1312 // AArch64 TLB Invalidate All, EL1
1313 case MISCREG_TLBI_ALLE1:
1314 case MISCREG_TLBI_VMALLE1:
1315 case MISCREG_TLBI_VMALLS12E1:
1316 // @todo: handle VMID and stage 2 to enable Virtualization
1317 {
1318 assert64(tc);
1319 scr = readMiscReg(MISCREG_SCR, tc);
1320
1321 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1322 tlbiOp(tc);
1323 return;
1324 }
1325 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1326 case MISCREG_TLBI_ALLE1IS:
1327 case MISCREG_TLBI_VMALLE1IS:
1328 case MISCREG_TLBI_VMALLS12E1IS:
1329 // @todo: handle VMID and stage 2 to enable Virtualization
1330 {
1331 assert64(tc);
1332 scr = readMiscReg(MISCREG_SCR, tc);
1333
1334 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1335 tlbiOp.broadcast(tc);
1336 return;
1337 }
1338 // VAEx(IS) and VALEx(IS) are the same because TLBs
1339 // only store entries
1340 // from the last level of translation table walks
1341 // @todo: handle VMID to enable Virtualization
1342 // AArch64 TLB Invalidate by VA, EL3
1343 case MISCREG_TLBI_VAE3_Xt:
1344 case MISCREG_TLBI_VALE3_Xt:
1345 {
1346 assert64(tc);
1347
1348 TLBIMVA tlbiOp(EL3, true,
1349 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1350 0xbeef);
1351 tlbiOp(tc);
1352 return;
1353 }
1354 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1355 case MISCREG_TLBI_VAE3IS_Xt:
1356 case MISCREG_TLBI_VALE3IS_Xt:
1357 {
1358 assert64(tc);
1359
1360 TLBIMVA tlbiOp(EL3, true,
1361 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1362 0xbeef);
1363
1364 tlbiOp.broadcast(tc);
1365 return;
1366 }
1367 // AArch64 TLB Invalidate by VA, EL2
1368 case MISCREG_TLBI_VAE2_Xt:
1369 case MISCREG_TLBI_VALE2_Xt:
1370 {
1371 assert64(tc);
1372 scr = readMiscReg(MISCREG_SCR, tc);
1373
1374 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1375 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1376 0xbeef);
1377 tlbiOp(tc);
1378 return;
1379 }
1380 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1381 case MISCREG_TLBI_VAE2IS_Xt:
1382 case MISCREG_TLBI_VALE2IS_Xt:
1383 {
1384 assert64(tc);
1385 scr = readMiscReg(MISCREG_SCR, tc);
1386
1387 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1388 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1389 0xbeef);
1390
1391 tlbiOp.broadcast(tc);
1392 return;
1393 }
1394 // AArch64 TLB Invalidate by VA, EL1
1395 case MISCREG_TLBI_VAE1_Xt:
1396 case MISCREG_TLBI_VALE1_Xt:
1397 {
1398 assert64(tc);
1399 scr = readMiscReg(MISCREG_SCR, tc);
1400 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1401 bits(newVal, 55, 48);
1402
1403 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1404 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1405 asid);
1406
1407 tlbiOp(tc);
1408 return;
1409 }
1410 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1411 case MISCREG_TLBI_VAE1IS_Xt:
1412 case MISCREG_TLBI_VALE1IS_Xt:
1413 {
1414 assert64(tc);
1415 scr = readMiscReg(MISCREG_SCR, tc);
1416 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1417 bits(newVal, 55, 48);
1418
1419 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1420 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1421 asid);
1422
1423 tlbiOp.broadcast(tc);
1424 return;
1425 }
1426 // AArch64 TLB Invalidate by ASID, EL1
1427 // @todo: handle VMID to enable Virtualization
1428 case MISCREG_TLBI_ASIDE1_Xt:
1429 {
1430 assert64(tc);
1431 scr = readMiscReg(MISCREG_SCR, tc);
1432 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1433 bits(newVal, 55, 48);
1434
1435 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1436 tlbiOp(tc);
1437 return;
1438 }
1439 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1440 case MISCREG_TLBI_ASIDE1IS_Xt:
1441 {
1442 assert64(tc);
1443 scr = readMiscReg(MISCREG_SCR, tc);
1444 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1445 bits(newVal, 55, 48);
1446
1447 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1448 tlbiOp.broadcast(tc);
1449 return;
1450 }
1451 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1452 // entries from the last level of translation table walks
1453 // AArch64 TLB Invalidate by VA, All ASID, EL1
1454 case MISCREG_TLBI_VAAE1_Xt:
1455 case MISCREG_TLBI_VAALE1_Xt:
1456 {
1457 assert64(tc);
1458 scr = readMiscReg(MISCREG_SCR, tc);
1459
1460 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1461 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1462
1463 tlbiOp(tc);
1464 return;
1465 }
1466 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1467 case MISCREG_TLBI_VAAE1IS_Xt:
1468 case MISCREG_TLBI_VAALE1IS_Xt:
1469 {
1470 assert64(tc);
1471 scr = readMiscReg(MISCREG_SCR, tc);
1472
1473 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1474 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1475
1476 tlbiOp.broadcast(tc);
1477 return;
1478 }
1479 // AArch64 TLB Invalidate by Intermediate Physical Address,
1480 // Stage 2, EL1
1481 case MISCREG_TLBI_IPAS2E1_Xt:
1482 case MISCREG_TLBI_IPAS2LE1_Xt:
1483 {
1484 assert64(tc);
1485 scr = readMiscReg(MISCREG_SCR, tc);
1486
1487 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1488 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1489
1490 tlbiOp(tc);
1491 return;
1492 }
1493 // AArch64 TLB Invalidate by Intermediate Physical Address,
1494 // Stage 2, EL1, Inner Shareable
1495 case MISCREG_TLBI_IPAS2E1IS_Xt:
1496 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1497 {
1498 assert64(tc);
1499 scr = readMiscReg(MISCREG_SCR, tc);
1500
1501 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1502 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1503
1504 tlbiOp.broadcast(tc);
1505 return;
1506 }
1507 case MISCREG_ACTLR:
1508 warn("Not doing anything for write of miscreg ACTLR\n");
1509 break;
1510
1511 case MISCREG_PMXEVTYPER_PMCCFILTR:
1512 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1513 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1514 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1515 pmu->setMiscReg(misc_reg, newVal);
1516 break;
1517
1518
1519 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1520 {
1521 HSTR hstrMask = 0;
1522 hstrMask.tjdbx = 1;
1523 newVal &= ~((uint32_t) hstrMask);
1524 break;
1525 }
1526 case MISCREG_HCPTR:
1527 {
1528 // If a CP bit in NSACR is 0 then the corresponding bit in
1529 // HCPTR is RAO/WI. Same applies to NSASEDIS
1530 secure_lookup = haveSecurity &&
1531 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1532 readMiscRegNoEffect(MISCREG_CPSR));
1533 if (!secure_lookup) {
1534 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1535 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1536 newVal = (newVal & ~mask) | (oldValue & mask);
1537 }
1538 break;
1539 }
1540 case MISCREG_HDFAR: // alias for secure DFAR
1541 misc_reg = MISCREG_DFAR_S;
1542 break;
1543 case MISCREG_HIFAR: // alias for secure IFAR
1544 misc_reg = MISCREG_IFAR_S;
1545 break;
1546 case MISCREG_ATS1CPR:
1547 case MISCREG_ATS1CPW:
1548 case MISCREG_ATS1CUR:
1549 case MISCREG_ATS1CUW:
1550 case MISCREG_ATS12NSOPR:
1551 case MISCREG_ATS12NSOPW:
1552 case MISCREG_ATS12NSOUR:
1553 case MISCREG_ATS12NSOUW:
1554 case MISCREG_ATS1HR:
1555 case MISCREG_ATS1HW:
1556 {
1557 Request::Flags flags = 0;
1558 BaseTLB::Mode mode = BaseTLB::Read;
1559 TLB::ArmTranslationType tranType = TLB::NormalTran;
1560 Fault fault;
1561 switch(misc_reg) {
1562 case MISCREG_ATS1CPR:
1563 flags = TLB::MustBeOne;
1564 tranType = TLB::S1CTran;
1565 mode = BaseTLB::Read;
1566 break;
1567 case MISCREG_ATS1CPW:
1568 flags = TLB::MustBeOne;
1569 tranType = TLB::S1CTran;
1570 mode = BaseTLB::Write;
1571 break;
1572 case MISCREG_ATS1CUR:
1573 flags = TLB::MustBeOne | TLB::UserMode;
1574 tranType = TLB::S1CTran;
1575 mode = BaseTLB::Read;
1576 break;
1577 case MISCREG_ATS1CUW:
1578 flags = TLB::MustBeOne | TLB::UserMode;
1579 tranType = TLB::S1CTran;
1580 mode = BaseTLB::Write;
1581 break;
1582 case MISCREG_ATS12NSOPR:
1583 if (!haveSecurity)
1584 panic("Security Extensions required for ATS12NSOPR");
1585 flags = TLB::MustBeOne;
1586 tranType = TLB::S1S2NsTran;
1587 mode = BaseTLB::Read;
1588 break;
1589 case MISCREG_ATS12NSOPW:
1590 if (!haveSecurity)
1591 panic("Security Extensions required for ATS12NSOPW");
1592 flags = TLB::MustBeOne;
1593 tranType = TLB::S1S2NsTran;
1594 mode = BaseTLB::Write;
1595 break;
1596 case MISCREG_ATS12NSOUR:
1597 if (!haveSecurity)
1598 panic("Security Extensions required for ATS12NSOUR");
1599 flags = TLB::MustBeOne | TLB::UserMode;
1600 tranType = TLB::S1S2NsTran;
1601 mode = BaseTLB::Read;
1602 break;
1603 case MISCREG_ATS12NSOUW:
1604 if (!haveSecurity)
1605 panic("Security Extensions required for ATS12NSOUW");
1606 flags = TLB::MustBeOne | TLB::UserMode;
1607 tranType = TLB::S1S2NsTran;
1608 mode = BaseTLB::Write;
1609 break;
1610 case MISCREG_ATS1HR: // only really useful from secure mode.
1611 flags = TLB::MustBeOne;
1612 tranType = TLB::HypMode;
1613 mode = BaseTLB::Read;
1614 break;
1615 case MISCREG_ATS1HW:
1616 flags = TLB::MustBeOne;
1617 tranType = TLB::HypMode;
1618 mode = BaseTLB::Write;
1619 break;
1620 }
1621 // If we're in timing mode then doing the translation in
1622 // functional mode then we're slightly distorting performance
1623 // results obtained from simulations. The translation should be
1624 // done in the same mode the core is running in. NOTE: This
1625 // can't be an atomic translation because that causes problems
1626 // with unexpected atomic snoop requests.
1627 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1628
1629 auto req = std::make_shared<Request>(
1630 0, val, 0, flags, Request::funcMasterId,
1631 tc->pcState().pc(), tc->contextId());
1632
1633 fault = getDTBPtr(tc)->translateFunctional(
1634 req, tc, mode, tranType);
1635
1636 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1637 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1638
1639 MiscReg newVal;
1640 if (fault == NoFault) {
1641 Addr paddr = req->getPaddr();
1642 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1643 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1644 newVal = (paddr & mask(39, 12)) |
1645 (getDTBPtr(tc)->getAttr());
1646 } else {
1647 newVal = (paddr & 0xfffff000) |
1648 (getDTBPtr(tc)->getAttr());
1649 }
1650 DPRINTF(MiscRegs,
1651 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1652 val, newVal);
1653 } else {
1654 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1655 armFault->update(tc);
1656 // Set fault bit and FSR
1657 FSR fsr = armFault->getFsr(tc);
1658
1659 newVal = ((fsr >> 9) & 1) << 11;
1660 if (newVal) {
1661 // LPAE - rearange fault status
1662 newVal |= ((fsr >> 0) & 0x3f) << 1;
1663 } else {
1664 // VMSA - rearange fault status
1665 newVal |= ((fsr >> 0) & 0xf) << 1;
1666 newVal |= ((fsr >> 10) & 0x1) << 5;
1667 newVal |= ((fsr >> 12) & 0x1) << 6;
1668 }
1669 newVal |= 0x1; // F bit
1670 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1671 newVal |= armFault->isStage2() ? 0x200 : 0;
1672 DPRINTF(MiscRegs,
1673 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1674 val, fsr, newVal);
1675 }
1676 setMiscRegNoEffect(MISCREG_PAR, newVal);
1677 return;
1678 }
1679 case MISCREG_TTBCR:
1680 {
1681 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1682 const uint32_t ones = (uint32_t)(-1);
1683 TTBCR ttbcrMask = 0;
1684 TTBCR ttbcrNew = newVal;
1685
1686 // ARM DDI 0406C.b, ARMv7-32
1687 ttbcrMask.n = ones; // T0SZ
1688 if (haveSecurity) {
1689 ttbcrMask.pd0 = ones;
1690 ttbcrMask.pd1 = ones;
1691 }
1692 ttbcrMask.epd0 = ones;
1693 ttbcrMask.irgn0 = ones;
1694 ttbcrMask.orgn0 = ones;
1695 ttbcrMask.sh0 = ones;
1696 ttbcrMask.ps = ones; // T1SZ
1697 ttbcrMask.a1 = ones;
1698 ttbcrMask.epd1 = ones;
1699 ttbcrMask.irgn1 = ones;
1700 ttbcrMask.orgn1 = ones;
1701 ttbcrMask.sh1 = ones;
1702 if (haveLPAE)
1703 ttbcrMask.eae = ones;
1704
1705 if (haveLPAE && ttbcrNew.eae) {
1706 newVal = newVal & ttbcrMask;
1707 } else {
1708 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1709 }
1710 // Invalidate TLB MiscReg
1711 getITBPtr(tc)->invalidateMiscReg();
1712 getDTBPtr(tc)->invalidateMiscReg();
1713 break;
1714 }
1715 case MISCREG_TTBR0:
1716 case MISCREG_TTBR1:
1717 {
1718 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1719 if (haveLPAE) {
1720 if (ttbcr.eae) {
1721 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1722 // ARMv8 AArch32 bit 63-56 only
1723 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1724 newVal = (newVal & (~ttbrMask));
1725 }
1726 }
1727 // Invalidate TLB MiscReg
1728 getITBPtr(tc)->invalidateMiscReg();
1729 getDTBPtr(tc)->invalidateMiscReg();
1730 break;
1731 }
1732 case MISCREG_SCTLR_EL1:
1733 case MISCREG_CONTEXTIDR:
1734 case MISCREG_PRRR:
1735 case MISCREG_NMRR:
1736 case MISCREG_MAIR0:
1737 case MISCREG_MAIR1:
1738 case MISCREG_DACR:
1739 case MISCREG_VTTBR:
1740 case MISCREG_SCR_EL3:
1741 case MISCREG_HCR_EL2:
1742 case MISCREG_TCR_EL1:
1743 case MISCREG_TCR_EL2:
1744 case MISCREG_TCR_EL3:
1745 case MISCREG_SCTLR_EL2:
1746 case MISCREG_SCTLR_EL3:
1747 case MISCREG_HSCTLR:
1748 case MISCREG_TTBR0_EL1:
1749 case MISCREG_TTBR1_EL1:
1750 case MISCREG_TTBR0_EL2:
1751 case MISCREG_TTBR1_EL2:
1752 case MISCREG_TTBR0_EL3:
1753 getITBPtr(tc)->invalidateMiscReg();
1754 getDTBPtr(tc)->invalidateMiscReg();
1755 break;
1756 case MISCREG_NZCV:
1757 {
1758 CPSR cpsr = val;
1759
1760 tc->setCCReg(CCREG_NZ, cpsr.nz);
1761 tc->setCCReg(CCREG_C, cpsr.c);
1762 tc->setCCReg(CCREG_V, cpsr.v);
1763 }
1764 break;
1765 case MISCREG_DAIF:
1766 {
1767 CPSR cpsr = miscRegs[MISCREG_CPSR];
1768 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1769 newVal = cpsr;
1770 misc_reg = MISCREG_CPSR;
1771 }
1772 break;
1773 case MISCREG_SP_EL0:
1774 tc->setIntReg(INTREG_SP0, newVal);
1775 break;
1776 case MISCREG_SP_EL1:
1777 tc->setIntReg(INTREG_SP1, newVal);
1778 break;
1779 case MISCREG_SP_EL2:
1780 tc->setIntReg(INTREG_SP2, newVal);
1781 break;
1782 case MISCREG_SPSEL:
1783 {
1784 CPSR cpsr = miscRegs[MISCREG_CPSR];
1785 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1786 newVal = cpsr;
1787 misc_reg = MISCREG_CPSR;
1788 }
1789 break;
1790 case MISCREG_CURRENTEL:
1791 {
1792 CPSR cpsr = miscRegs[MISCREG_CPSR];
1793 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1794 newVal = cpsr;
1795 misc_reg = MISCREG_CPSR;
1796 }
1797 break;
1798 case MISCREG_AT_S1E1R_Xt:
1799 case MISCREG_AT_S1E1W_Xt:
1800 case MISCREG_AT_S1E0R_Xt:
1801 case MISCREG_AT_S1E0W_Xt:
1802 case MISCREG_AT_S1E2R_Xt:
1803 case MISCREG_AT_S1E2W_Xt:
1804 case MISCREG_AT_S12E1R_Xt:
1805 case MISCREG_AT_S12E1W_Xt:
1806 case MISCREG_AT_S12E0R_Xt:
1807 case MISCREG_AT_S12E0W_Xt:
1808 case MISCREG_AT_S1E3R_Xt:
1809 case MISCREG_AT_S1E3W_Xt:
1810 {
1811 RequestPtr req = std::make_shared<Request>();
1812 Request::Flags flags = 0;
1813 BaseTLB::Mode mode = BaseTLB::Read;
1814 TLB::ArmTranslationType tranType = TLB::NormalTran;
1815 Fault fault;
1816 switch(misc_reg) {
1817 case MISCREG_AT_S1E1R_Xt:
1818 flags = TLB::MustBeOne;
1819 tranType = TLB::S1E1Tran;
1820 mode = BaseTLB::Read;
1821 break;
1822 case MISCREG_AT_S1E1W_Xt:
1823 flags = TLB::MustBeOne;
1824 tranType = TLB::S1E1Tran;
1825 mode = BaseTLB::Write;
1826 break;
1827 case MISCREG_AT_S1E0R_Xt:
1828 flags = TLB::MustBeOne | TLB::UserMode;
1829 tranType = TLB::S1E0Tran;
1830 mode = BaseTLB::Read;
1831 break;
1832 case MISCREG_AT_S1E0W_Xt:
1833 flags = TLB::MustBeOne | TLB::UserMode;
1834 tranType = TLB::S1E0Tran;
1835 mode = BaseTLB::Write;
1836 break;
1837 case MISCREG_AT_S1E2R_Xt:
1838 flags = TLB::MustBeOne;
1839 tranType = TLB::S1E2Tran;
1840 mode = BaseTLB::Read;
1841 break;
1842 case MISCREG_AT_S1E2W_Xt:
1843 flags = TLB::MustBeOne;
1844 tranType = TLB::S1E2Tran;
1845 mode = BaseTLB::Write;
1846 break;
1847 case MISCREG_AT_S12E0R_Xt:
1848 flags = TLB::MustBeOne | TLB::UserMode;
1849 tranType = TLB::S12E0Tran;
1850 mode = BaseTLB::Read;
1851 break;
1852 case MISCREG_AT_S12E0W_Xt:
1853 flags = TLB::MustBeOne | TLB::UserMode;
1854 tranType = TLB::S12E0Tran;
1855 mode = BaseTLB::Write;
1856 break;
1857 case MISCREG_AT_S12E1R_Xt:
1858 flags = TLB::MustBeOne;
1859 tranType = TLB::S12E1Tran;
1860 mode = BaseTLB::Read;
1861 break;
1862 case MISCREG_AT_S12E1W_Xt:
1863 flags = TLB::MustBeOne;
1864 tranType = TLB::S12E1Tran;
1865 mode = BaseTLB::Write;
1866 break;
1867 case MISCREG_AT_S1E3R_Xt:
1868 flags = TLB::MustBeOne;
1869 tranType = TLB::S1E3Tran;
1870 mode = BaseTLB::Read;
1871 break;
1872 case MISCREG_AT_S1E3W_Xt:
1873 flags = TLB::MustBeOne;
1874 tranType = TLB::S1E3Tran;
1875 mode = BaseTLB::Write;
1876 break;
1877 }
1878 // If we're in timing mode then doing the translation in
1879 // functional mode then we're slightly distorting performance
1880 // results obtained from simulations. The translation should be
1881 // done in the same mode the core is running in. NOTE: This
1882 // can't be an atomic translation because that causes problems
1883 // with unexpected atomic snoop requests.
1884 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1885 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1886 tc->pcState().pc());
1887 req->setContext(tc->contextId());
1888 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1889 tranType);
1890
1891 MiscReg newVal;
1892 if (fault == NoFault) {
1893 Addr paddr = req->getPaddr();
1894 uint64_t attr = getDTBPtr(tc)->getAttr();
1895 uint64_t attr1 = attr >> 56;
1896 if (!attr1 || attr1 ==0x44) {
1897 attr |= 0x100;
1898 attr &= ~ uint64_t(0x80);
1899 }
1900 newVal = (paddr & mask(47, 12)) | attr;
1901 DPRINTF(MiscRegs,
1902 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1903 val, newVal);
1904 } else {
1905 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1906 armFault->update(tc);
1907 // Set fault bit and FSR
1908 FSR fsr = armFault->getFsr(tc);
1909
1910 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1911 if (cpsr.width) { // AArch32
1912 newVal = ((fsr >> 9) & 1) << 11;
1913 // rearrange fault status
1914 newVal |= ((fsr >> 0) & 0x3f) << 1;
1915 newVal |= 0x1; // F bit
1916 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1917 newVal |= armFault->isStage2() ? 0x200 : 0;
1918 } else { // AArch64
1919 newVal = 1; // F bit
1920 newVal |= fsr << 1; // FST
1921 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1922 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1923 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1924 newVal |= 1 << 11; // RES1
1925 }
1926 DPRINTF(MiscRegs,
1927 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1928 val, fsr, newVal);
1929 }
1930 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1931 return;
1932 }
1933 case MISCREG_SPSR_EL3:
1934 case MISCREG_SPSR_EL2:
1935 case MISCREG_SPSR_EL1:
1936 // Force bits 23:21 to 0
1937 newVal = val & ~(0x7 << 21);
1938 break;
1939 case MISCREG_L2CTLR:
1940 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1941 miscRegName[misc_reg], uint32_t(val));
1942 break;
1943
1944 // Generic Timer registers
1945 case MISCREG_CNTHV_CTL_EL2:
1946 case MISCREG_CNTHV_CVAL_EL2:
1947 case MISCREG_CNTHV_TVAL_EL2:
1948 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1949 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1950 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1951 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1952 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1953 break;
1954 }
1955 }
1956 setMiscRegNoEffect(misc_reg, newVal);
1957}
1958
1959BaseISADevice &
1960ISA::getGenericTimer(ThreadContext *tc)
1961{
1962 // We only need to create an ISA interface the first time we try
1963 // to access the timer.
1964 if (timer)
1965 return *timer.get();
1966
1967 assert(system);
1968 GenericTimer *generic_timer(system->getGenericTimer());
1969 if (!generic_timer) {
1970 panic("Trying to get a generic timer from a system that hasn't "
1971 "been configured to use a generic timer.\n");
1972 }
1973
1974 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1975 timer->setThreadContext(tc);
1976
1977 return *timer.get();
1978}
1979
1980}
1981
1982ArmISA::ISA *
1983ArmISAParams::create()
1984{
1985 return new ArmISA::ISA(this);
1986}