1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58
59ISA::ISA(Params *p)
60 : SimObject(p),
61 system(NULL),
62 _decoderFlavour(p->decoderFlavour),
63 _vecRegRenameMode(p->vecRegRenameMode),
64 pmu(p->pmu),
65 impdefAsNop(p->impdef_nop)
66{
67 miscRegs[MISCREG_SCTLR_RST] = 0;
68
69 // Hook up a dummy device if we haven't been configured with a
70 // real PMU. By using a dummy device, we don't need to check that
71 // the PMU exist every time we try to access a PMU register.
72 if (!pmu)
73 pmu = &dummyDevice;
74
75 // Give all ISA devices a pointer to this ISA
76 pmu->setISA(this);
77
78 system = dynamic_cast<ArmSystem *>(p->system);
79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
87 physAddrRange64 = system->physAddrRange64();
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
92 physAddrRange64 = 32; // dummy value
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();
99}
100
101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
102
103const ArmISAParams *
104ISA::params() const
105{
106 return dynamic_cast<const Params *>(_params);
107}
108
109void
110ISA::clear()
111{
112 const Params *p(params());
113
114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
115 memset(miscRegs, 0, sizeof(miscRegs));
116
117 // Initialize configurable default values
118 miscRegs[MISCREG_MIDR] = p->midr;
119 miscRegs[MISCREG_MIDR_EL1] = p->midr;
120 miscRegs[MISCREG_VPIDR] = p->midr;
121
122 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
123 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
124 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
125 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
126 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
127 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
128
129 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
130 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
131 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
132 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
133
134 if (FullSystem && system->highestELIs64()) {
135 // Initialize AArch64 state
136 clear64(p);
137 return;
138 }
139
140 // Initialize AArch32 state...
141
142 CPSR cpsr = 0;
143 cpsr.mode = MODE_USER;
144 miscRegs[MISCREG_CPSR] = cpsr;
145 updateRegMap(cpsr);
146
147 SCTLR sctlr = 0;
148 sctlr.te = (bool) sctlr_rst.te;
149 sctlr.nmfi = (bool) sctlr_rst.nmfi;
150 sctlr.v = (bool) sctlr_rst.v;
151 sctlr.u = 1;
152 sctlr.xp = 1;
153 sctlr.rao2 = 1;
154 sctlr.rao3 = 1;
155 sctlr.rao4 = 0xf; // SCTLR[6:3]
156 sctlr.uci = 1;
157 sctlr.dze = 1;
158 miscRegs[MISCREG_SCTLR_NS] = sctlr;
159 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
160 miscRegs[MISCREG_HCPTR] = 0;
161
162 // Start with an event in the mailbox
163 miscRegs[MISCREG_SEV_MAILBOX] = 1;
164
165 // Separate Instruction and Data TLBs
166 miscRegs[MISCREG_TLBTR] = 1;
167
168 MVFR0 mvfr0 = 0;
169 mvfr0.advSimdRegisters = 2;
170 mvfr0.singlePrecision = 2;
171 mvfr0.doublePrecision = 2;
172 mvfr0.vfpExceptionTrapping = 0;
173 mvfr0.divide = 1;
174 mvfr0.squareRoot = 1;
175 mvfr0.shortVectors = 1;
176 mvfr0.roundingModes = 1;
177 miscRegs[MISCREG_MVFR0] = mvfr0;
178
179 MVFR1 mvfr1 = 0;
180 mvfr1.flushToZero = 1;
181 mvfr1.defaultNaN = 1;
182 mvfr1.advSimdLoadStore = 1;
183 mvfr1.advSimdInteger = 1;
184 mvfr1.advSimdSinglePrecision = 1;
185 mvfr1.advSimdHalfPrecision = 1;
186 mvfr1.vfpHalfPrecision = 1;
187 miscRegs[MISCREG_MVFR1] = mvfr1;
188
189 // Reset values of PRRR and NMRR are implementation dependent
190
191 // @todo: PRRR and NMRR in secure state?
192 miscRegs[MISCREG_PRRR_NS] =
193 (1 << 19) | // 19
194 (0 << 18) | // 18
195 (0 << 17) | // 17
196 (1 << 16) | // 16
197 (2 << 14) | // 15:14
198 (0 << 12) | // 13:12
199 (2 << 10) | // 11:10
200 (2 << 8) | // 9:8
201 (2 << 6) | // 7:6
202 (2 << 4) | // 5:4
203 (1 << 2) | // 3:2
204 0; // 1:0
205 miscRegs[MISCREG_NMRR_NS] =
206 (1 << 30) | // 31:30
207 (0 << 26) | // 27:26
208 (0 << 24) | // 25:24
209 (3 << 22) | // 23:22
210 (2 << 20) | // 21:20
211 (0 << 18) | // 19:18
212 (0 << 16) | // 17:16
213 (1 << 14) | // 15:14
214 (0 << 12) | // 13:12
215 (2 << 10) | // 11:10
216 (0 << 8) | // 9:8
217 (3 << 6) | // 7:6
218 (2 << 4) | // 5:4
219 (0 << 2) | // 3:2
220 0; // 1:0
221
222 miscRegs[MISCREG_CPACR] = 0;
223
224 miscRegs[MISCREG_FPSID] = p->fpsid;
225
226 if (haveLPAE) {
227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
228 ttbcr.eae = 0;
229 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
230 // Enforce consistency with system-level settings
231 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
232 }
233
234 if (haveSecurity) {
235 miscRegs[MISCREG_SCTLR_S] = sctlr;
236 miscRegs[MISCREG_SCR] = 0;
237 miscRegs[MISCREG_VBAR_S] = 0;
238 } else {
239 // we're always non-secure
240 miscRegs[MISCREG_SCR] = 1;
241 }
242
243 //XXX We need to initialize the rest of the state.
244}
245
246void
247ISA::clear64(const ArmISAParams *p)
248{
249 CPSR cpsr = 0;
250 Addr rvbar = system->resetAddr64();
251 switch (system->highestEL()) {
252 // Set initial EL to highest implemented EL using associated stack
253 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
254 // value
255 case EL3:
256 cpsr.mode = MODE_EL3H;
257 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
258 break;
259 case EL2:
260 cpsr.mode = MODE_EL2H;
261 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
262 break;
263 case EL1:
264 cpsr.mode = MODE_EL1H;
265 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
266 break;
267 default:
268 panic("Invalid highest implemented exception level");
269 break;
270 }
271
272 // Initialize rest of CPSR
273 cpsr.daif = 0xf; // Mask all interrupts
274 cpsr.ss = 0;
275 cpsr.il = 0;
276 miscRegs[MISCREG_CPSR] = cpsr;
277 updateRegMap(cpsr);
278
279 // Initialize other control registers
280 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
281 if (haveSecurity) {
282 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
283 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
284 } else if (haveVirtualization) {
285 // also MISCREG_SCTLR_EL2 (by mapping)
286 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
287 } else {
288 // also MISCREG_SCTLR_EL1 (by mapping)
289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
290 // Always non-secure
291 miscRegs[MISCREG_SCR_EL3] = 1;
292 }
293
294 // Initialize configurable id registers
295 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
296 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
297 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
298 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
299 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
300
301 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
302 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
303 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
304 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
305 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
306
307 miscRegs[MISCREG_ID_DFR0_EL1] =
308 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
309
310 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
311
312 // Enforce consistency with system-level settings...
313
314 // EL3
315 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
316 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
317 haveSecurity ? 0x2 : 0x0);
318 // EL2
319 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
320 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
321 haveVirtualization ? 0x2 : 0x0);
322 // Large ASID support
323 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
324 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
325 haveLargeAsid64 ? 0x2 : 0x0);
326 // Physical address size
327 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
328 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
329 encodePhysAddrRange64(physAddrRange64));
330}
331
332void
333ISA::startup(ThreadContext *tc)
334{
335 pmu->setThreadContext(tc);
336
337}
338
339
340MiscReg
341ISA::readMiscRegNoEffect(int misc_reg) const
342{
343 assert(misc_reg < NumMiscRegs);
344
345 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
346 const auto &map = getMiscIndices(misc_reg);
347 int lower = map.first, upper = map.second;
348 // NB!: apply architectural masks according to desired register,
349 // despite possibly getting value from different (mapped) register.
350 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
351 |(miscRegs[upper] << 32));
352 if (val & reg.res0()) {
353 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
354 miscRegName[misc_reg], val & reg.res0());
355 }
356 if ((val & reg.res1()) != reg.res1()) {
357 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
358 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
359 }
360 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
361}
362
363
364MiscReg
365ISA::readMiscReg(int misc_reg, ThreadContext *tc)
366{
367 CPSR cpsr = 0;
368 PCState pc = 0;
369 SCR scr = 0;
370
371 if (misc_reg == MISCREG_CPSR) {
372 cpsr = miscRegs[misc_reg];
373 pc = tc->pcState();
374 cpsr.j = pc.jazelle() ? 1 : 0;
375 cpsr.t = pc.thumb() ? 1 : 0;
376 return cpsr;
377 }
378
379#ifndef NDEBUG
380 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
381 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
382 warn("Unimplemented system register %s read.\n",
383 miscRegName[misc_reg]);
384 else
385 panic("Unimplemented system register %s read.\n",
386 miscRegName[misc_reg]);
387 }
388#endif
389
390 switch (unflattenMiscReg(misc_reg)) {
391 case MISCREG_HCR:
392 {
393 if (!haveVirtualization)
394 return 0;
395 else
396 return readMiscRegNoEffect(MISCREG_HCR);
397 }
398 case MISCREG_CPACR:
399 {
400 const uint32_t ones = (uint32_t)(-1);
401 CPACR cpacrMask = 0;
402 // Only cp10, cp11, and ase are implemented, nothing else should
403 // be readable? (straight copy from the write code)
404 cpacrMask.cp10 = ones;
405 cpacrMask.cp11 = ones;
406 cpacrMask.asedis = ones;
407
408 // Security Extensions may limit the readability of CPACR
409 if (haveSecurity) {
410 scr = readMiscRegNoEffect(MISCREG_SCR);
411 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
412 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
413 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
414 // NB: Skipping the full loop, here
415 if (!nsacr.cp10) cpacrMask.cp10 = 0;
416 if (!nsacr.cp11) cpacrMask.cp11 = 0;
417 }
418 }
419 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
420 val &= cpacrMask;
421 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
422 miscRegName[misc_reg], val);
423 return val;
424 }
425 case MISCREG_MPIDR:
426 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
427 scr = readMiscRegNoEffect(MISCREG_SCR);
428 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
429 return getMPIDR(system, tc);
430 } else {
431 return readMiscReg(MISCREG_VMPIDR, tc);
432 }
433 break;
434 case MISCREG_MPIDR_EL1:
435 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
436 return getMPIDR(system, tc) & 0xffffffff;
437 case MISCREG_VMPIDR:
438 // top bit defined as RES1
439 return readMiscRegNoEffect(misc_reg) | 0x80000000;
440 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
441 case MISCREG_REVIDR: // not implemented, so alias MIDR
442 case MISCREG_MIDR:
443 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
444 scr = readMiscRegNoEffect(MISCREG_SCR);
445 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
446 return readMiscRegNoEffect(misc_reg);
447 } else {
448 return readMiscRegNoEffect(MISCREG_VPIDR);
449 }
450 break;
451 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
452 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
453 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
454 case MISCREG_AIDR: // AUX ID set to 0
455 case MISCREG_TCMTR: // No TCM's
456 return 0;
457
458 case MISCREG_CLIDR:
459 warn_once("The clidr register always reports 0 caches.\n");
460 warn_once("clidr LoUIS field of 0b001 to match current "
461 "ARM implementations.\n");
462 return 0x00200000;
463 case MISCREG_CCSIDR:
464 warn_once("The ccsidr register isn't implemented and "
465 "always reads as 0.\n");
466 break;
467 case MISCREG_CTR: // AArch32, ARMv7, top bit set
468 case MISCREG_CTR_EL0: // AArch64
469 {
470 //all caches have the same line size in gem5
471 //4 byte words in ARM
472 unsigned lineSizeWords =
473 tc->getSystemPtr()->cacheLineSize() / 4;
474 unsigned log2LineSizeWords = 0;
475
476 while (lineSizeWords >>= 1) {
477 ++log2LineSizeWords;
478 }
479
480 CTR ctr = 0;
481 //log2 of minimun i-cache line size (words)
482 ctr.iCacheLineSize = log2LineSizeWords;
483 //b11 - gem5 uses pipt
484 ctr.l1IndexPolicy = 0x3;
485 //log2 of minimum d-cache line size (words)
486 ctr.dCacheLineSize = log2LineSizeWords;
487 //log2 of max reservation size (words)
488 ctr.erg = log2LineSizeWords;
489 //log2 of max writeback size (words)
490 ctr.cwg = log2LineSizeWords;
491 //b100 - gem5 format is ARMv7
492 ctr.format = 0x4;
493
494 return ctr;
495 }
496 case MISCREG_ACTLR:
497 warn("Not doing anything for miscreg ACTLR\n");
498 break;
499
500 case MISCREG_PMXEVTYPER_PMCCFILTR:
501 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
502 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
503 case MISCREG_PMCR ... MISCREG_PMOVSSET:
504 return pmu->readMiscReg(misc_reg);
505
506 case MISCREG_CPSR_Q:
507 panic("shouldn't be reading this register seperately\n");
508 case MISCREG_FPSCR_QC:
509 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
510 case MISCREG_FPSCR_EXC:
511 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
512 case MISCREG_FPSR:
513 {
514 const uint32_t ones = (uint32_t)(-1);
515 FPSCR fpscrMask = 0;
516 fpscrMask.ioc = ones;
517 fpscrMask.dzc = ones;
518 fpscrMask.ofc = ones;
519 fpscrMask.ufc = ones;
520 fpscrMask.ixc = ones;
521 fpscrMask.idc = ones;
522 fpscrMask.qc = ones;
523 fpscrMask.v = ones;
524 fpscrMask.c = ones;
525 fpscrMask.z = ones;
526 fpscrMask.n = ones;
527 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
528 }
529 case MISCREG_FPCR:
530 {
531 const uint32_t ones = (uint32_t)(-1);
532 FPSCR fpscrMask = 0;
533 fpscrMask.len = ones;
534 fpscrMask.stride = ones;
535 fpscrMask.rMode = ones;
536 fpscrMask.fz = ones;
537 fpscrMask.dn = ones;
538 fpscrMask.ahp = ones;
539 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
540 }
541 case MISCREG_NZCV:
542 {
543 CPSR cpsr = 0;
544 cpsr.nz = tc->readCCReg(CCREG_NZ);
545 cpsr.c = tc->readCCReg(CCREG_C);
546 cpsr.v = tc->readCCReg(CCREG_V);
547 return cpsr;
548 }
549 case MISCREG_DAIF:
550 {
551 CPSR cpsr = 0;
552 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
553 return cpsr;
554 }
555 case MISCREG_SP_EL0:
556 {
557 return tc->readIntReg(INTREG_SP0);
558 }
559 case MISCREG_SP_EL1:
560 {
561 return tc->readIntReg(INTREG_SP1);
562 }
563 case MISCREG_SP_EL2:
564 {
565 return tc->readIntReg(INTREG_SP2);
566 }
567 case MISCREG_SPSEL:
568 {
569 return miscRegs[MISCREG_CPSR] & 0x1;
570 }
571 case MISCREG_CURRENTEL:
572 {
573 return miscRegs[MISCREG_CPSR] & 0xc;
574 }
575 case MISCREG_L2CTLR:
576 {
577 // mostly unimplemented, just set NumCPUs field from sim and return
578 L2CTLR l2ctlr = 0;
579 // b00:1CPU to b11:4CPUs
580 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
581 return l2ctlr;
582 }
583 case MISCREG_DBGDIDR:
584 /* For now just implement the version number.
585 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
586 */
587 return 0x5 << 16;
588 case MISCREG_DBGDSCRint:
589 return 0;
590 case MISCREG_ISR:
591 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
592 readMiscRegNoEffect(MISCREG_HCR),
593 readMiscRegNoEffect(MISCREG_CPSR),
594 readMiscRegNoEffect(MISCREG_SCR));
595 case MISCREG_ISR_EL1:
596 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
597 readMiscRegNoEffect(MISCREG_HCR_EL2),
598 readMiscRegNoEffect(MISCREG_CPSR),
599 readMiscRegNoEffect(MISCREG_SCR_EL3));
600 case MISCREG_DCZID_EL0:
601 return 0x04; // DC ZVA clear 64-byte chunks
602 case MISCREG_HCPTR:
603 {
604 MiscReg val = readMiscRegNoEffect(misc_reg);
605 // The trap bit associated with CP14 is defined as RAZ
606 val &= ~(1 << 14);
607 // If a CP bit in NSACR is 0 then the corresponding bit in
608 // HCPTR is RAO/WI
609 bool secure_lookup = haveSecurity &&
610 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
611 readMiscRegNoEffect(MISCREG_CPSR));
612 if (!secure_lookup) {
613 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
614 val |= (mask ^ 0x7FFF) & 0xBFFF;
615 }
616 // Set the bits for unimplemented coprocessors to RAO/WI
617 val |= 0x33FF;
618 return (val);
619 }
620 case MISCREG_HDFAR: // alias for secure DFAR
621 return readMiscRegNoEffect(MISCREG_DFAR_S);
622 case MISCREG_HIFAR: // alias for secure IFAR
623 return readMiscRegNoEffect(MISCREG_IFAR_S);
624 case MISCREG_HVBAR: // bottom bits reserved
625 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
626 case MISCREG_SCTLR:
627 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
628 case MISCREG_SCTLR_EL1:
629 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
630 case MISCREG_SCTLR_EL2:
631 case MISCREG_SCTLR_EL3:
632 case MISCREG_HSCTLR:
633 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
634
635 case MISCREG_ID_PFR0:
636 // !ThumbEE | !Jazelle | Thumb | ARM
637 return 0x00000031;
638 case MISCREG_ID_PFR1:
639 { // Timer | Virti | !M Profile | TrustZone | ARMv4
640 bool haveTimer = (system->getGenericTimer() != NULL);
641 return 0x00000001
642 | (haveSecurity ? 0x00000010 : 0x0)
643 | (haveVirtualization ? 0x00001000 : 0x0)
644 | (haveTimer ? 0x00010000 : 0x0);
645 }
646 case MISCREG_ID_AA64PFR0_EL1:
647 return 0x0000000000000002 // AArch{64,32} supported at EL0
648 | 0x0000000000000020 // EL1
649 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
650 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
651 case MISCREG_ID_AA64PFR1_EL1:
652 return 0; // bits [63:0] RES0 (reserved for future use)
653
654 // Generic Timer registers
655 case MISCREG_CNTHV_CTL_EL2:
656 case MISCREG_CNTHV_CVAL_EL2:
657 case MISCREG_CNTHV_TVAL_EL2:
658 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
659 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
660 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
661 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
662 return getGenericTimer(tc).readMiscReg(misc_reg);
663
664 default:
665 break;
666
667 }
668 return readMiscRegNoEffect(misc_reg);
669}
670
671void
672ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
673{
674 assert(misc_reg < NumMiscRegs);
675
676 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
677 const auto &map = getMiscIndices(misc_reg);
678 int lower = map.first, upper = map.second;
679
680 auto v = (val & ~reg.wi()) | reg.rao();
681 if (upper > 0) {
682 miscRegs[lower] = bits(v, 31, 0);
683 miscRegs[upper] = bits(v, 63, 32);
684 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
685 misc_reg, lower, upper, v);
686 } else {
687 miscRegs[lower] = v;
688 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
689 misc_reg, lower, v);
690 }
691}
692
693void
694ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
695{
696
697 MiscReg newVal = val;
698 bool secure_lookup;
699 SCR scr;
700
701 if (misc_reg == MISCREG_CPSR) {
702 updateRegMap(val);
703
704
705 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
706 int old_mode = old_cpsr.mode;
707 CPSR cpsr = val;
708 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
709 getITBPtr(tc)->invalidateMiscReg();
710 getDTBPtr(tc)->invalidateMiscReg();
711 }
712
713 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
714 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
715 PCState pc = tc->pcState();
716 pc.nextThumb(cpsr.t);
717 pc.nextJazelle(cpsr.j);
718 pc.illegalExec(cpsr.il == 1);
719
720 // Follow slightly different semantics if a CheckerCPU object
721 // is connected
722 CheckerCPU *checker = tc->getCheckerCpuPtr();
723 if (checker) {
724 tc->pcStateNoRecord(pc);
725 } else {
726 tc->pcState(pc);
727 }
728 } else {
729#ifndef NDEBUG
730 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
731 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
732 warn("Unimplemented system register %s write with %#x.\n",
733 miscRegName[misc_reg], val);
734 else
735 panic("Unimplemented system register %s write with %#x.\n",
736 miscRegName[misc_reg], val);
737 }
738#endif
739 switch (unflattenMiscReg(misc_reg)) {
740 case MISCREG_CPACR:
741 {
742
743 const uint32_t ones = (uint32_t)(-1);
744 CPACR cpacrMask = 0;
745 // Only cp10, cp11, and ase are implemented, nothing else should
746 // be writable
747 cpacrMask.cp10 = ones;
748 cpacrMask.cp11 = ones;
749 cpacrMask.asedis = ones;
750
751 // Security Extensions may limit the writability of CPACR
752 if (haveSecurity) {
753 scr = readMiscRegNoEffect(MISCREG_SCR);
754 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
755 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
756 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
757 // NB: Skipping the full loop, here
758 if (!nsacr.cp10) cpacrMask.cp10 = 0;
759 if (!nsacr.cp11) cpacrMask.cp11 = 0;
760 }
761 }
762
763 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
764 newVal &= cpacrMask;
765 newVal |= old_val & ~cpacrMask;
766 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
767 miscRegName[misc_reg], newVal);
768 }
769 break;
770 case MISCREG_CPTR_EL2:
771 {
772 const uint32_t ones = (uint32_t)(-1);
773 CPTR cptrMask = 0;
774 cptrMask.tcpac = ones;
775 cptrMask.tta = ones;
776 cptrMask.tfp = ones;
777 newVal &= cptrMask;
778 cptrMask = 0;
779 cptrMask.res1_13_12_el2 = ones;
780 cptrMask.res1_9_0_el2 = ones;
781 newVal |= cptrMask;
782 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
783 miscRegName[misc_reg], newVal);
784 }
785 break;
786 case MISCREG_CPTR_EL3:
787 {
788 const uint32_t ones = (uint32_t)(-1);
789 CPTR cptrMask = 0;
790 cptrMask.tcpac = ones;
791 cptrMask.tta = ones;
792 cptrMask.tfp = ones;
793 newVal &= cptrMask;
794 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
795 miscRegName[misc_reg], newVal);
796 }
797 break;
798 case MISCREG_CSSELR:
799 warn_once("The csselr register isn't implemented.\n");
800 return;
801
802 case MISCREG_DC_ZVA_Xt:
803 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
804 return;
805
806 case MISCREG_FPSCR:
807 {
808 const uint32_t ones = (uint32_t)(-1);
809 FPSCR fpscrMask = 0;
810 fpscrMask.ioc = ones;
811 fpscrMask.dzc = ones;
812 fpscrMask.ofc = ones;
813 fpscrMask.ufc = ones;
814 fpscrMask.ixc = ones;
815 fpscrMask.idc = ones;
816 fpscrMask.ioe = ones;
817 fpscrMask.dze = ones;
818 fpscrMask.ofe = ones;
819 fpscrMask.ufe = ones;
820 fpscrMask.ixe = ones;
821 fpscrMask.ide = ones;
822 fpscrMask.len = ones;
823 fpscrMask.stride = ones;
824 fpscrMask.rMode = ones;
825 fpscrMask.fz = ones;
826 fpscrMask.dn = ones;
827 fpscrMask.ahp = ones;
828 fpscrMask.qc = ones;
829 fpscrMask.v = ones;
830 fpscrMask.c = ones;
831 fpscrMask.z = ones;
832 fpscrMask.n = ones;
833 newVal = (newVal & (uint32_t)fpscrMask) |
834 (readMiscRegNoEffect(MISCREG_FPSCR) &
835 ~(uint32_t)fpscrMask);
836 tc->getDecoderPtr()->setContext(newVal);
837 }
838 break;
839 case MISCREG_FPSR:
840 {
841 const uint32_t ones = (uint32_t)(-1);
842 FPSCR fpscrMask = 0;
843 fpscrMask.ioc = ones;
844 fpscrMask.dzc = ones;
845 fpscrMask.ofc = ones;
846 fpscrMask.ufc = ones;
847 fpscrMask.ixc = ones;
848 fpscrMask.idc = ones;
849 fpscrMask.qc = ones;
850 fpscrMask.v = ones;
851 fpscrMask.c = ones;
852 fpscrMask.z = ones;
853 fpscrMask.n = ones;
854 newVal = (newVal & (uint32_t)fpscrMask) |
855 (readMiscRegNoEffect(MISCREG_FPSCR) &
856 ~(uint32_t)fpscrMask);
857 misc_reg = MISCREG_FPSCR;
858 }
859 break;
860 case MISCREG_FPCR:
861 {
862 const uint32_t ones = (uint32_t)(-1);
863 FPSCR fpscrMask = 0;
864 fpscrMask.len = ones;
865 fpscrMask.stride = ones;
866 fpscrMask.rMode = ones;
867 fpscrMask.fz = ones;
868 fpscrMask.dn = ones;
869 fpscrMask.ahp = ones;
870 newVal = (newVal & (uint32_t)fpscrMask) |
871 (readMiscRegNoEffect(MISCREG_FPSCR) &
872 ~(uint32_t)fpscrMask);
873 misc_reg = MISCREG_FPSCR;
874 }
875 break;
876 case MISCREG_CPSR_Q:
877 {
878 assert(!(newVal & ~CpsrMaskQ));
879 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
880 misc_reg = MISCREG_CPSR;
881 }
882 break;
883 case MISCREG_FPSCR_QC:
884 {
885 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
886 (newVal & FpscrQcMask);
887 misc_reg = MISCREG_FPSCR;
888 }
889 break;
890 case MISCREG_FPSCR_EXC:
891 {
892 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
893 (newVal & FpscrExcMask);
894 misc_reg = MISCREG_FPSCR;
895 }
896 break;
897 case MISCREG_FPEXC:
898 {
899 // vfpv3 architecture, section B.6.1 of DDI04068
900 // bit 29 - valid only if fpexc[31] is 0
901 const uint32_t fpexcMask = 0x60000000;
902 newVal = (newVal & fpexcMask) |
903 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
904 }
905 break;
906 case MISCREG_HCR:
907 {
908 if (!haveVirtualization)
909 return;
910 }
911 break;
912 case MISCREG_IFSR:
913 {
914 // ARM ARM (ARM DDI 0406C.b) B4.1.96
915 const uint32_t ifsrMask =
916 mask(31, 13) | mask(11, 11) | mask(8, 6);
917 newVal = newVal & ~ifsrMask;
918 }
919 break;
920 case MISCREG_DFSR:
921 {
922 // ARM ARM (ARM DDI 0406C.b) B4.1.52
923 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
924 newVal = newVal & ~dfsrMask;
925 }
926 break;
927 case MISCREG_AMAIR0:
928 case MISCREG_AMAIR1:
929 {
930 // ARM ARM (ARM DDI 0406C.b) B4.1.5
931 // Valid only with LPAE
932 if (!haveLPAE)
933 return;
934 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
935 }
936 break;
937 case MISCREG_SCR:
938 getITBPtr(tc)->invalidateMiscReg();
939 getDTBPtr(tc)->invalidateMiscReg();
940 break;
941 case MISCREG_SCTLR:
942 {
943 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
944 scr = readMiscRegNoEffect(MISCREG_SCR);
945
946 MiscRegIndex sctlr_idx;
947 if (haveSecurity && !highestELIs64 && !scr.ns) {
948 sctlr_idx = MISCREG_SCTLR_S;
949 } else {
950 sctlr_idx = MISCREG_SCTLR_NS;
951 }
952
953 SCTLR sctlr = miscRegs[sctlr_idx];
954 SCTLR new_sctlr = newVal;
955 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
956 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
957 getITBPtr(tc)->invalidateMiscReg();
958 getDTBPtr(tc)->invalidateMiscReg();
959 }
960 case MISCREG_MIDR:
961 case MISCREG_ID_PFR0:
962 case MISCREG_ID_PFR1:
963 case MISCREG_ID_DFR0:
964 case MISCREG_ID_MMFR0:
965 case MISCREG_ID_MMFR1:
966 case MISCREG_ID_MMFR2:
967 case MISCREG_ID_MMFR3:
968 case MISCREG_ID_ISAR0:
969 case MISCREG_ID_ISAR1:
970 case MISCREG_ID_ISAR2:
971 case MISCREG_ID_ISAR3:
972 case MISCREG_ID_ISAR4:
973 case MISCREG_ID_ISAR5:
974
975 case MISCREG_MPIDR:
976 case MISCREG_FPSID:
977 case MISCREG_TLBTR:
978 case MISCREG_MVFR0:
979 case MISCREG_MVFR1:
980
981 case MISCREG_ID_AA64AFR0_EL1:
982 case MISCREG_ID_AA64AFR1_EL1:
983 case MISCREG_ID_AA64DFR0_EL1:
984 case MISCREG_ID_AA64DFR1_EL1:
985 case MISCREG_ID_AA64ISAR0_EL1:
986 case MISCREG_ID_AA64ISAR1_EL1:
987 case MISCREG_ID_AA64MMFR0_EL1:
988 case MISCREG_ID_AA64MMFR1_EL1:
989 case MISCREG_ID_AA64PFR0_EL1:
990 case MISCREG_ID_AA64PFR1_EL1:
991 // ID registers are constants.
992 return;
993
994 // TLB Invalidate All
995 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
996 {
997 assert32(tc);
998 scr = readMiscReg(MISCREG_SCR, tc);
999
1000 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1001 tlbiOp(tc);
1002 return;
1003 }
1004 // TLB Invalidate All, Inner Shareable
1005 case MISCREG_TLBIALLIS:
1006 {
1007 assert32(tc);
1008 scr = readMiscReg(MISCREG_SCR, tc);
1009
1010 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1011 tlbiOp.broadcast(tc);
1012 return;
1013 }
1014 // Instruction TLB Invalidate All
1015 case MISCREG_ITLBIALL:
1016 {
1017 assert32(tc);
1018 scr = readMiscReg(MISCREG_SCR, tc);
1019
1020 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1021 tlbiOp(tc);
1022 return;
1023 }
1024 // Data TLB Invalidate All
1025 case MISCREG_DTLBIALL:
1026 {
1027 assert32(tc);
1028 scr = readMiscReg(MISCREG_SCR, tc);
1029
1030 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1031 tlbiOp(tc);
1032 return;
1033 }
1034 // TLB Invalidate by VA
1035 // mcr tlbimval(is) is invalidating all matching entries
1036 // regardless of the level of lookup, since in gem5 we cache
1037 // in the tlb the last level of lookup only.
1038 case MISCREG_TLBIMVA:
1039 case MISCREG_TLBIMVAL:
1040 {
1041 assert32(tc);
1042 scr = readMiscReg(MISCREG_SCR, tc);
1043
1044 TLBIMVA tlbiOp(EL1,
1045 haveSecurity && !scr.ns,
1046 mbits(newVal, 31, 12),
1047 bits(newVal, 7,0));
1048
1049 tlbiOp(tc);
1050 return;
1051 }
1052 // TLB Invalidate by VA, Inner Shareable
1053 case MISCREG_TLBIMVAIS:
1054 case MISCREG_TLBIMVALIS:
1055 {
1056 assert32(tc);
1057 scr = readMiscReg(MISCREG_SCR, tc);
1058
1059 TLBIMVA tlbiOp(EL1,
1060 haveSecurity && !scr.ns,
1061 mbits(newVal, 31, 12),
1062 bits(newVal, 7,0));
1063
1064 tlbiOp.broadcast(tc);
1065 return;
1066 }
1067 // TLB Invalidate by ASID match
1068 case MISCREG_TLBIASID:
1069 {
1070 assert32(tc);
1071 scr = readMiscReg(MISCREG_SCR, tc);
1072
1073 TLBIASID tlbiOp(EL1,
1074 haveSecurity && !scr.ns,
1075 bits(newVal, 7,0));
1076
1077 tlbiOp(tc);
1078 return;
1079 }
1080 // TLB Invalidate by ASID match, Inner Shareable
1081 case MISCREG_TLBIASIDIS:
1082 {
1083 assert32(tc);
1084 scr = readMiscReg(MISCREG_SCR, tc);
1085
1086 TLBIASID tlbiOp(EL1,
1087 haveSecurity && !scr.ns,
1088 bits(newVal, 7,0));
1089
1090 tlbiOp.broadcast(tc);
1091 return;
1092 }
1093 // mcr tlbimvaal(is) is invalidating all matching entries
1094 // regardless of the level of lookup, since in gem5 we cache
1095 // in the tlb the last level of lookup only.
1096 // TLB Invalidate by VA, All ASID
1097 case MISCREG_TLBIMVAA:
1098 case MISCREG_TLBIMVAAL:
1099 {
1100 assert32(tc);
1101 scr = readMiscReg(MISCREG_SCR, tc);
1102
1103 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1104 mbits(newVal, 31,12), false);
1105
1106 tlbiOp(tc);
1107 return;
1108 }
1109 // TLB Invalidate by VA, All ASID, Inner Shareable
1110 case MISCREG_TLBIMVAAIS:
1111 case MISCREG_TLBIMVAALIS:
1112 {
1113 assert32(tc);
1114 scr = readMiscReg(MISCREG_SCR, tc);
1115
1116 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1117 mbits(newVal, 31,12), false);
1118
1119 tlbiOp.broadcast(tc);
1120 return;
1121 }
1122 // mcr tlbimvalh(is) is invalidating all matching entries
1123 // regardless of the level of lookup, since in gem5 we cache
1124 // in the tlb the last level of lookup only.
1125 // TLB Invalidate by VA, Hyp mode
1126 case MISCREG_TLBIMVAH:
1127 case MISCREG_TLBIMVALH:
1128 {
1129 assert32(tc);
1130 scr = readMiscReg(MISCREG_SCR, tc);
1131
1132 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1133 mbits(newVal, 31,12), true);
1134
1135 tlbiOp(tc);
1136 return;
1137 }
1138 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1139 case MISCREG_TLBIMVAHIS:
1140 case MISCREG_TLBIMVALHIS:
1141 {
1142 assert32(tc);
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144
1145 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1146 mbits(newVal, 31,12), true);
1147
1148 tlbiOp.broadcast(tc);
1149 return;
1150 }
1151 // mcr tlbiipas2l(is) is invalidating all matching entries
1152 // regardless of the level of lookup, since in gem5 we cache
1153 // in the tlb the last level of lookup only.
1154 // TLB Invalidate by Intermediate Physical Address, Stage 2
1155 case MISCREG_TLBIIPAS2:
1156 case MISCREG_TLBIIPAS2L:
1157 {
1158 assert32(tc);
1159 scr = readMiscReg(MISCREG_SCR, tc);
1160
1161 TLBIIPA tlbiOp(EL1,
1162 haveSecurity && !scr.ns,
1163 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1164
1165 tlbiOp(tc);
1166 return;
1167 }
1168 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1169 // Inner Shareable
1170 case MISCREG_TLBIIPAS2IS:
1171 case MISCREG_TLBIIPAS2LIS:
1172 {
1173 assert32(tc);
1174 scr = readMiscReg(MISCREG_SCR, tc);
1175
1176 TLBIIPA tlbiOp(EL1,
1177 haveSecurity && !scr.ns,
1178 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1179
1180 tlbiOp.broadcast(tc);
1181 return;
1182 }
1183 // Instruction TLB Invalidate by VA
1184 case MISCREG_ITLBIMVA:
1185 {
1186 assert32(tc);
1187 scr = readMiscReg(MISCREG_SCR, tc);
1188
1189 ITLBIMVA tlbiOp(EL1,
1190 haveSecurity && !scr.ns,
1191 mbits(newVal, 31, 12),
1192 bits(newVal, 7,0));
1193
1194 tlbiOp(tc);
1195 return;
1196 }
1197 // Data TLB Invalidate by VA
1198 case MISCREG_DTLBIMVA:
1199 {
1200 assert32(tc);
1201 scr = readMiscReg(MISCREG_SCR, tc);
1202
1203 DTLBIMVA tlbiOp(EL1,
1204 haveSecurity && !scr.ns,
1205 mbits(newVal, 31, 12),
1206 bits(newVal, 7,0));
1207
1208 tlbiOp(tc);
1209 return;
1210 }
1211 // Instruction TLB Invalidate by ASID match
1212 case MISCREG_ITLBIASID:
1213 {
1214 assert32(tc);
1215 scr = readMiscReg(MISCREG_SCR, tc);
1216
1217 ITLBIASID tlbiOp(EL1,
1218 haveSecurity && !scr.ns,
1219 bits(newVal, 7,0));
1220
1221 tlbiOp(tc);
1222 return;
1223 }
1224 // Data TLB Invalidate by ASID match
1225 case MISCREG_DTLBIASID:
1226 {
1227 assert32(tc);
1228 scr = readMiscReg(MISCREG_SCR, tc);
1229
1230 DTLBIASID tlbiOp(EL1,
1231 haveSecurity && !scr.ns,
1232 bits(newVal, 7,0));
1233
1234 tlbiOp(tc);
1235 return;
1236 }
1237 // TLB Invalidate All, Non-Secure Non-Hyp
1238 case MISCREG_TLBIALLNSNH:
1239 {
1240 assert32(tc);
1241
1242 TLBIALLN tlbiOp(EL1, false);
1243 tlbiOp(tc);
1244 return;
1245 }
1246 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1247 case MISCREG_TLBIALLNSNHIS:
1248 {
1249 assert32(tc);
1250
1251 TLBIALLN tlbiOp(EL1, false);
1252 tlbiOp.broadcast(tc);
1253 return;
1254 }
1255 // TLB Invalidate All, Hyp mode
1256 case MISCREG_TLBIALLH:
1257 {
1258 assert32(tc);
1259
1260 TLBIALLN tlbiOp(EL1, true);
1261 tlbiOp(tc);
1262 return;
1263 }
1264 // TLB Invalidate All, Hyp mode, Inner Shareable
1265 case MISCREG_TLBIALLHIS:
1266 {
1267 assert32(tc);
1268
1269 TLBIALLN tlbiOp(EL1, true);
1270 tlbiOp.broadcast(tc);
1271 return;
1272 }
1273 // AArch64 TLB Invalidate All, EL3
1274 case MISCREG_TLBI_ALLE3:
1275 {
1276 assert64(tc);
1277
1278 TLBIALL tlbiOp(EL3, true);
1279 tlbiOp(tc);
1280 return;
1281 }
1282 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1283 case MISCREG_TLBI_ALLE3IS:
1284 {
1285 assert64(tc);
1286
1287 TLBIALL tlbiOp(EL3, true);
1288 tlbiOp.broadcast(tc);
1289 return;
1290 }
1291 // @todo: uncomment this to enable Virtualization
1292 // case MISCREG_TLBI_ALLE2IS:
1293 // case MISCREG_TLBI_ALLE2:
1294 // AArch64 TLB Invalidate All, EL1
1295 case MISCREG_TLBI_ALLE1:
1296 case MISCREG_TLBI_VMALLE1:
1297 case MISCREG_TLBI_VMALLS12E1:
1298 // @todo: handle VMID and stage 2 to enable Virtualization
1299 {
1300 assert64(tc);
1301 scr = readMiscReg(MISCREG_SCR, tc);
1302
1303 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1304 tlbiOp(tc);
1305 return;
1306 }
1307 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1308 case MISCREG_TLBI_ALLE1IS:
1309 case MISCREG_TLBI_VMALLE1IS:
1310 case MISCREG_TLBI_VMALLS12E1IS:
1311 // @todo: handle VMID and stage 2 to enable Virtualization
1312 {
1313 assert64(tc);
1314 scr = readMiscReg(MISCREG_SCR, tc);
1315
1316 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1317 tlbiOp.broadcast(tc);
1318 return;
1319 }
1320 // VAEx(IS) and VALEx(IS) are the same because TLBs
1321 // only store entries
1322 // from the last level of translation table walks
1323 // @todo: handle VMID to enable Virtualization
1324 // AArch64 TLB Invalidate by VA, EL3
1325 case MISCREG_TLBI_VAE3_Xt:
1326 case MISCREG_TLBI_VALE3_Xt:
1327 {
1328 assert64(tc);
1329
1330 TLBIMVA tlbiOp(EL3, true,
1331 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1332 0xbeef);
1333 tlbiOp(tc);
1334 return;
1335 }
1336 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1337 case MISCREG_TLBI_VAE3IS_Xt:
1338 case MISCREG_TLBI_VALE3IS_Xt:
1339 {
1340 assert64(tc);
1341
1342 TLBIMVA tlbiOp(EL3, true,
1343 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1344 0xbeef);
1345
1346 tlbiOp.broadcast(tc);
1347 return;
1348 }
1349 // AArch64 TLB Invalidate by VA, EL2
1350 case MISCREG_TLBI_VAE2_Xt:
1351 case MISCREG_TLBI_VALE2_Xt:
1352 {
1353 assert64(tc);
1354 scr = readMiscReg(MISCREG_SCR, tc);
1355
1356 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1357 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1358 0xbeef);
1359 tlbiOp(tc);
1360 return;
1361 }
1362 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1363 case MISCREG_TLBI_VAE2IS_Xt:
1364 case MISCREG_TLBI_VALE2IS_Xt:
1365 {
1366 assert64(tc);
1367 scr = readMiscReg(MISCREG_SCR, tc);
1368
1369 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1370 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1371 0xbeef);
1372
1373 tlbiOp.broadcast(tc);
1374 return;
1375 }
1376 // AArch64 TLB Invalidate by VA, EL1
1377 case MISCREG_TLBI_VAE1_Xt:
1378 case MISCREG_TLBI_VALE1_Xt:
1379 {
1380 assert64(tc);
1381 scr = readMiscReg(MISCREG_SCR, tc);
1382 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1383 bits(newVal, 55, 48);
1384
1385 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1386 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1387 asid);
1388
1389 tlbiOp(tc);
1390 return;
1391 }
1392 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1393 case MISCREG_TLBI_VAE1IS_Xt:
1394 case MISCREG_TLBI_VALE1IS_Xt:
1395 {
1396 assert64(tc);
1397 scr = readMiscReg(MISCREG_SCR, tc);
1398 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1399 bits(newVal, 55, 48);
1400
1401 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1402 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1403 asid);
1404
1405 tlbiOp.broadcast(tc);
1406 return;
1407 }
1408 // AArch64 TLB Invalidate by ASID, EL1
1409 // @todo: handle VMID to enable Virtualization
1410 case MISCREG_TLBI_ASIDE1_Xt:
1411 {
1412 assert64(tc);
1413 scr = readMiscReg(MISCREG_SCR, tc);
1414 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1415 bits(newVal, 55, 48);
1416
1417 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1418 tlbiOp(tc);
1419 return;
1420 }
1421 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1422 case MISCREG_TLBI_ASIDE1IS_Xt:
1423 {
1424 assert64(tc);
1425 scr = readMiscReg(MISCREG_SCR, tc);
1426 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1427 bits(newVal, 55, 48);
1428
1429 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1430 tlbiOp.broadcast(tc);
1431 return;
1432 }
1433 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1434 // entries from the last level of translation table walks
1435 // AArch64 TLB Invalidate by VA, All ASID, EL1
1436 case MISCREG_TLBI_VAAE1_Xt:
1437 case MISCREG_TLBI_VAALE1_Xt:
1438 {
1439 assert64(tc);
1440 scr = readMiscReg(MISCREG_SCR, tc);
1441
1442 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1443 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1444
1445 tlbiOp(tc);
1446 return;
1447 }
1448 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1449 case MISCREG_TLBI_VAAE1IS_Xt:
1450 case MISCREG_TLBI_VAALE1IS_Xt:
1451 {
1452 assert64(tc);
1453 scr = readMiscReg(MISCREG_SCR, tc);
1454
1455 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1456 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1457
1458 tlbiOp.broadcast(tc);
1459 return;
1460 }
1461 // AArch64 TLB Invalidate by Intermediate Physical Address,
1462 // Stage 2, EL1
1463 case MISCREG_TLBI_IPAS2E1_Xt:
1464 case MISCREG_TLBI_IPAS2LE1_Xt:
1465 {
1466 assert64(tc);
1467 scr = readMiscReg(MISCREG_SCR, tc);
1468
1469 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1470 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1471
1472 tlbiOp(tc);
1473 return;
1474 }
1475 // AArch64 TLB Invalidate by Intermediate Physical Address,
1476 // Stage 2, EL1, Inner Shareable
1477 case MISCREG_TLBI_IPAS2E1IS_Xt:
1478 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1479 {
1480 assert64(tc);
1481 scr = readMiscReg(MISCREG_SCR, tc);
1482
1483 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1484 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1485
1486 tlbiOp.broadcast(tc);
1487 return;
1488 }
1489 case MISCREG_ACTLR:
1490 warn("Not doing anything for write of miscreg ACTLR\n");
1491 break;
1492
1493 case MISCREG_PMXEVTYPER_PMCCFILTR:
1494 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1495 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1496 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1497 pmu->setMiscReg(misc_reg, newVal);
1498 break;
1499
1500
1501 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1502 {
1503 HSTR hstrMask = 0;
1504 hstrMask.tjdbx = 1;
1505 newVal &= ~((uint32_t) hstrMask);
1506 break;
1507 }
1508 case MISCREG_HCPTR:
1509 {
1510 // If a CP bit in NSACR is 0 then the corresponding bit in
1511 // HCPTR is RAO/WI. Same applies to NSASEDIS
1512 secure_lookup = haveSecurity &&
1513 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1514 readMiscRegNoEffect(MISCREG_CPSR));
1515 if (!secure_lookup) {
1516 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1517 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1518 newVal = (newVal & ~mask) | (oldValue & mask);
1519 }
1520 break;
1521 }
1522 case MISCREG_HDFAR: // alias for secure DFAR
1523 misc_reg = MISCREG_DFAR_S;
1524 break;
1525 case MISCREG_HIFAR: // alias for secure IFAR
1526 misc_reg = MISCREG_IFAR_S;
1527 break;
1528 case MISCREG_ATS1CPR:
1529 case MISCREG_ATS1CPW:
1530 case MISCREG_ATS1CUR:
1531 case MISCREG_ATS1CUW:
1532 case MISCREG_ATS12NSOPR:
1533 case MISCREG_ATS12NSOPW:
1534 case MISCREG_ATS12NSOUR:
1535 case MISCREG_ATS12NSOUW:
1536 case MISCREG_ATS1HR:
1537 case MISCREG_ATS1HW:
1538 {
1539 Request::Flags flags = 0;
1540 BaseTLB::Mode mode = BaseTLB::Read;
1541 TLB::ArmTranslationType tranType = TLB::NormalTran;
1542 Fault fault;
1543 switch(misc_reg) {
1544 case MISCREG_ATS1CPR:
1545 flags = TLB::MustBeOne;
1546 tranType = TLB::S1CTran;
1547 mode = BaseTLB::Read;
1548 break;
1549 case MISCREG_ATS1CPW:
1550 flags = TLB::MustBeOne;
1551 tranType = TLB::S1CTran;
1552 mode = BaseTLB::Write;
1553 break;
1554 case MISCREG_ATS1CUR:
1555 flags = TLB::MustBeOne | TLB::UserMode;
1556 tranType = TLB::S1CTran;
1557 mode = BaseTLB::Read;
1558 break;
1559 case MISCREG_ATS1CUW:
1560 flags = TLB::MustBeOne | TLB::UserMode;
1561 tranType = TLB::S1CTran;
1562 mode = BaseTLB::Write;
1563 break;
1564 case MISCREG_ATS12NSOPR:
1565 if (!haveSecurity)
1566 panic("Security Extensions required for ATS12NSOPR");
1567 flags = TLB::MustBeOne;
1568 tranType = TLB::S1S2NsTran;
1569 mode = BaseTLB::Read;
1570 break;
1571 case MISCREG_ATS12NSOPW:
1572 if (!haveSecurity)
1573 panic("Security Extensions required for ATS12NSOPW");
1574 flags = TLB::MustBeOne;
1575 tranType = TLB::S1S2NsTran;
1576 mode = BaseTLB::Write;
1577 break;
1578 case MISCREG_ATS12NSOUR:
1579 if (!haveSecurity)
1580 panic("Security Extensions required for ATS12NSOUR");
1581 flags = TLB::MustBeOne | TLB::UserMode;
1582 tranType = TLB::S1S2NsTran;
1583 mode = BaseTLB::Read;
1584 break;
1585 case MISCREG_ATS12NSOUW:
1586 if (!haveSecurity)
1587 panic("Security Extensions required for ATS12NSOUW");
1588 flags = TLB::MustBeOne | TLB::UserMode;
1589 tranType = TLB::S1S2NsTran;
1590 mode = BaseTLB::Write;
1591 break;
1592 case MISCREG_ATS1HR: // only really useful from secure mode.
1593 flags = TLB::MustBeOne;
1594 tranType = TLB::HypMode;
1595 mode = BaseTLB::Read;
1596 break;
1597 case MISCREG_ATS1HW:
1598 flags = TLB::MustBeOne;
1599 tranType = TLB::HypMode;
1600 mode = BaseTLB::Write;
1601 break;
1602 }
1603 // If we're in timing mode then doing the translation in
1604 // functional mode then we're slightly distorting performance
1605 // results obtained from simulations. The translation should be
1606 // done in the same mode the core is running in. NOTE: This
1607 // can't be an atomic translation because that causes problems
1608 // with unexpected atomic snoop requests.
1609 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1610
1611 auto req = std::make_shared<Request>(
1612 0, val, 0, flags, Request::funcMasterId,
1613 tc->pcState().pc(), tc->contextId());
1614
1615 fault = getDTBPtr(tc)->translateFunctional(
1616 req, tc, mode, tranType);
1617
1618 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1619 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1620
1621 MiscReg newVal;
1622 if (fault == NoFault) {
1623 Addr paddr = req->getPaddr();
1624 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1625 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1626 newVal = (paddr & mask(39, 12)) |
1627 (getDTBPtr(tc)->getAttr());
1628 } else {
1629 newVal = (paddr & 0xfffff000) |
1630 (getDTBPtr(tc)->getAttr());
1631 }
1632 DPRINTF(MiscRegs,
1633 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1634 val, newVal);
1635 } else {
1636 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1637 armFault->update(tc);
1638 // Set fault bit and FSR
1639 FSR fsr = armFault->getFsr(tc);
1640
1641 newVal = ((fsr >> 9) & 1) << 11;
1642 if (newVal) {
1643 // LPAE - rearange fault status
1644 newVal |= ((fsr >> 0) & 0x3f) << 1;
1645 } else {
1646 // VMSA - rearange fault status
1647 newVal |= ((fsr >> 0) & 0xf) << 1;
1648 newVal |= ((fsr >> 10) & 0x1) << 5;
1649 newVal |= ((fsr >> 12) & 0x1) << 6;
1650 }
1651 newVal |= 0x1; // F bit
1652 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1653 newVal |= armFault->isStage2() ? 0x200 : 0;
1654 DPRINTF(MiscRegs,
1655 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1656 val, fsr, newVal);
1657 }
1658 setMiscRegNoEffect(MISCREG_PAR, newVal);
1659 return;
1660 }
1661 case MISCREG_TTBCR:
1662 {
1663 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1664 const uint32_t ones = (uint32_t)(-1);
1665 TTBCR ttbcrMask = 0;
1666 TTBCR ttbcrNew = newVal;
1667
1668 // ARM DDI 0406C.b, ARMv7-32
1669 ttbcrMask.n = ones; // T0SZ
1670 if (haveSecurity) {
1671 ttbcrMask.pd0 = ones;
1672 ttbcrMask.pd1 = ones;
1673 }
1674 ttbcrMask.epd0 = ones;
1675 ttbcrMask.irgn0 = ones;
1676 ttbcrMask.orgn0 = ones;
1677 ttbcrMask.sh0 = ones;
1678 ttbcrMask.ps = ones; // T1SZ
1679 ttbcrMask.a1 = ones;
1680 ttbcrMask.epd1 = ones;
1681 ttbcrMask.irgn1 = ones;
1682 ttbcrMask.orgn1 = ones;
1683 ttbcrMask.sh1 = ones;
1684 if (haveLPAE)
1685 ttbcrMask.eae = ones;
1686
1687 if (haveLPAE && ttbcrNew.eae) {
1688 newVal = newVal & ttbcrMask;
1689 } else {
1690 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1691 }
1692 // Invalidate TLB MiscReg
1693 getITBPtr(tc)->invalidateMiscReg();
1694 getDTBPtr(tc)->invalidateMiscReg();
1695 break;
1696 }
1697 case MISCREG_TTBR0:
1698 case MISCREG_TTBR1:
1699 {
1700 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1701 if (haveLPAE) {
1702 if (ttbcr.eae) {
1703 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1704 // ARMv8 AArch32 bit 63-56 only
1705 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1706 newVal = (newVal & (~ttbrMask));
1707 }
1708 }
1709 // Invalidate TLB MiscReg
1710 getITBPtr(tc)->invalidateMiscReg();
1711 getDTBPtr(tc)->invalidateMiscReg();
1712 break;
1713 }
1714 case MISCREG_SCTLR_EL1:
1715 case MISCREG_CONTEXTIDR:
1716 case MISCREG_PRRR:
1717 case MISCREG_NMRR:
1718 case MISCREG_MAIR0:
1719 case MISCREG_MAIR1:
1720 case MISCREG_DACR:
1721 case MISCREG_VTTBR:
1722 case MISCREG_SCR_EL3:
1723 case MISCREG_HCR_EL2:
1724 case MISCREG_TCR_EL1:
1725 case MISCREG_TCR_EL2:
1726 case MISCREG_TCR_EL3:
1727 case MISCREG_SCTLR_EL2:
1728 case MISCREG_SCTLR_EL3:
1729 case MISCREG_HSCTLR:
1730 case MISCREG_TTBR0_EL1:
1731 case MISCREG_TTBR1_EL1:
1732 case MISCREG_TTBR0_EL2:
1733 case MISCREG_TTBR1_EL2:
1734 case MISCREG_TTBR0_EL3:
1735 getITBPtr(tc)->invalidateMiscReg();
1736 getDTBPtr(tc)->invalidateMiscReg();
1737 break;
1738 case MISCREG_NZCV:
1739 {
1740 CPSR cpsr = val;
1741
1742 tc->setCCReg(CCREG_NZ, cpsr.nz);
1743 tc->setCCReg(CCREG_C, cpsr.c);
1744 tc->setCCReg(CCREG_V, cpsr.v);
1745 }
1746 break;
1747 case MISCREG_DAIF:
1748 {
1749 CPSR cpsr = miscRegs[MISCREG_CPSR];
1750 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1751 newVal = cpsr;
1752 misc_reg = MISCREG_CPSR;
1753 }
1754 break;
1755 case MISCREG_SP_EL0:
1756 tc->setIntReg(INTREG_SP0, newVal);
1757 break;
1758 case MISCREG_SP_EL1:
1759 tc->setIntReg(INTREG_SP1, newVal);
1760 break;
1761 case MISCREG_SP_EL2:
1762 tc->setIntReg(INTREG_SP2, newVal);
1763 break;
1764 case MISCREG_SPSEL:
1765 {
1766 CPSR cpsr = miscRegs[MISCREG_CPSR];
1767 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1768 newVal = cpsr;
1769 misc_reg = MISCREG_CPSR;
1770 }
1771 break;
1772 case MISCREG_CURRENTEL:
1773 {
1774 CPSR cpsr = miscRegs[MISCREG_CPSR];
1775 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1776 newVal = cpsr;
1777 misc_reg = MISCREG_CPSR;
1778 }
1779 break;
1780 case MISCREG_AT_S1E1R_Xt:
1781 case MISCREG_AT_S1E1W_Xt:
1782 case MISCREG_AT_S1E0R_Xt:
1783 case MISCREG_AT_S1E0W_Xt:
1784 case MISCREG_AT_S1E2R_Xt:
1785 case MISCREG_AT_S1E2W_Xt:
1786 case MISCREG_AT_S12E1R_Xt:
1787 case MISCREG_AT_S12E1W_Xt:
1788 case MISCREG_AT_S12E0R_Xt:
1789 case MISCREG_AT_S12E0W_Xt:
1790 case MISCREG_AT_S1E3R_Xt:
1791 case MISCREG_AT_S1E3W_Xt:
1792 {
1793 RequestPtr req = std::make_shared<Request>();
1794 Request::Flags flags = 0;
1795 BaseTLB::Mode mode = BaseTLB::Read;
1796 TLB::ArmTranslationType tranType = TLB::NormalTran;
1797 Fault fault;
1798 switch(misc_reg) {
1799 case MISCREG_AT_S1E1R_Xt:
1800 flags = TLB::MustBeOne;
1801 tranType = TLB::S1E1Tran;
1802 mode = BaseTLB::Read;
1803 break;
1804 case MISCREG_AT_S1E1W_Xt:
1805 flags = TLB::MustBeOne;
1806 tranType = TLB::S1E1Tran;
1807 mode = BaseTLB::Write;
1808 break;
1809 case MISCREG_AT_S1E0R_Xt:
1810 flags = TLB::MustBeOne | TLB::UserMode;
1811 tranType = TLB::S1E0Tran;
1812 mode = BaseTLB::Read;
1813 break;
1814 case MISCREG_AT_S1E0W_Xt:
1815 flags = TLB::MustBeOne | TLB::UserMode;
1816 tranType = TLB::S1E0Tran;
1817 mode = BaseTLB::Write;
1818 break;
1819 case MISCREG_AT_S1E2R_Xt:
1820 flags = TLB::MustBeOne;
1821 tranType = TLB::S1E2Tran;
1822 mode = BaseTLB::Read;
1823 break;
1824 case MISCREG_AT_S1E2W_Xt:
1825 flags = TLB::MustBeOne;
1826 tranType = TLB::S1E2Tran;
1827 mode = BaseTLB::Write;
1828 break;
1829 case MISCREG_AT_S12E0R_Xt:
1830 flags = TLB::MustBeOne | TLB::UserMode;
1831 tranType = TLB::S12E0Tran;
1832 mode = BaseTLB::Read;
1833 break;
1834 case MISCREG_AT_S12E0W_Xt:
1835 flags = TLB::MustBeOne | TLB::UserMode;
1836 tranType = TLB::S12E0Tran;
1837 mode = BaseTLB::Write;
1838 break;
1839 case MISCREG_AT_S12E1R_Xt:
1840 flags = TLB::MustBeOne;
1841 tranType = TLB::S12E1Tran;
1842 mode = BaseTLB::Read;
1843 break;
1844 case MISCREG_AT_S12E1W_Xt:
1845 flags = TLB::MustBeOne;
1846 tranType = TLB::S12E1Tran;
1847 mode = BaseTLB::Write;
1848 break;
1849 case MISCREG_AT_S1E3R_Xt:
1850 flags = TLB::MustBeOne;
1851 tranType = TLB::S1E3Tran;
1852 mode = BaseTLB::Read;
1853 break;
1854 case MISCREG_AT_S1E3W_Xt:
1855 flags = TLB::MustBeOne;
1856 tranType = TLB::S1E3Tran;
1857 mode = BaseTLB::Write;
1858 break;
1859 }
1860 // If we're in timing mode then doing the translation in
1861 // functional mode then we're slightly distorting performance
1862 // results obtained from simulations. The translation should be
1863 // done in the same mode the core is running in. NOTE: This
1864 // can't be an atomic translation because that causes problems
1865 // with unexpected atomic snoop requests.
1866 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1867 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1868 tc->pcState().pc());
1869 req->setContext(tc->contextId());
1870 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1871 tranType);
1872
1873 MiscReg newVal;
1874 if (fault == NoFault) {
1875 Addr paddr = req->getPaddr();
1876 uint64_t attr = getDTBPtr(tc)->getAttr();
1877 uint64_t attr1 = attr >> 56;
1878 if (!attr1 || attr1 ==0x44) {
1879 attr |= 0x100;
1880 attr &= ~ uint64_t(0x80);
1881 }
1882 newVal = (paddr & mask(47, 12)) | attr;
1883 DPRINTF(MiscRegs,
1884 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1885 val, newVal);
1886 } else {
1887 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1888 armFault->update(tc);
1889 // Set fault bit and FSR
1890 FSR fsr = armFault->getFsr(tc);
1891
1892 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1893 if (cpsr.width) { // AArch32
1894 newVal = ((fsr >> 9) & 1) << 11;
1895 // rearrange fault status
1896 newVal |= ((fsr >> 0) & 0x3f) << 1;
1897 newVal |= 0x1; // F bit
1898 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1899 newVal |= armFault->isStage2() ? 0x200 : 0;
1900 } else { // AArch64
1901 newVal = 1; // F bit
1902 newVal |= fsr << 1; // FST
1903 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1904 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1905 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1906 newVal |= 1 << 11; // RES1
1907 }
1908 DPRINTF(MiscRegs,
1909 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1910 val, fsr, newVal);
1911 }
1912 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1913 return;
1914 }
1915 case MISCREG_SPSR_EL3:
1916 case MISCREG_SPSR_EL2:
1917 case MISCREG_SPSR_EL1:
1918 // Force bits 23:21 to 0
1919 newVal = val & ~(0x7 << 21);
1920 break;
1921 case MISCREG_L2CTLR:
1922 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1923 miscRegName[misc_reg], uint32_t(val));
1924 break;
1925
1926 // Generic Timer registers
1927 case MISCREG_CNTHV_CTL_EL2:
1928 case MISCREG_CNTHV_CVAL_EL2:
1929 case MISCREG_CNTHV_TVAL_EL2:
1930 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1931 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1932 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1933 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1934 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1935 break;
1936 }
1937 }
1938 setMiscRegNoEffect(misc_reg, newVal);
1939}
1940
1941BaseISADevice &
1942ISA::getGenericTimer(ThreadContext *tc)
1943{
1944 // We only need to create an ISA interface the first time we try
1945 // to access the timer.
1946 if (timer)
1947 return *timer.get();
1948
1949 assert(system);
1950 GenericTimer *generic_timer(system->getGenericTimer());
1951 if (!generic_timer) {
1952 panic("Trying to get a generic timer from a system that hasn't "
1953 "been configured to use a generic timer.\n");
1954 }
1955
1956 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1957 timer->setThreadContext(tc);
1958
1959 return *timer.get();
1960}
1961
1962}
1963
1964ArmISA::ISA *
1965ArmISAParams::create()
1966{
1967 return new ArmISA::ISA(this);
1968}