1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * When two mapping registers are given, they are the 32b lower and
62 * upper halves, respectively, of the 64b register being mapped.
63 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
64 */
65void
66ISA::initializeMiscRegMetadata()
67{
68 InitReg(MISCREG_ACTLR_EL1).mapsTo(MISCREG_ACTLR_NS);
69 InitReg(MISCREG_AFSR0_EL1).mapsTo(MISCREG_ADFSR_NS);
70 InitReg(MISCREG_AFSR1_EL1).mapsTo(MISCREG_AIFSR_NS);
71 InitReg(MISCREG_AMAIR_EL1).mapsTo(MISCREG_AMAIR0_NS,
72 MISCREG_AMAIR1_NS);
73 InitReg(MISCREG_CONTEXTIDR_EL1).mapsTo(MISCREG_CONTEXTIDR_NS);
74 InitReg(MISCREG_CPACR_EL1).mapsTo(MISCREG_CPACR);
75 InitReg(MISCREG_CSSELR_EL1).mapsTo(MISCREG_CSSELR_NS);
76 InitReg(MISCREG_DACR32_EL2).mapsTo(MISCREG_DACR_NS);
77 InitReg(MISCREG_FAR_EL1).mapsTo(MISCREG_DFAR_NS,
78 MISCREG_IFAR_NS);
79 // ESR_EL1 -> DFSR
80 InitReg(MISCREG_HACR_EL2).mapsTo(MISCREG_HACR);
81 InitReg(MISCREG_ACTLR_EL2).mapsTo(MISCREG_HACTLR);
82 InitReg(MISCREG_AFSR0_EL2).mapsTo(MISCREG_HADFSR);
83 InitReg(MISCREG_AFSR1_EL2).mapsTo(MISCREG_HAIFSR);
84 InitReg(MISCREG_AMAIR_EL2).mapsTo(MISCREG_HAMAIR0,
85 MISCREG_HAMAIR1);
86 InitReg(MISCREG_CPTR_EL2).mapsTo(MISCREG_HCPTR);
87 InitReg(MISCREG_HCR_EL2).mapsTo(MISCREG_HCR /*,
88 MISCREG_HCR2*/);
89 InitReg(MISCREG_MDCR_EL2).mapsTo(MISCREG_HDCR);
90 InitReg(MISCREG_FAR_EL2).mapsTo(MISCREG_HDFAR,
91 MISCREG_HIFAR);
92 InitReg(MISCREG_MAIR_EL2).mapsTo(MISCREG_HMAIR0,
93 MISCREG_HMAIR1);
94 InitReg(MISCREG_HPFAR_EL2).mapsTo(MISCREG_HPFAR);
95 InitReg(MISCREG_SCTLR_EL2).mapsTo(MISCREG_HSCTLR);
96 InitReg(MISCREG_ESR_EL2).mapsTo(MISCREG_HSR);
97 InitReg(MISCREG_HSTR_EL2).mapsTo(MISCREG_HSTR);
98 InitReg(MISCREG_TCR_EL2).mapsTo(MISCREG_HTCR);
99 InitReg(MISCREG_TPIDR_EL2).mapsTo(MISCREG_HTPIDR);
100 InitReg(MISCREG_TTBR0_EL2).mapsTo(MISCREG_HTTBR);
101 InitReg(MISCREG_VBAR_EL2).mapsTo(MISCREG_HVBAR);
102 InitReg(MISCREG_IFSR32_EL2).mapsTo(MISCREG_IFSR_NS);
103 InitReg(MISCREG_MAIR_EL1).mapsTo(MISCREG_PRRR_NS,
104 MISCREG_NMRR_NS);
105 InitReg(MISCREG_PAR_EL1).mapsTo(MISCREG_PAR_NS);
106 // RMR_EL1 -> RMR
107 // RMR_EL2 -> HRMR
108 InitReg(MISCREG_SCTLR_EL1).mapsTo(MISCREG_SCTLR_NS);
109 InitReg(MISCREG_SDER32_EL3).mapsTo(MISCREG_SDER);
110 InitReg(MISCREG_TPIDR_EL1).mapsTo(MISCREG_TPIDRPRW_NS);
111 InitReg(MISCREG_TPIDRRO_EL0).mapsTo(MISCREG_TPIDRURO_NS);
112 InitReg(MISCREG_TPIDR_EL0).mapsTo(MISCREG_TPIDRURW_NS);
113 InitReg(MISCREG_TCR_EL1).mapsTo(MISCREG_TTBCR_NS);
114 InitReg(MISCREG_TTBR0_EL1).mapsTo(MISCREG_TTBR0_NS);
115 InitReg(MISCREG_TTBR1_EL1).mapsTo(MISCREG_TTBR1_NS);
116 InitReg(MISCREG_VBAR_EL1).mapsTo(MISCREG_VBAR_NS);
117 InitReg(MISCREG_VMPIDR_EL2).mapsTo(MISCREG_VMPIDR);
118 InitReg(MISCREG_VPIDR_EL2).mapsTo(MISCREG_VPIDR);
119 InitReg(MISCREG_VTCR_EL2).mapsTo(MISCREG_VTCR);
120 InitReg(MISCREG_VTTBR_EL2).mapsTo(MISCREG_VTTBR);
121 InitReg(MISCREG_CNTFRQ_EL0).mapsTo(MISCREG_CNTFRQ);
122 InitReg(MISCREG_CNTHCTL_EL2).mapsTo(MISCREG_CNTHCTL);
123 InitReg(MISCREG_CNTHP_CTL_EL2).mapsTo(MISCREG_CNTHP_CTL);
124 InitReg(MISCREG_CNTHP_CVAL_EL2).mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
125 InitReg(MISCREG_CNTHP_TVAL_EL2).mapsTo(MISCREG_CNTHP_TVAL);
126 InitReg(MISCREG_CNTKCTL_EL1).mapsTo(MISCREG_CNTKCTL);
127 InitReg(MISCREG_CNTP_CTL_EL0).mapsTo(MISCREG_CNTP_CTL_NS);
128 InitReg(MISCREG_CNTP_CVAL_EL0).mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
129 InitReg(MISCREG_CNTP_TVAL_EL0).mapsTo(MISCREG_CNTP_TVAL_NS);
130 InitReg(MISCREG_CNTPCT_EL0).mapsTo(MISCREG_CNTPCT); /* 64b */
131 InitReg(MISCREG_CNTV_CTL_EL0).mapsTo(MISCREG_CNTV_CTL);
132 InitReg(MISCREG_CNTV_CVAL_EL0).mapsTo(MISCREG_CNTV_CVAL); /* 64b */
133 InitReg(MISCREG_CNTV_TVAL_EL0).mapsTo(MISCREG_CNTV_TVAL);
134 InitReg(MISCREG_CNTVCT_EL0).mapsTo(MISCREG_CNTVCT); /* 64b */
135 InitReg(MISCREG_CNTVOFF_EL2).mapsTo(MISCREG_CNTVOFF); /* 64b */
136 InitReg(MISCREG_DBGAUTHSTATUS_EL1).mapsTo(MISCREG_DBGAUTHSTATUS);
137 InitReg(MISCREG_DBGBCR0_EL1).mapsTo(MISCREG_DBGBCR0);
138 InitReg(MISCREG_DBGBCR1_EL1).mapsTo(MISCREG_DBGBCR1);
139 InitReg(MISCREG_DBGBCR2_EL1).mapsTo(MISCREG_DBGBCR2);
140 InitReg(MISCREG_DBGBCR3_EL1).mapsTo(MISCREG_DBGBCR3);
141 InitReg(MISCREG_DBGBCR4_EL1).mapsTo(MISCREG_DBGBCR4);
142 InitReg(MISCREG_DBGBCR5_EL1).mapsTo(MISCREG_DBGBCR5);
143 InitReg(MISCREG_DBGBVR0_EL1).mapsTo(MISCREG_DBGBVR0 /*,
144 MISCREG_DBGBXVR0 */);
145 InitReg(MISCREG_DBGBVR1_EL1).mapsTo(MISCREG_DBGBVR1 /*,
146 MISCREG_DBGBXVR1 */);
147 InitReg(MISCREG_DBGBVR2_EL1).mapsTo(MISCREG_DBGBVR2 /*,
148 MISCREG_DBGBXVR2 */);
149 InitReg(MISCREG_DBGBVR3_EL1).mapsTo(MISCREG_DBGBVR3 /*,
150 MISCREG_DBGBXVR3 */);
151 InitReg(MISCREG_DBGBVR4_EL1).mapsTo(MISCREG_DBGBVR4 /*,
152 MISCREG_DBGBXVR4 */);
153 InitReg(MISCREG_DBGBVR5_EL1).mapsTo(MISCREG_DBGBVR5 /*,
154 MISCREG_DBGBXVR5 */);
155 InitReg(MISCREG_DBGCLAIMSET_EL1).mapsTo(MISCREG_DBGCLAIMSET);
156 InitReg(MISCREG_DBGCLAIMCLR_EL1).mapsTo(MISCREG_DBGCLAIMCLR);
157 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
158 // DBGDTRRX_EL0 -> DBGDTRRXint
159 // DBGDTRTX_EL0 -> DBGDTRRXint
160 InitReg(MISCREG_DBGPRCR_EL1).mapsTo(MISCREG_DBGPRCR);
161 InitReg(MISCREG_DBGVCR32_EL2).mapsTo(MISCREG_DBGVCR);
162 InitReg(MISCREG_DBGWCR0_EL1).mapsTo(MISCREG_DBGWCR0);
163 InitReg(MISCREG_DBGWCR1_EL1).mapsTo(MISCREG_DBGWCR1);
164 InitReg(MISCREG_DBGWCR2_EL1).mapsTo(MISCREG_DBGWCR2);
165 InitReg(MISCREG_DBGWCR3_EL1).mapsTo(MISCREG_DBGWCR3);
166 InitReg(MISCREG_DBGWVR0_EL1).mapsTo(MISCREG_DBGWVR0);
167 InitReg(MISCREG_DBGWVR1_EL1).mapsTo(MISCREG_DBGWVR1);
168 InitReg(MISCREG_DBGWVR2_EL1).mapsTo(MISCREG_DBGWVR2);
169 InitReg(MISCREG_DBGWVR3_EL1).mapsTo(MISCREG_DBGWVR3);
170 InitReg(MISCREG_ID_DFR0_EL1).mapsTo(MISCREG_ID_DFR0);
171 InitReg(MISCREG_MDCCSR_EL0).mapsTo(MISCREG_DBGDSCRint);
172 InitReg(MISCREG_MDRAR_EL1).mapsTo(MISCREG_DBGDRAR);
173 InitReg(MISCREG_MDSCR_EL1).mapsTo(MISCREG_DBGDSCRext);
174 InitReg(MISCREG_OSDLR_EL1).mapsTo(MISCREG_DBGOSDLR);
175 InitReg(MISCREG_OSDTRRX_EL1).mapsTo(MISCREG_DBGDTRRXext);
176 InitReg(MISCREG_OSDTRTX_EL1).mapsTo(MISCREG_DBGDTRTXext);
177 InitReg(MISCREG_OSECCR_EL1).mapsTo(MISCREG_DBGOSECCR);
178 InitReg(MISCREG_OSLAR_EL1).mapsTo(MISCREG_DBGOSLAR);
179 InitReg(MISCREG_OSLSR_EL1).mapsTo(MISCREG_DBGOSLSR);
180 InitReg(MISCREG_PMCCNTR_EL0).mapsTo(MISCREG_PMCCNTR);
181 InitReg(MISCREG_PMCEID0_EL0).mapsTo(MISCREG_PMCEID0);
182 InitReg(MISCREG_PMCEID1_EL0).mapsTo(MISCREG_PMCEID1);
183 InitReg(MISCREG_PMCNTENSET_EL0).mapsTo(MISCREG_PMCNTENSET);
184 InitReg(MISCREG_PMCNTENCLR_EL0).mapsTo(MISCREG_PMCNTENCLR);
185 InitReg(MISCREG_PMCR_EL0).mapsTo(MISCREG_PMCR);
186/* InitReg(MISCREG_PMEVCNTR0_EL0).mapsTo(MISCREG_PMEVCNTR0);
187 InitReg(MISCREG_PMEVCNTR1_EL0).mapsTo(MISCREG_PMEVCNTR1);
188 InitReg(MISCREG_PMEVCNTR2_EL0).mapsTo(MISCREG_PMEVCNTR2);
189 InitReg(MISCREG_PMEVCNTR3_EL0).mapsTo(MISCREG_PMEVCNTR3);
190 InitReg(MISCREG_PMEVCNTR4_EL0).mapsTo(MISCREG_PMEVCNTR4);
191 InitReg(MISCREG_PMEVCNTR5_EL0).mapsTo(MISCREG_PMEVCNTR5);
192 InitReg(MISCREG_PMEVTYPER0_EL0).mapsTo(MISCREG_PMEVTYPER0);
193 InitReg(MISCREG_PMEVTYPER1_EL0).mapsTo(MISCREG_PMEVTYPER1);
194 InitReg(MISCREG_PMEVTYPER2_EL0).mapsTo(MISCREG_PMEVTYPER2);
195 InitReg(MISCREG_PMEVTYPER3_EL0).mapsTo(MISCREG_PMEVTYPER3);
196 InitReg(MISCREG_PMEVTYPER4_EL0).mapsTo(MISCREG_PMEVTYPER4);
197 InitReg(MISCREG_PMEVTYPER5_EL0).mapsTo(MISCREG_PMEVTYPER5); */
198 InitReg(MISCREG_PMINTENCLR_EL1).mapsTo(MISCREG_PMINTENCLR);
199 InitReg(MISCREG_PMINTENSET_EL1).mapsTo(MISCREG_PMINTENSET);
200// InitReg(MISCREG_PMOVSCLR_EL0).mapsTo(MISCREG_PMOVSCLR);
201 InitReg(MISCREG_PMOVSSET_EL0).mapsTo(MISCREG_PMOVSSET);
202 InitReg(MISCREG_PMSELR_EL0).mapsTo(MISCREG_PMSELR);
203 InitReg(MISCREG_PMSWINC_EL0).mapsTo(MISCREG_PMSWINC);
204 InitReg(MISCREG_PMUSERENR_EL0).mapsTo(MISCREG_PMUSERENR);
205 InitReg(MISCREG_PMXEVCNTR_EL0).mapsTo(MISCREG_PMXEVCNTR);
206 InitReg(MISCREG_PMXEVTYPER_EL0).mapsTo(MISCREG_PMXEVTYPER);
207
208 InitReg(MISCREG_SCR).res0(0xff40) // [31:16], [6]
209 .res1(0x0030); // [5:4]
210
211 // from ARM DDI 0487A.i, template text
212 // "AArch64 System register ___ can be mapped to
213 // AArch32 System register ___, but this is not
214 // architecturally mandated."
215 InitReg(MISCREG_SCR_EL3).mapsTo(MISCREG_SCR); // D7-2005
216 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
217 InitReg(MISCREG_SPSR_EL1).mapsTo(MISCREG_SPSR_SVC); // C5.2.17 SPSR_EL1
218 InitReg(MISCREG_SPSR_EL2).mapsTo(MISCREG_SPSR_HYP); // C5.2.18 SPSR_EL2
219 InitReg(MISCREG_SPSR_EL3).mapsTo(MISCREG_SPSR_MON); // C5.2.19 SPSR_EL3
220}
221
222ISA::ISA(Params *p)
223 : SimObject(p),
224 system(NULL),
225 _decoderFlavour(p->decoderFlavour),
226 _vecRegRenameMode(p->vecRegRenameMode),
227 pmu(p->pmu),
228 lookUpMiscReg(NUM_MISCREGS)
229{
230 miscRegs[MISCREG_SCTLR_RST] = 0;
231
232 // Hook up a dummy device if we haven't been configured with a
233 // real PMU. By using a dummy device, we don't need to check that
234 // the PMU exist every time we try to access a PMU register.
235 if (!pmu)
236 pmu = &dummyDevice;
237
238 // Give all ISA devices a pointer to this ISA
239 pmu->setISA(this);
240
241 system = dynamic_cast<ArmSystem *>(p->system);
242
243 // Cache system-level properties
244 if (FullSystem && system) {
245 highestELIs64 = system->highestELIs64();
246 haveSecurity = system->haveSecurity();
247 haveLPAE = system->haveLPAE();
248 haveVirtualization = system->haveVirtualization();
249 haveLargeAsid64 = system->haveLargeAsid64();
250 physAddrRange64 = system->physAddrRange64();
251 } else {
252 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
253 haveSecurity = haveLPAE = haveVirtualization = false;
254 haveLargeAsid64 = false;
255 physAddrRange64 = 32; // dummy value
256 }
257
258 initializeMiscRegMetadata();
259 preUnflattenMiscReg();
260
261 clear();
262}
263
264const ArmISAParams *
265ISA::params() const
266{
267 return dynamic_cast<const Params *>(_params);
268}
269
270void
271ISA::clear()
272{
273 const Params *p(params());
274
275 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
276 memset(miscRegs, 0, sizeof(miscRegs));
277
278 // Initialize configurable default values
279 miscRegs[MISCREG_MIDR] = p->midr;
280 miscRegs[MISCREG_MIDR_EL1] = p->midr;
281 miscRegs[MISCREG_VPIDR] = p->midr;
282
283 if (FullSystem && system->highestELIs64()) {
284 // Initialize AArch64 state
285 clear64(p);
286 return;
287 }
288
289 // Initialize AArch32 state...
290
291 CPSR cpsr = 0;
292 cpsr.mode = MODE_USER;
293 miscRegs[MISCREG_CPSR] = cpsr;
294 updateRegMap(cpsr);
295
296 SCTLR sctlr = 0;
297 sctlr.te = (bool) sctlr_rst.te;
298 sctlr.nmfi = (bool) sctlr_rst.nmfi;
299 sctlr.v = (bool) sctlr_rst.v;
300 sctlr.u = 1;
301 sctlr.xp = 1;
302 sctlr.rao2 = 1;
303 sctlr.rao3 = 1;
304 sctlr.rao4 = 0xf; // SCTLR[6:3]
305 sctlr.uci = 1;
306 sctlr.dze = 1;
307 miscRegs[MISCREG_SCTLR_NS] = sctlr;
308 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
309 miscRegs[MISCREG_HCPTR] = 0;
310
311 // Start with an event in the mailbox
312 miscRegs[MISCREG_SEV_MAILBOX] = 1;
313
314 // Separate Instruction and Data TLBs
315 miscRegs[MISCREG_TLBTR] = 1;
316
317 MVFR0 mvfr0 = 0;
318 mvfr0.advSimdRegisters = 2;
319 mvfr0.singlePrecision = 2;
320 mvfr0.doublePrecision = 2;
321 mvfr0.vfpExceptionTrapping = 0;
322 mvfr0.divide = 1;
323 mvfr0.squareRoot = 1;
324 mvfr0.shortVectors = 1;
325 mvfr0.roundingModes = 1;
326 miscRegs[MISCREG_MVFR0] = mvfr0;
327
328 MVFR1 mvfr1 = 0;
329 mvfr1.flushToZero = 1;
330 mvfr1.defaultNaN = 1;
331 mvfr1.advSimdLoadStore = 1;
332 mvfr1.advSimdInteger = 1;
333 mvfr1.advSimdSinglePrecision = 1;
334 mvfr1.advSimdHalfPrecision = 1;
335 mvfr1.vfpHalfPrecision = 1;
336 miscRegs[MISCREG_MVFR1] = mvfr1;
337
338 // Reset values of PRRR and NMRR are implementation dependent
339
340 // @todo: PRRR and NMRR in secure state?
341 miscRegs[MISCREG_PRRR_NS] =
342 (1 << 19) | // 19
343 (0 << 18) | // 18
344 (0 << 17) | // 17
345 (1 << 16) | // 16
346 (2 << 14) | // 15:14
347 (0 << 12) | // 13:12
348 (2 << 10) | // 11:10
349 (2 << 8) | // 9:8
350 (2 << 6) | // 7:6
351 (2 << 4) | // 5:4
352 (1 << 2) | // 3:2
353 0; // 1:0
354 miscRegs[MISCREG_NMRR_NS] =
355 (1 << 30) | // 31:30
356 (0 << 26) | // 27:26
357 (0 << 24) | // 25:24
358 (3 << 22) | // 23:22
359 (2 << 20) | // 21:20
360 (0 << 18) | // 19:18
361 (0 << 16) | // 17:16
362 (1 << 14) | // 15:14
363 (0 << 12) | // 13:12
364 (2 << 10) | // 11:10
365 (0 << 8) | // 9:8
366 (3 << 6) | // 7:6
367 (2 << 4) | // 5:4
368 (0 << 2) | // 3:2
369 0; // 1:0
370
371 miscRegs[MISCREG_CPACR] = 0;
372
373 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
374 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
375 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
376 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
377
378 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
379 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
380 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
381 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
382 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
383 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
384
385 miscRegs[MISCREG_FPSID] = p->fpsid;
386
387 if (haveLPAE) {
388 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
389 ttbcr.eae = 0;
390 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
391 // Enforce consistency with system-level settings
392 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
393 }
394
395 if (haveSecurity) {
396 miscRegs[MISCREG_SCTLR_S] = sctlr;
397 miscRegs[MISCREG_SCR] = 0;
398 miscRegs[MISCREG_VBAR_S] = 0;
399 } else {
400 // we're always non-secure
401 miscRegs[MISCREG_SCR] = 1;
402 }
403
404 //XXX We need to initialize the rest of the state.
405}
406
407void
408ISA::clear64(const ArmISAParams *p)
409{
410 CPSR cpsr = 0;
411 Addr rvbar = system->resetAddr64();
412 switch (system->highestEL()) {
413 // Set initial EL to highest implemented EL using associated stack
414 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
415 // value
416 case EL3:
417 cpsr.mode = MODE_EL3H;
418 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
419 break;
420 case EL2:
421 cpsr.mode = MODE_EL2H;
422 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
423 break;
424 case EL1:
425 cpsr.mode = MODE_EL1H;
426 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
427 break;
428 default:
429 panic("Invalid highest implemented exception level");
430 break;
431 }
432
433 // Initialize rest of CPSR
434 cpsr.daif = 0xf; // Mask all interrupts
435 cpsr.ss = 0;
436 cpsr.il = 0;
437 miscRegs[MISCREG_CPSR] = cpsr;
438 updateRegMap(cpsr);
439
440 // Initialize other control registers
441 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
442 if (haveSecurity) {
443 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
444 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
445 } else if (haveVirtualization) {
446 // also MISCREG_SCTLR_EL2 (by mapping)
447 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
448 } else {
449 // also MISCREG_SCTLR_EL1 (by mapping)
450 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
451 // Always non-secure
452 miscRegs[MISCREG_SCR_EL3] = 1;
453 }
454
455 // Initialize configurable id registers
456 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
457 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
458 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
459 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
460 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
461
462 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
463 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
464 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
465 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
466 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
467
468 miscRegs[MISCREG_ID_DFR0_EL1] =
469 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
470
471 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
472
473 // Enforce consistency with system-level settings...
474
475 // EL3
476 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
477 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
478 haveSecurity ? 0x2 : 0x0);
479 // EL2
480 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
481 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
482 haveVirtualization ? 0x2 : 0x0);
483 // Large ASID support
484 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
485 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
486 haveLargeAsid64 ? 0x2 : 0x0);
487 // Physical address size
488 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
489 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
490 encodePhysAddrRange64(physAddrRange64));
491}
492
493MiscReg
494ISA::readMiscRegNoEffect(int misc_reg) const
495{
496 assert(misc_reg < NumMiscRegs);
497
498 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
499 const auto &map = getMiscIndices(misc_reg);
500 int lower = map.first, upper = map.second;
501 // NB!: apply architectural masks according to desired register,
502 // despite possibly getting value from different (mapped) register.
503 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
504 |(miscRegs[upper] << 32));
505 if (val & reg.res0()) {
506 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
507 miscRegName[misc_reg], val & reg.res0());
508 }
509 if ((val & reg.res1()) != reg.res1()) {
510 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
511 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
512 }
513 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
514}
515
516
517MiscReg
518ISA::readMiscReg(int misc_reg, ThreadContext *tc)
519{
520 CPSR cpsr = 0;
521 PCState pc = 0;
522 SCR scr = 0;
523
524 if (misc_reg == MISCREG_CPSR) {
525 cpsr = miscRegs[misc_reg];
526 pc = tc->pcState();
527 cpsr.j = pc.jazelle() ? 1 : 0;
528 cpsr.t = pc.thumb() ? 1 : 0;
529 return cpsr;
530 }
531
532#ifndef NDEBUG
533 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
534 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
535 warn("Unimplemented system register %s read.\n",
536 miscRegName[misc_reg]);
537 else
538 panic("Unimplemented system register %s read.\n",
539 miscRegName[misc_reg]);
540 }
541#endif
542
543 switch (unflattenMiscReg(misc_reg)) {
544 case MISCREG_HCR:
545 {
546 if (!haveVirtualization)
547 return 0;
548 else
549 return readMiscRegNoEffect(MISCREG_HCR);
550 }
551 case MISCREG_CPACR:
552 {
553 const uint32_t ones = (uint32_t)(-1);
554 CPACR cpacrMask = 0;
555 // Only cp10, cp11, and ase are implemented, nothing else should
556 // be readable? (straight copy from the write code)
557 cpacrMask.cp10 = ones;
558 cpacrMask.cp11 = ones;
559 cpacrMask.asedis = ones;
560
561 // Security Extensions may limit the readability of CPACR
562 if (haveSecurity) {
563 scr = readMiscRegNoEffect(MISCREG_SCR);
564 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
565 if (scr.ns && (cpsr.mode != MODE_MON)) {
566 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
567 // NB: Skipping the full loop, here
568 if (!nsacr.cp10) cpacrMask.cp10 = 0;
569 if (!nsacr.cp11) cpacrMask.cp11 = 0;
570 }
571 }
572 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
573 val &= cpacrMask;
574 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
575 miscRegName[misc_reg], val);
576 return val;
577 }
578 case MISCREG_MPIDR:
579 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
580 scr = readMiscRegNoEffect(MISCREG_SCR);
581 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
582 return getMPIDR(system, tc);
583 } else {
584 return readMiscReg(MISCREG_VMPIDR, tc);
585 }
586 break;
587 case MISCREG_MPIDR_EL1:
588 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
589 return getMPIDR(system, tc) & 0xffffffff;
590 case MISCREG_VMPIDR:
591 // top bit defined as RES1
592 return readMiscRegNoEffect(misc_reg) | 0x80000000;
593 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
594 case MISCREG_REVIDR: // not implemented, so alias MIDR
595 case MISCREG_MIDR:
596 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
597 scr = readMiscRegNoEffect(MISCREG_SCR);
598 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
599 return readMiscRegNoEffect(misc_reg);
600 } else {
601 return readMiscRegNoEffect(MISCREG_VPIDR);
602 }
603 break;
604 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
605 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
606 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
607 case MISCREG_AIDR: // AUX ID set to 0
608 case MISCREG_TCMTR: // No TCM's
609 return 0;
610
611 case MISCREG_CLIDR:
612 warn_once("The clidr register always reports 0 caches.\n");
613 warn_once("clidr LoUIS field of 0b001 to match current "
614 "ARM implementations.\n");
615 return 0x00200000;
616 case MISCREG_CCSIDR:
617 warn_once("The ccsidr register isn't implemented and "
618 "always reads as 0.\n");
619 break;
620 case MISCREG_CTR: // AArch32, ARMv7, top bit set
621 case MISCREG_CTR_EL0: // AArch64
622 {
623 //all caches have the same line size in gem5
624 //4 byte words in ARM
625 unsigned lineSizeWords =
626 tc->getSystemPtr()->cacheLineSize() / 4;
627 unsigned log2LineSizeWords = 0;
628
629 while (lineSizeWords >>= 1) {
630 ++log2LineSizeWords;
631 }
632
633 CTR ctr = 0;
634 //log2 of minimun i-cache line size (words)
635 ctr.iCacheLineSize = log2LineSizeWords;
636 //b11 - gem5 uses pipt
637 ctr.l1IndexPolicy = 0x3;
638 //log2 of minimum d-cache line size (words)
639 ctr.dCacheLineSize = log2LineSizeWords;
640 //log2 of max reservation size (words)
641 ctr.erg = log2LineSizeWords;
642 //log2 of max writeback size (words)
643 ctr.cwg = log2LineSizeWords;
644 //b100 - gem5 format is ARMv7
645 ctr.format = 0x4;
646
647 return ctr;
648 }
649 case MISCREG_ACTLR:
650 warn("Not doing anything for miscreg ACTLR\n");
651 break;
652
653 case MISCREG_PMXEVTYPER_PMCCFILTR:
654 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
655 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
656 case MISCREG_PMCR ... MISCREG_PMOVSSET:
657 return pmu->readMiscReg(misc_reg);
658
659 case MISCREG_CPSR_Q:
660 panic("shouldn't be reading this register seperately\n");
661 case MISCREG_FPSCR_QC:
662 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
663 case MISCREG_FPSCR_EXC:
664 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
665 case MISCREG_FPSR:
666 {
667 const uint32_t ones = (uint32_t)(-1);
668 FPSCR fpscrMask = 0;
669 fpscrMask.ioc = ones;
670 fpscrMask.dzc = ones;
671 fpscrMask.ofc = ones;
672 fpscrMask.ufc = ones;
673 fpscrMask.ixc = ones;
674 fpscrMask.idc = ones;
675 fpscrMask.qc = ones;
676 fpscrMask.v = ones;
677 fpscrMask.c = ones;
678 fpscrMask.z = ones;
679 fpscrMask.n = ones;
680 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
681 }
682 case MISCREG_FPCR:
683 {
684 const uint32_t ones = (uint32_t)(-1);
685 FPSCR fpscrMask = 0;
686 fpscrMask.ioe = ones;
687 fpscrMask.dze = ones;
688 fpscrMask.ofe = ones;
689 fpscrMask.ufe = ones;
690 fpscrMask.ixe = ones;
691 fpscrMask.ide = ones;
692 fpscrMask.len = ones;
693 fpscrMask.stride = ones;
694 fpscrMask.rMode = ones;
695 fpscrMask.fz = ones;
696 fpscrMask.dn = ones;
697 fpscrMask.ahp = ones;
698 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
699 }
700 case MISCREG_NZCV:
701 {
702 CPSR cpsr = 0;
703 cpsr.nz = tc->readCCReg(CCREG_NZ);
704 cpsr.c = tc->readCCReg(CCREG_C);
705 cpsr.v = tc->readCCReg(CCREG_V);
706 return cpsr;
707 }
708 case MISCREG_DAIF:
709 {
710 CPSR cpsr = 0;
711 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
712 return cpsr;
713 }
714 case MISCREG_SP_EL0:
715 {
716 return tc->readIntReg(INTREG_SP0);
717 }
718 case MISCREG_SP_EL1:
719 {
720 return tc->readIntReg(INTREG_SP1);
721 }
722 case MISCREG_SP_EL2:
723 {
724 return tc->readIntReg(INTREG_SP2);
725 }
726 case MISCREG_SPSEL:
727 {
728 return miscRegs[MISCREG_CPSR] & 0x1;
729 }
730 case MISCREG_CURRENTEL:
731 {
732 return miscRegs[MISCREG_CPSR] & 0xc;
733 }
734 case MISCREG_L2CTLR:
735 {
736 // mostly unimplemented, just set NumCPUs field from sim and return
737 L2CTLR l2ctlr = 0;
738 // b00:1CPU to b11:4CPUs
739 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
740 return l2ctlr;
741 }
742 case MISCREG_DBGDIDR:
743 /* For now just implement the version number.
744 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
745 */
746 return 0x5 << 16;
747 case MISCREG_DBGDSCRint:
748 return 0;
749 case MISCREG_ISR:
750 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
751 readMiscRegNoEffect(MISCREG_HCR),
752 readMiscRegNoEffect(MISCREG_CPSR),
753 readMiscRegNoEffect(MISCREG_SCR));
754 case MISCREG_ISR_EL1:
755 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
756 readMiscRegNoEffect(MISCREG_HCR_EL2),
757 readMiscRegNoEffect(MISCREG_CPSR),
758 readMiscRegNoEffect(MISCREG_SCR_EL3));
759 case MISCREG_DCZID_EL0:
760 return 0x04; // DC ZVA clear 64-byte chunks
761 case MISCREG_HCPTR:
762 {
763 MiscReg val = readMiscRegNoEffect(misc_reg);
764 // The trap bit associated with CP14 is defined as RAZ
765 val &= ~(1 << 14);
766 // If a CP bit in NSACR is 0 then the corresponding bit in
767 // HCPTR is RAO/WI
768 bool secure_lookup = haveSecurity &&
769 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
770 readMiscRegNoEffect(MISCREG_CPSR));
771 if (!secure_lookup) {
772 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
773 val |= (mask ^ 0x7FFF) & 0xBFFF;
774 }
775 // Set the bits for unimplemented coprocessors to RAO/WI
776 val |= 0x33FF;
777 return (val);
778 }
779 case MISCREG_HDFAR: // alias for secure DFAR
780 return readMiscRegNoEffect(MISCREG_DFAR_S);
781 case MISCREG_HIFAR: // alias for secure IFAR
782 return readMiscRegNoEffect(MISCREG_IFAR_S);
783 case MISCREG_HVBAR: // bottom bits reserved
784 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
785 case MISCREG_SCTLR:
786 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
787 case MISCREG_SCTLR_EL1:
788 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
789 case MISCREG_SCTLR_EL2:
790 case MISCREG_SCTLR_EL3:
791 case MISCREG_HSCTLR:
792 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
793
794 case MISCREG_ID_PFR0:
795 // !ThumbEE | !Jazelle | Thumb | ARM
796 return 0x00000031;
797 case MISCREG_ID_PFR1:
798 { // Timer | Virti | !M Profile | TrustZone | ARMv4
799 bool haveTimer = (system->getGenericTimer() != NULL);
800 return 0x00000001
801 | (haveSecurity ? 0x00000010 : 0x0)
802 | (haveVirtualization ? 0x00001000 : 0x0)
803 | (haveTimer ? 0x00010000 : 0x0);
804 }
805 case MISCREG_ID_AA64PFR0_EL1:
806 return 0x0000000000000002 // AArch{64,32} supported at EL0
807 | 0x0000000000000020 // EL1
808 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
809 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
810 case MISCREG_ID_AA64PFR1_EL1:
811 return 0; // bits [63:0] RES0 (reserved for future use)
812
813 // Generic Timer registers
814 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
815 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
816 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
817 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
818 return getGenericTimer(tc).readMiscReg(misc_reg);
819
820 default:
821 break;
822
823 }
824 return readMiscRegNoEffect(misc_reg);
825}
826
827void
828ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
829{
830 assert(misc_reg < NumMiscRegs);
831
832 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
833 const auto &map = getMiscIndices(misc_reg);
834 int lower = map.first, upper = map.second;
835
836 auto v = (val & ~reg.wi()) | reg.rao();
837 if (upper > 0) {
838 miscRegs[lower] = bits(v, 31, 0);
839 miscRegs[upper] = bits(v, 63, 32);
840 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
841 misc_reg, lower, upper, v);
842 } else {
843 miscRegs[lower] = v;
844 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
845 misc_reg, lower, v);
846 }
847}
848
849namespace {
850
851template<typename T>
852TLB *
853getITBPtr(T *tc)
854{
855 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
856 assert(tlb);
857 return tlb;
858}
859
860template<typename T>
861TLB *
862getDTBPtr(T *tc)
863{
864 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
865 assert(tlb);
866 return tlb;
867}
868
869} // anonymous namespace
870
871void
872ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
873{
874
875 MiscReg newVal = val;
876 int x;
877 bool secure_lookup;
878 bool hyp;
879 System *sys;
880 ThreadContext *oc;
881 uint8_t target_el;
882 uint16_t asid;
883 SCR scr;
884
885 if (misc_reg == MISCREG_CPSR) {
886 updateRegMap(val);
887
888
889 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
890 int old_mode = old_cpsr.mode;
891 CPSR cpsr = val;
892 if (old_mode != cpsr.mode) {
893 getITBPtr(tc)->invalidateMiscReg();
894 getDTBPtr(tc)->invalidateMiscReg();
895 }
896
897 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
898 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
899 PCState pc = tc->pcState();
900 pc.nextThumb(cpsr.t);
901 pc.nextJazelle(cpsr.j);
902
903 // Follow slightly different semantics if a CheckerCPU object
904 // is connected
905 CheckerCPU *checker = tc->getCheckerCpuPtr();
906 if (checker) {
907 tc->pcStateNoRecord(pc);
908 } else {
909 tc->pcState(pc);
910 }
911 } else {
912#ifndef NDEBUG
913 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
914 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
915 warn("Unimplemented system register %s write with %#x.\n",
916 miscRegName[misc_reg], val);
917 else
918 panic("Unimplemented system register %s write with %#x.\n",
919 miscRegName[misc_reg], val);
920 }
921#endif
922 switch (unflattenMiscReg(misc_reg)) {
923 case MISCREG_CPACR:
924 {
925
926 const uint32_t ones = (uint32_t)(-1);
927 CPACR cpacrMask = 0;
928 // Only cp10, cp11, and ase are implemented, nothing else should
929 // be writable
930 cpacrMask.cp10 = ones;
931 cpacrMask.cp11 = ones;
932 cpacrMask.asedis = ones;
933
934 // Security Extensions may limit the writability of CPACR
935 if (haveSecurity) {
936 scr = readMiscRegNoEffect(MISCREG_SCR);
937 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
938 if (scr.ns && (cpsr.mode != MODE_MON)) {
939 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
940 // NB: Skipping the full loop, here
941 if (!nsacr.cp10) cpacrMask.cp10 = 0;
942 if (!nsacr.cp11) cpacrMask.cp11 = 0;
943 }
944 }
945
946 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
947 newVal &= cpacrMask;
948 newVal |= old_val & ~cpacrMask;
949 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
950 miscRegName[misc_reg], newVal);
951 }
952 break;
953 case MISCREG_CPACR_EL1:
954 {
955 const uint32_t ones = (uint32_t)(-1);
956 CPACR cpacrMask = 0;
957 cpacrMask.tta = ones;
958 cpacrMask.fpen = ones;
959 newVal &= cpacrMask;
960 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
961 miscRegName[misc_reg], newVal);
962 }
963 break;
964 case MISCREG_CPTR_EL2:
965 {
966 const uint32_t ones = (uint32_t)(-1);
967 CPTR cptrMask = 0;
968 cptrMask.tcpac = ones;
969 cptrMask.tta = ones;
970 cptrMask.tfp = ones;
971 newVal &= cptrMask;
972 cptrMask = 0;
973 cptrMask.res1_13_12_el2 = ones;
974 cptrMask.res1_9_0_el2 = ones;
975 newVal |= cptrMask;
976 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
977 miscRegName[misc_reg], newVal);
978 }
979 break;
980 case MISCREG_CPTR_EL3:
981 {
982 const uint32_t ones = (uint32_t)(-1);
983 CPTR cptrMask = 0;
984 cptrMask.tcpac = ones;
985 cptrMask.tta = ones;
986 cptrMask.tfp = ones;
987 newVal &= cptrMask;
988 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
989 miscRegName[misc_reg], newVal);
990 }
991 break;
992 case MISCREG_CSSELR:
993 warn_once("The csselr register isn't implemented.\n");
994 return;
995
996 case MISCREG_DC_ZVA_Xt:
997 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
998 return;
999
1000 case MISCREG_FPSCR:
1001 {
1002 const uint32_t ones = (uint32_t)(-1);
1003 FPSCR fpscrMask = 0;
1004 fpscrMask.ioc = ones;
1005 fpscrMask.dzc = ones;
1006 fpscrMask.ofc = ones;
1007 fpscrMask.ufc = ones;
1008 fpscrMask.ixc = ones;
1009 fpscrMask.idc = ones;
1010 fpscrMask.ioe = ones;
1011 fpscrMask.dze = ones;
1012 fpscrMask.ofe = ones;
1013 fpscrMask.ufe = ones;
1014 fpscrMask.ixe = ones;
1015 fpscrMask.ide = ones;
1016 fpscrMask.len = ones;
1017 fpscrMask.stride = ones;
1018 fpscrMask.rMode = ones;
1019 fpscrMask.fz = ones;
1020 fpscrMask.dn = ones;
1021 fpscrMask.ahp = ones;
1022 fpscrMask.qc = ones;
1023 fpscrMask.v = ones;
1024 fpscrMask.c = ones;
1025 fpscrMask.z = ones;
1026 fpscrMask.n = ones;
1027 newVal = (newVal & (uint32_t)fpscrMask) |
1028 (readMiscRegNoEffect(MISCREG_FPSCR) &
1029 ~(uint32_t)fpscrMask);
1030 tc->getDecoderPtr()->setContext(newVal);
1031 }
1032 break;
1033 case MISCREG_FPSR:
1034 {
1035 const uint32_t ones = (uint32_t)(-1);
1036 FPSCR fpscrMask = 0;
1037 fpscrMask.ioc = ones;
1038 fpscrMask.dzc = ones;
1039 fpscrMask.ofc = ones;
1040 fpscrMask.ufc = ones;
1041 fpscrMask.ixc = ones;
1042 fpscrMask.idc = ones;
1043 fpscrMask.qc = ones;
1044 fpscrMask.v = ones;
1045 fpscrMask.c = ones;
1046 fpscrMask.z = ones;
1047 fpscrMask.n = ones;
1048 newVal = (newVal & (uint32_t)fpscrMask) |
1049 (readMiscRegNoEffect(MISCREG_FPSCR) &
1050 ~(uint32_t)fpscrMask);
1051 misc_reg = MISCREG_FPSCR;
1052 }
1053 break;
1054 case MISCREG_FPCR:
1055 {
1056 const uint32_t ones = (uint32_t)(-1);
1057 FPSCR fpscrMask = 0;
1058 fpscrMask.ioe = ones;
1059 fpscrMask.dze = ones;
1060 fpscrMask.ofe = ones;
1061 fpscrMask.ufe = ones;
1062 fpscrMask.ixe = ones;
1063 fpscrMask.ide = ones;
1064 fpscrMask.len = ones;
1065 fpscrMask.stride = ones;
1066 fpscrMask.rMode = ones;
1067 fpscrMask.fz = ones;
1068 fpscrMask.dn = ones;
1069 fpscrMask.ahp = ones;
1070 newVal = (newVal & (uint32_t)fpscrMask) |
1071 (readMiscRegNoEffect(MISCREG_FPSCR) &
1072 ~(uint32_t)fpscrMask);
1073 misc_reg = MISCREG_FPSCR;
1074 }
1075 break;
1076 case MISCREG_CPSR_Q:
1077 {
1078 assert(!(newVal & ~CpsrMaskQ));
1079 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1080 misc_reg = MISCREG_CPSR;
1081 }
1082 break;
1083 case MISCREG_FPSCR_QC:
1084 {
1085 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1086 (newVal & FpscrQcMask);
1087 misc_reg = MISCREG_FPSCR;
1088 }
1089 break;
1090 case MISCREG_FPSCR_EXC:
1091 {
1092 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1093 (newVal & FpscrExcMask);
1094 misc_reg = MISCREG_FPSCR;
1095 }
1096 break;
1097 case MISCREG_FPEXC:
1098 {
1099 // vfpv3 architecture, section B.6.1 of DDI04068
1100 // bit 29 - valid only if fpexc[31] is 0
1101 const uint32_t fpexcMask = 0x60000000;
1102 newVal = (newVal & fpexcMask) |
1103 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1104 }
1105 break;
1106 case MISCREG_HCR:
1107 {
1108 if (!haveVirtualization)
1109 return;
1110 }
1111 break;
1112 case MISCREG_IFSR:
1113 {
1114 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1115 const uint32_t ifsrMask =
1116 mask(31, 13) | mask(11, 11) | mask(8, 6);
1117 newVal = newVal & ~ifsrMask;
1118 }
1119 break;
1120 case MISCREG_DFSR:
1121 {
1122 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1123 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1124 newVal = newVal & ~dfsrMask;
1125 }
1126 break;
1127 case MISCREG_AMAIR0:
1128 case MISCREG_AMAIR1:
1129 {
1130 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1131 // Valid only with LPAE
1132 if (!haveLPAE)
1133 return;
1134 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1135 }
1136 break;
1137 case MISCREG_SCR:
1138 getITBPtr(tc)->invalidateMiscReg();
1139 getDTBPtr(tc)->invalidateMiscReg();
1140 break;
1141 case MISCREG_SCTLR:
1142 {
1143 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1144 scr = readMiscRegNoEffect(MISCREG_SCR);
1145 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1146 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1147 SCTLR sctlr = miscRegs[sctlr_idx];
1148 SCTLR new_sctlr = newVal;
1149 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1150 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1151 getITBPtr(tc)->invalidateMiscReg();
1152 getDTBPtr(tc)->invalidateMiscReg();
1153 }
1154 case MISCREG_MIDR:
1155 case MISCREG_ID_PFR0:
1156 case MISCREG_ID_PFR1:
1157 case MISCREG_ID_DFR0:
1158 case MISCREG_ID_MMFR0:
1159 case MISCREG_ID_MMFR1:
1160 case MISCREG_ID_MMFR2:
1161 case MISCREG_ID_MMFR3:
1162 case MISCREG_ID_ISAR0:
1163 case MISCREG_ID_ISAR1:
1164 case MISCREG_ID_ISAR2:
1165 case MISCREG_ID_ISAR3:
1166 case MISCREG_ID_ISAR4:
1167 case MISCREG_ID_ISAR5:
1168
1169 case MISCREG_MPIDR:
1170 case MISCREG_FPSID:
1171 case MISCREG_TLBTR:
1172 case MISCREG_MVFR0:
1173 case MISCREG_MVFR1:
1174
1175 case MISCREG_ID_AA64AFR0_EL1:
1176 case MISCREG_ID_AA64AFR1_EL1:
1177 case MISCREG_ID_AA64DFR0_EL1:
1178 case MISCREG_ID_AA64DFR1_EL1:
1179 case MISCREG_ID_AA64ISAR0_EL1:
1180 case MISCREG_ID_AA64ISAR1_EL1:
1181 case MISCREG_ID_AA64MMFR0_EL1:
1182 case MISCREG_ID_AA64MMFR1_EL1:
1183 case MISCREG_ID_AA64PFR0_EL1:
1184 case MISCREG_ID_AA64PFR1_EL1:
1185 // ID registers are constants.
1186 return;
1187
1188 // TLBI all entries, EL0&1 inner sharable (ignored)
1189 case MISCREG_TLBIALLIS:
1190 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1191 assert32(tc);
1192 target_el = 1; // el 0 and 1 are handled together
1193 scr = readMiscReg(MISCREG_SCR, tc);
1194 secure_lookup = haveSecurity && !scr.ns;
1195 sys = tc->getSystemPtr();
1196 for (x = 0; x < sys->numContexts(); x++) {
1197 oc = sys->getThreadContext(x);
1198 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1199 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1200
1201 // If CheckerCPU is connected, need to notify it of a flush
1202 CheckerCPU *checker = oc->getCheckerCpuPtr();
1203 if (checker) {
1204 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1205 target_el);
1206 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1207 target_el);
1208 }
1209 }
1210 return;
1211 // TLBI all entries, EL0&1, instruction side
1212 case MISCREG_ITLBIALL:
1213 assert32(tc);
1214 target_el = 1; // el 0 and 1 are handled together
1215 scr = readMiscReg(MISCREG_SCR, tc);
1216 secure_lookup = haveSecurity && !scr.ns;
1217 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1218 return;
1219 // TLBI all entries, EL0&1, data side
1220 case MISCREG_DTLBIALL:
1221 assert32(tc);
1222 target_el = 1; // el 0 and 1 are handled together
1223 scr = readMiscReg(MISCREG_SCR, tc);
1224 secure_lookup = haveSecurity && !scr.ns;
1225 getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1226 return;
1227 // TLBI based on VA, EL0&1 inner sharable (ignored)
1228 case MISCREG_TLBIMVAIS:
1229 case MISCREG_TLBIMVA:
1230 assert32(tc);
1231 target_el = 1; // el 0 and 1 are handled together
1232 scr = readMiscReg(MISCREG_SCR, tc);
1233 secure_lookup = haveSecurity && !scr.ns;
1234 sys = tc->getSystemPtr();
1235 for (x = 0; x < sys->numContexts(); x++) {
1236 oc = sys->getThreadContext(x);
1237 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1238 bits(newVal, 7,0),
1239 secure_lookup, target_el);
1240 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1241 bits(newVal, 7,0),
1242 secure_lookup, target_el);
1243
1244 CheckerCPU *checker = oc->getCheckerCpuPtr();
1245 if (checker) {
1246 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1247 bits(newVal, 7,0), secure_lookup, target_el);
1248 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1249 bits(newVal, 7,0), secure_lookup, target_el);
1250 }
1251 }
1252 return;
1253 // TLBI by ASID, EL0&1, inner sharable
1254 case MISCREG_TLBIASIDIS:
1255 case MISCREG_TLBIASID:
1256 assert32(tc);
1257 target_el = 1; // el 0 and 1 are handled together
1258 scr = readMiscReg(MISCREG_SCR, tc);
1259 secure_lookup = haveSecurity && !scr.ns;
1260 sys = tc->getSystemPtr();
1261 for (x = 0; x < sys->numContexts(); x++) {
1262 oc = sys->getThreadContext(x);
1263 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1264 secure_lookup, target_el);
1265 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1266 secure_lookup, target_el);
1267 CheckerCPU *checker = oc->getCheckerCpuPtr();
1268 if (checker) {
1269 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1270 secure_lookup, target_el);
1271 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1272 secure_lookup, target_el);
1273 }
1274 }
1275 return;
1276 // TLBI by address, EL0&1, inner sharable (ignored)
1277 case MISCREG_TLBIMVAAIS:
1278 case MISCREG_TLBIMVAA:
1279 assert32(tc);
1280 target_el = 1; // el 0 and 1 are handled together
1281 scr = readMiscReg(MISCREG_SCR, tc);
1282 secure_lookup = haveSecurity && !scr.ns;
1283 hyp = 0;
1284 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1285 return;
1286 // TLBI by address, EL2, hypervisor mode
1287 case MISCREG_TLBIMVAH:
1288 case MISCREG_TLBIMVAHIS:
1289 assert32(tc);
1290 target_el = 1; // aarch32, use hyp bit
1291 scr = readMiscReg(MISCREG_SCR, tc);
1292 secure_lookup = haveSecurity && !scr.ns;
1293 hyp = 1;
1294 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1295 return;
1296 // TLBI by address and asid, EL0&1, instruction side only
1297 case MISCREG_ITLBIMVA:
1298 assert32(tc);
1299 target_el = 1; // el 0 and 1 are handled together
1300 scr = readMiscReg(MISCREG_SCR, tc);
1301 secure_lookup = haveSecurity && !scr.ns;
1302 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1303 bits(newVal, 7,0), secure_lookup, target_el);
1304 return;
1305 // TLBI by address and asid, EL0&1, data side only
1306 case MISCREG_DTLBIMVA:
1307 assert32(tc);
1308 target_el = 1; // el 0 and 1 are handled together
1309 scr = readMiscReg(MISCREG_SCR, tc);
1310 secure_lookup = haveSecurity && !scr.ns;
1311 getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1312 bits(newVal, 7,0), secure_lookup, target_el);
1313 return;
1314 // TLBI by ASID, EL0&1, instrution side only
1315 case MISCREG_ITLBIASID:
1316 assert32(tc);
1317 target_el = 1; // el 0 and 1 are handled together
1318 scr = readMiscReg(MISCREG_SCR, tc);
1319 secure_lookup = haveSecurity && !scr.ns;
1320 getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1321 target_el);
1322 return;
1323 // TLBI by ASID EL0&1 data size only
1324 case MISCREG_DTLBIASID:
1325 assert32(tc);
1326 target_el = 1; // el 0 and 1 are handled together
1327 scr = readMiscReg(MISCREG_SCR, tc);
1328 secure_lookup = haveSecurity && !scr.ns;
1329 getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1330 target_el);
1331 return;
1332 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1333 case MISCREG_TLBIALLNSNH:
1334 case MISCREG_TLBIALLNSNHIS:
1335 assert32(tc);
1336 target_el = 1; // el 0 and 1 are handled together
1337 hyp = 0;
1338 tlbiALLN(tc, hyp, target_el);
1339 return;
1340 // TLBI all entries, EL2, hyp,
1341 case MISCREG_TLBIALLH:
1342 case MISCREG_TLBIALLHIS:
1343 assert32(tc);
1344 target_el = 1; // aarch32, use hyp bit
1345 hyp = 1;
1346 tlbiALLN(tc, hyp, target_el);
1347 return;
1348 // AArch64 TLBI: invalidate all entries EL3
1349 case MISCREG_TLBI_ALLE3IS:
1350 case MISCREG_TLBI_ALLE3:
1351 assert64(tc);
1352 target_el = 3;
1353 secure_lookup = true;
1354 tlbiALL(tc, secure_lookup, target_el);
1355 return;
1356 // @todo: uncomment this to enable Virtualization
1357 // case MISCREG_TLBI_ALLE2IS:
1358 // case MISCREG_TLBI_ALLE2:
1359 // TLBI all entries, EL0&1
1360 case MISCREG_TLBI_ALLE1IS:
1361 case MISCREG_TLBI_ALLE1:
1362 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1363 case MISCREG_TLBI_VMALLE1IS:
1364 case MISCREG_TLBI_VMALLE1:
1365 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1366 case MISCREG_TLBI_VMALLS12E1IS:
1367 case MISCREG_TLBI_VMALLS12E1:
1368 // @todo: handle VMID and stage 2 to enable Virtualization
1369 assert64(tc);
1370 target_el = 1; // el 0 and 1 are handled together
1371 scr = readMiscReg(MISCREG_SCR, tc);
1372 secure_lookup = haveSecurity && !scr.ns;
1373 tlbiALL(tc, secure_lookup, target_el);
1374 return;
1375 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1376 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1377 // from the last level of translation table walks
1378 // @todo: handle VMID to enable Virtualization
1379 // TLBI all entries, EL0&1
1380 case MISCREG_TLBI_VAE3IS_Xt:
1381 case MISCREG_TLBI_VAE3_Xt:
1382 // TLBI by VA, EL3 regime stage 1, last level walk
1383 case MISCREG_TLBI_VALE3IS_Xt:
1384 case MISCREG_TLBI_VALE3_Xt:
1385 assert64(tc);
1386 target_el = 3;
1387 asid = 0xbeef; // does not matter, tlbi is global
1388 secure_lookup = true;
1389 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1390 return;
1391 // TLBI by VA, EL2
1392 case MISCREG_TLBI_VAE2IS_Xt:
1393 case MISCREG_TLBI_VAE2_Xt:
1394 // TLBI by VA, EL2, stage1 last level walk
1395 case MISCREG_TLBI_VALE2IS_Xt:
1396 case MISCREG_TLBI_VALE2_Xt:
1397 assert64(tc);
1398 target_el = 2;
1399 asid = 0xbeef; // does not matter, tlbi is global
1400 scr = readMiscReg(MISCREG_SCR, tc);
1401 secure_lookup = haveSecurity && !scr.ns;
1402 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1403 return;
1404 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1405 case MISCREG_TLBI_VAE1IS_Xt:
1406 case MISCREG_TLBI_VAE1_Xt:
1407 case MISCREG_TLBI_VALE1IS_Xt:
1408 case MISCREG_TLBI_VALE1_Xt:
1409 assert64(tc);
1410 asid = bits(newVal, 63, 48);
1411 target_el = 1; // el 0 and 1 are handled together
1412 scr = readMiscReg(MISCREG_SCR, tc);
1413 secure_lookup = haveSecurity && !scr.ns;
1414 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1415 return;
1416 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1417 // @todo: handle VMID to enable Virtualization
1418 case MISCREG_TLBI_ASIDE1IS_Xt:
1419 case MISCREG_TLBI_ASIDE1_Xt:
1420 assert64(tc);
1421 target_el = 1; // el 0 and 1 are handled together
1422 scr = readMiscReg(MISCREG_SCR, tc);
1423 secure_lookup = haveSecurity && !scr.ns;
1424 sys = tc->getSystemPtr();
1425 for (x = 0; x < sys->numContexts(); x++) {
1426 oc = sys->getThreadContext(x);
1427 asid = bits(newVal, 63, 48);
1428 if (!haveLargeAsid64)
1429 asid &= mask(8);
1430 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1431 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1432 CheckerCPU *checker = oc->getCheckerCpuPtr();
1433 if (checker) {
1434 getITBPtr(checker)->flushAsid(asid,
1435 secure_lookup, target_el);
1436 getDTBPtr(checker)->flushAsid(asid,
1437 secure_lookup, target_el);
1438 }
1439 }
1440 return;
1441 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1442 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1443 // entries from the last level of translation table walks
1444 // @todo: handle VMID to enable Virtualization
1445 case MISCREG_TLBI_VAAE1IS_Xt:
1446 case MISCREG_TLBI_VAAE1_Xt:
1447 case MISCREG_TLBI_VAALE1IS_Xt:
1448 case MISCREG_TLBI_VAALE1_Xt:
1449 assert64(tc);
1450 target_el = 1; // el 0 and 1 are handled together
1451 scr = readMiscReg(MISCREG_SCR, tc);
1452 secure_lookup = haveSecurity && !scr.ns;
1453 sys = tc->getSystemPtr();
1454 for (x = 0; x < sys->numContexts(); x++) {
1455 // @todo: extra controls on TLBI broadcast?
1456 oc = sys->getThreadContext(x);
1457 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1458 getITBPtr(oc)->flushMva(va,
1459 secure_lookup, false, target_el);
1460 getDTBPtr(oc)->flushMva(va,
1461 secure_lookup, false, target_el);
1462
1463 CheckerCPU *checker = oc->getCheckerCpuPtr();
1464 if (checker) {
1465 getITBPtr(checker)->flushMva(va,
1466 secure_lookup, false, target_el);
1467 getDTBPtr(checker)->flushMva(va,
1468 secure_lookup, false, target_el);
1469 }
1470 }
1471 return;
1472 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1473 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1474 case MISCREG_TLBI_IPAS2LE1_Xt:
1475 case MISCREG_TLBI_IPAS2E1IS_Xt:
1476 case MISCREG_TLBI_IPAS2E1_Xt:
1477 assert64(tc);
1478 target_el = 1; // EL 0 and 1 are handled together
1479 scr = readMiscReg(MISCREG_SCR, tc);
1480 secure_lookup = haveSecurity && !scr.ns;
1481 sys = tc->getSystemPtr();
1482 for (x = 0; x < sys->numContexts(); x++) {
1483 oc = sys->getThreadContext(x);
1484 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1485 getITBPtr(oc)->flushIpaVmid(ipa,
1486 secure_lookup, false, target_el);
1487 getDTBPtr(oc)->flushIpaVmid(ipa,
1488 secure_lookup, false, target_el);
1489
1490 CheckerCPU *checker = oc->getCheckerCpuPtr();
1491 if (checker) {
1492 getITBPtr(checker)->flushIpaVmid(ipa,
1493 secure_lookup, false, target_el);
1494 getDTBPtr(checker)->flushIpaVmid(ipa,
1495 secure_lookup, false, target_el);
1496 }
1497 }
1498 return;
1499 case MISCREG_ACTLR:
1500 warn("Not doing anything for write of miscreg ACTLR\n");
1501 break;
1502
1503 case MISCREG_PMXEVTYPER_PMCCFILTR:
1504 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1505 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1506 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1507 pmu->setMiscReg(misc_reg, newVal);
1508 break;
1509
1510
1511 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1512 {
1513 HSTR hstrMask = 0;
1514 hstrMask.tjdbx = 1;
1515 newVal &= ~((uint32_t) hstrMask);
1516 break;
1517 }
1518 case MISCREG_HCPTR:
1519 {
1520 // If a CP bit in NSACR is 0 then the corresponding bit in
1521 // HCPTR is RAO/WI. Same applies to NSASEDIS
1522 secure_lookup = haveSecurity &&
1523 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1524 readMiscRegNoEffect(MISCREG_CPSR));
1525 if (!secure_lookup) {
1526 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1527 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1528 newVal = (newVal & ~mask) | (oldValue & mask);
1529 }
1530 break;
1531 }
1532 case MISCREG_HDFAR: // alias for secure DFAR
1533 misc_reg = MISCREG_DFAR_S;
1534 break;
1535 case MISCREG_HIFAR: // alias for secure IFAR
1536 misc_reg = MISCREG_IFAR_S;
1537 break;
1538 case MISCREG_ATS1CPR:
1539 case MISCREG_ATS1CPW:
1540 case MISCREG_ATS1CUR:
1541 case MISCREG_ATS1CUW:
1542 case MISCREG_ATS12NSOPR:
1543 case MISCREG_ATS12NSOPW:
1544 case MISCREG_ATS12NSOUR:
1545 case MISCREG_ATS12NSOUW:
1546 case MISCREG_ATS1HR:
1547 case MISCREG_ATS1HW:
1548 {
1549 Request::Flags flags = 0;
1550 BaseTLB::Mode mode = BaseTLB::Read;
1551 TLB::ArmTranslationType tranType = TLB::NormalTran;
1552 Fault fault;
1553 switch(misc_reg) {
1554 case MISCREG_ATS1CPR:
1555 flags = TLB::MustBeOne;
1556 tranType = TLB::S1CTran;
1557 mode = BaseTLB::Read;
1558 break;
1559 case MISCREG_ATS1CPW:
1560 flags = TLB::MustBeOne;
1561 tranType = TLB::S1CTran;
1562 mode = BaseTLB::Write;
1563 break;
1564 case MISCREG_ATS1CUR:
1565 flags = TLB::MustBeOne | TLB::UserMode;
1566 tranType = TLB::S1CTran;
1567 mode = BaseTLB::Read;
1568 break;
1569 case MISCREG_ATS1CUW:
1570 flags = TLB::MustBeOne | TLB::UserMode;
1571 tranType = TLB::S1CTran;
1572 mode = BaseTLB::Write;
1573 break;
1574 case MISCREG_ATS12NSOPR:
1575 if (!haveSecurity)
1576 panic("Security Extensions required for ATS12NSOPR");
1577 flags = TLB::MustBeOne;
1578 tranType = TLB::S1S2NsTran;
1579 mode = BaseTLB::Read;
1580 break;
1581 case MISCREG_ATS12NSOPW:
1582 if (!haveSecurity)
1583 panic("Security Extensions required for ATS12NSOPW");
1584 flags = TLB::MustBeOne;
1585 tranType = TLB::S1S2NsTran;
1586 mode = BaseTLB::Write;
1587 break;
1588 case MISCREG_ATS12NSOUR:
1589 if (!haveSecurity)
1590 panic("Security Extensions required for ATS12NSOUR");
1591 flags = TLB::MustBeOne | TLB::UserMode;
1592 tranType = TLB::S1S2NsTran;
1593 mode = BaseTLB::Read;
1594 break;
1595 case MISCREG_ATS12NSOUW:
1596 if (!haveSecurity)
1597 panic("Security Extensions required for ATS12NSOUW");
1598 flags = TLB::MustBeOne | TLB::UserMode;
1599 tranType = TLB::S1S2NsTran;
1600 mode = BaseTLB::Write;
1601 break;
1602 case MISCREG_ATS1HR: // only really useful from secure mode.
1603 flags = TLB::MustBeOne;
1604 tranType = TLB::HypMode;
1605 mode = BaseTLB::Read;
1606 break;
1607 case MISCREG_ATS1HW:
1608 flags = TLB::MustBeOne;
1609 tranType = TLB::HypMode;
1610 mode = BaseTLB::Write;
1611 break;
1612 }
1613 // If we're in timing mode then doing the translation in
1614 // functional mode then we're slightly distorting performance
1615 // results obtained from simulations. The translation should be
1616 // done in the same mode the core is running in. NOTE: This
1617 // can't be an atomic translation because that causes problems
1618 // with unexpected atomic snoop requests.
1619 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1620 Request req(0, val, 0, flags, Request::funcMasterId,
1621 tc->pcState().pc(), tc->contextId());
1622 fault = getDTBPtr(tc)->translateFunctional(
1623 &req, tc, mode, tranType);
1624 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1625 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1626
1627 MiscReg newVal;
1628 if (fault == NoFault) {
1629 Addr paddr = req.getPaddr();
1630 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1631 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1632 newVal = (paddr & mask(39, 12)) |
1633 (getDTBPtr(tc)->getAttr());
1634 } else {
1635 newVal = (paddr & 0xfffff000) |
1636 (getDTBPtr(tc)->getAttr());
1637 }
1638 DPRINTF(MiscRegs,
1639 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1640 val, newVal);
1641 } else {
1642 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1643 // Set fault bit and FSR
1644 FSR fsr = armFault->getFsr(tc);
1645
1646 newVal = ((fsr >> 9) & 1) << 11;
1647 if (newVal) {
1648 // LPAE - rearange fault status
1649 newVal |= ((fsr >> 0) & 0x3f) << 1;
1650 } else {
1651 // VMSA - rearange fault status
1652 newVal |= ((fsr >> 0) & 0xf) << 1;
1653 newVal |= ((fsr >> 10) & 0x1) << 5;
1654 newVal |= ((fsr >> 12) & 0x1) << 6;
1655 }
1656 newVal |= 0x1; // F bit
1657 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1658 newVal |= armFault->isStage2() ? 0x200 : 0;
1659 DPRINTF(MiscRegs,
1660 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1661 val, fsr, newVal);
1662 }
1663 setMiscRegNoEffect(MISCREG_PAR, newVal);
1664 return;
1665 }
1666 case MISCREG_TTBCR:
1667 {
1668 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1669 const uint32_t ones = (uint32_t)(-1);
1670 TTBCR ttbcrMask = 0;
1671 TTBCR ttbcrNew = newVal;
1672
1673 // ARM DDI 0406C.b, ARMv7-32
1674 ttbcrMask.n = ones; // T0SZ
1675 if (haveSecurity) {
1676 ttbcrMask.pd0 = ones;
1677 ttbcrMask.pd1 = ones;
1678 }
1679 ttbcrMask.epd0 = ones;
1680 ttbcrMask.irgn0 = ones;
1681 ttbcrMask.orgn0 = ones;
1682 ttbcrMask.sh0 = ones;
1683 ttbcrMask.ps = ones; // T1SZ
1684 ttbcrMask.a1 = ones;
1685 ttbcrMask.epd1 = ones;
1686 ttbcrMask.irgn1 = ones;
1687 ttbcrMask.orgn1 = ones;
1688 ttbcrMask.sh1 = ones;
1689 if (haveLPAE)
1690 ttbcrMask.eae = ones;
1691
1692 if (haveLPAE && ttbcrNew.eae) {
1693 newVal = newVal & ttbcrMask;
1694 } else {
1695 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1696 }
1697 }
1698 M5_FALLTHROUGH;
1699 case MISCREG_TTBR0:
1700 case MISCREG_TTBR1:
1701 {
1702 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1703 if (haveLPAE) {
1704 if (ttbcr.eae) {
1705 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1706 // ARMv8 AArch32 bit 63-56 only
1707 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1708 newVal = (newVal & (~ttbrMask));
1709 }
1710 }
1711 }
1712 M5_FALLTHROUGH;
1713 case MISCREG_SCTLR_EL1:
1714 {
1715 getITBPtr(tc)->invalidateMiscReg();
1716 getDTBPtr(tc)->invalidateMiscReg();
1717 setMiscRegNoEffect(misc_reg, newVal);
1718 }
1719 M5_FALLTHROUGH;
1720 case MISCREG_CONTEXTIDR:
1721 case MISCREG_PRRR:
1722 case MISCREG_NMRR:
1723 case MISCREG_MAIR0:
1724 case MISCREG_MAIR1:
1725 case MISCREG_DACR:
1726 case MISCREG_VTTBR:
1727 case MISCREG_SCR_EL3:
1728 case MISCREG_HCR_EL2:
1729 case MISCREG_TCR_EL1:
1730 case MISCREG_TCR_EL2:
1731 case MISCREG_TCR_EL3:
1732 case MISCREG_SCTLR_EL2:
1733 case MISCREG_SCTLR_EL3:
1734 case MISCREG_HSCTLR:
1735 case MISCREG_TTBR0_EL1:
1736 case MISCREG_TTBR1_EL1:
1737 case MISCREG_TTBR0_EL2:
1738 case MISCREG_TTBR0_EL3:
1739 getITBPtr(tc)->invalidateMiscReg();
1740 getDTBPtr(tc)->invalidateMiscReg();
1741 break;
1742 case MISCREG_NZCV:
1743 {
1744 CPSR cpsr = val;
1745
1746 tc->setCCReg(CCREG_NZ, cpsr.nz);
1747 tc->setCCReg(CCREG_C, cpsr.c);
1748 tc->setCCReg(CCREG_V, cpsr.v);
1749 }
1750 break;
1751 case MISCREG_DAIF:
1752 {
1753 CPSR cpsr = miscRegs[MISCREG_CPSR];
1754 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1755 newVal = cpsr;
1756 misc_reg = MISCREG_CPSR;
1757 }
1758 break;
1759 case MISCREG_SP_EL0:
1760 tc->setIntReg(INTREG_SP0, newVal);
1761 break;
1762 case MISCREG_SP_EL1:
1763 tc->setIntReg(INTREG_SP1, newVal);
1764 break;
1765 case MISCREG_SP_EL2:
1766 tc->setIntReg(INTREG_SP2, newVal);
1767 break;
1768 case MISCREG_SPSEL:
1769 {
1770 CPSR cpsr = miscRegs[MISCREG_CPSR];
1771 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1772 newVal = cpsr;
1773 misc_reg = MISCREG_CPSR;
1774 }
1775 break;
1776 case MISCREG_CURRENTEL:
1777 {
1778 CPSR cpsr = miscRegs[MISCREG_CPSR];
1779 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1780 newVal = cpsr;
1781 misc_reg = MISCREG_CPSR;
1782 }
1783 break;
1784 case MISCREG_AT_S1E1R_Xt:
1785 case MISCREG_AT_S1E1W_Xt:
1786 case MISCREG_AT_S1E0R_Xt:
1787 case MISCREG_AT_S1E0W_Xt:
1788 case MISCREG_AT_S1E2R_Xt:
1789 case MISCREG_AT_S1E2W_Xt:
1790 case MISCREG_AT_S12E1R_Xt:
1791 case MISCREG_AT_S12E1W_Xt:
1792 case MISCREG_AT_S12E0R_Xt:
1793 case MISCREG_AT_S12E0W_Xt:
1794 case MISCREG_AT_S1E3R_Xt:
1795 case MISCREG_AT_S1E3W_Xt:
1796 {
1797 RequestPtr req = new Request;
1798 Request::Flags flags = 0;
1799 BaseTLB::Mode mode = BaseTLB::Read;
1800 TLB::ArmTranslationType tranType = TLB::NormalTran;
1801 Fault fault;
1802 switch(misc_reg) {
1803 case MISCREG_AT_S1E1R_Xt:
1804 flags = TLB::MustBeOne;
1805 tranType = TLB::S1E1Tran;
1806 mode = BaseTLB::Read;
1807 break;
1808 case MISCREG_AT_S1E1W_Xt:
1809 flags = TLB::MustBeOne;
1810 tranType = TLB::S1E1Tran;
1811 mode = BaseTLB::Write;
1812 break;
1813 case MISCREG_AT_S1E0R_Xt:
1814 flags = TLB::MustBeOne | TLB::UserMode;
1815 tranType = TLB::S1E0Tran;
1816 mode = BaseTLB::Read;
1817 break;
1818 case MISCREG_AT_S1E0W_Xt:
1819 flags = TLB::MustBeOne | TLB::UserMode;
1820 tranType = TLB::S1E0Tran;
1821 mode = BaseTLB::Write;
1822 break;
1823 case MISCREG_AT_S1E2R_Xt:
1824 flags = TLB::MustBeOne;
1825 tranType = TLB::S1E2Tran;
1826 mode = BaseTLB::Read;
1827 break;
1828 case MISCREG_AT_S1E2W_Xt:
1829 flags = TLB::MustBeOne;
1830 tranType = TLB::S1E2Tran;
1831 mode = BaseTLB::Write;
1832 break;
1833 case MISCREG_AT_S12E0R_Xt:
1834 flags = TLB::MustBeOne | TLB::UserMode;
1835 tranType = TLB::S12E0Tran;
1836 mode = BaseTLB::Read;
1837 break;
1838 case MISCREG_AT_S12E0W_Xt:
1839 flags = TLB::MustBeOne | TLB::UserMode;
1840 tranType = TLB::S12E0Tran;
1841 mode = BaseTLB::Write;
1842 break;
1843 case MISCREG_AT_S12E1R_Xt:
1844 flags = TLB::MustBeOne;
1845 tranType = TLB::S12E1Tran;
1846 mode = BaseTLB::Read;
1847 break;
1848 case MISCREG_AT_S12E1W_Xt:
1849 flags = TLB::MustBeOne;
1850 tranType = TLB::S12E1Tran;
1851 mode = BaseTLB::Write;
1852 break;
1853 case MISCREG_AT_S1E3R_Xt:
1854 flags = TLB::MustBeOne;
1855 tranType = TLB::S1E3Tran;
1856 mode = BaseTLB::Read;
1857 break;
1858 case MISCREG_AT_S1E3W_Xt:
1859 flags = TLB::MustBeOne;
1860 tranType = TLB::S1E3Tran;
1861 mode = BaseTLB::Write;
1862 break;
1863 }
1864 // If we're in timing mode then doing the translation in
1865 // functional mode then we're slightly distorting performance
1866 // results obtained from simulations. The translation should be
1867 // done in the same mode the core is running in. NOTE: This
1868 // can't be an atomic translation because that causes problems
1869 // with unexpected atomic snoop requests.
1870 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1871 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1872 tc->pcState().pc());
1873 req->setContext(tc->contextId());
1874 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1875 tranType);
1876
1877 MiscReg newVal;
1878 if (fault == NoFault) {
1879 Addr paddr = req->getPaddr();
1880 uint64_t attr = getDTBPtr(tc)->getAttr();
1881 uint64_t attr1 = attr >> 56;
1882 if (!attr1 || attr1 ==0x44) {
1883 attr |= 0x100;
1884 attr &= ~ uint64_t(0x80);
1885 }
1886 newVal = (paddr & mask(47, 12)) | attr;
1887 DPRINTF(MiscRegs,
1888 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1889 val, newVal);
1890 } else {
1891 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1892 // Set fault bit and FSR
1893 FSR fsr = armFault->getFsr(tc);
1894
1895 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1896 if (cpsr.width) { // AArch32
1897 newVal = ((fsr >> 9) & 1) << 11;
1898 // rearrange fault status
1899 newVal |= ((fsr >> 0) & 0x3f) << 1;
1900 newVal |= 0x1; // F bit
1901 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1902 newVal |= armFault->isStage2() ? 0x200 : 0;
1903 } else { // AArch64
1904 newVal = 1; // F bit
1905 newVal |= fsr << 1; // FST
1906 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1907 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1908 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1909 newVal |= 1 << 11; // RES1
1910 }
1911 DPRINTF(MiscRegs,
1912 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1913 val, fsr, newVal);
1914 }
1915 delete req;
1916 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1917 return;
1918 }
1919 case MISCREG_SPSR_EL3:
1920 case MISCREG_SPSR_EL2:
1921 case MISCREG_SPSR_EL1:
1922 // Force bits 23:21 to 0
1923 newVal = val & ~(0x7 << 21);
1924 break;
1925 case MISCREG_L2CTLR:
1926 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1927 miscRegName[misc_reg], uint32_t(val));
1928 break;
1929
1930 // Generic Timer registers
1931 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1932 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1933 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1934 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1935 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1936 break;
1937 }
1938 }
1939 setMiscRegNoEffect(misc_reg, newVal);
1940}
1941
1942void
1943ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1944 bool secure_lookup, uint8_t target_el)
1945{
1946 if (!haveLargeAsid64)
1947 asid &= mask(8);
1948 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1949 System *sys = tc->getSystemPtr();
1950 for (int x = 0; x < sys->numContexts(); x++) {
1951 ThreadContext *oc = sys->getThreadContext(x);
1952 getITBPtr(oc)->flushMvaAsid(va, asid,
1953 secure_lookup, target_el);
1954 getDTBPtr(oc)->flushMvaAsid(va, asid,
1955 secure_lookup, target_el);
1956
1957 CheckerCPU *checker = oc->getCheckerCpuPtr();
1958 if (checker) {
1959 getITBPtr(checker)->flushMvaAsid(
1960 va, asid, secure_lookup, target_el);
1961 getDTBPtr(checker)->flushMvaAsid(
1962 va, asid, secure_lookup, target_el);
1963 }
1964 }
1965}
1966
1967void
1968ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1969{
1970 System *sys = tc->getSystemPtr();
1971 for (int x = 0; x < sys->numContexts(); x++) {
1972 ThreadContext *oc = sys->getThreadContext(x);
1973 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1974 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1975
1976 // If CheckerCPU is connected, need to notify it of a flush
1977 CheckerCPU *checker = oc->getCheckerCpuPtr();
1978 if (checker) {
1979 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1980 target_el);
1981 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1982 target_el);
1983 }
1984 }
1985}
1986
1987void
1988ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1989{
1990 System *sys = tc->getSystemPtr();
1991 for (int x = 0; x < sys->numContexts(); x++) {
1992 ThreadContext *oc = sys->getThreadContext(x);
1993 getITBPtr(oc)->flushAllNs(hyp, target_el);
1994 getDTBPtr(oc)->flushAllNs(hyp, target_el);
1995
1996 CheckerCPU *checker = oc->getCheckerCpuPtr();
1997 if (checker) {
1998 getITBPtr(checker)->flushAllNs(hyp, target_el);
1999 getDTBPtr(checker)->flushAllNs(hyp, target_el);
2000 }
2001 }
2002}
2003
2004void
2005ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
2006 uint8_t target_el)
2007{
2008 System *sys = tc->getSystemPtr();
2009 for (int x = 0; x < sys->numContexts(); x++) {
2010 ThreadContext *oc = sys->getThreadContext(x);
2011 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
2012 secure_lookup, hyp, target_el);
2013 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
2014 secure_lookup, hyp, target_el);
2015
2016 CheckerCPU *checker = oc->getCheckerCpuPtr();
2017 if (checker) {
2018 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
2019 secure_lookup, hyp, target_el);
2020 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
2021 secure_lookup, hyp, target_el);
2022 }
2023 }
2024}
2025
2026BaseISADevice &
2027ISA::getGenericTimer(ThreadContext *tc)
2028{
2029 // We only need to create an ISA interface the first time we try
2030 // to access the timer.
2031 if (timer)
2032 return *timer.get();
2033
2034 assert(system);
2035 GenericTimer *generic_timer(system->getGenericTimer());
2036 if (!generic_timer) {
2037 panic("Trying to get a generic timer from a system that hasn't "
2038 "been configured to use a generic timer.\n");
2039 }
2040
2041 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2042 return *timer.get();
2043}
2044
2045}
2046
2047ArmISA::ISA *
2048ArmISAParams::create()
2049{
2050 return new ArmISA::ISA(this);
2051}