1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 198 unchanged lines hidden (view full) ---

207 warn("The clidr register always reports 0 caches.\n");
208 break;
209 case MISCREG_CCSIDR:
210 warn("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
214 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
215 }
216 return readMiscRegNoEffect(misc_reg);
217}
218
219void
220ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
221{
222 assert(misc_reg < NumMiscRegs);

--- 166 unchanged lines hidden (view full) ---

389 bits(newVal, 7,0));
390 return;
391 case MISCREG_ITLBIASID:
392 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
393 return;
394 case MISCREG_DTLBIASID:
395 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
396 return;
397 case MISCREG_V2PCWPR:
398 case MISCREG_V2PCWPW:
399 case MISCREG_V2PCWUR:
400 case MISCREG_V2PCWUW:
401 case MISCREG_V2POWPR:
402 case MISCREG_V2POWPW:
403 case MISCREG_V2POWUR:
404 case MISCREG_V2POWUW:

--- 52 unchanged lines hidden ---