1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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112 mvfr1.advSimdInteger = 1;
113 mvfr1.advSimdSinglePrecision = 1;
114 mvfr1.advSimdHalfPrecision = 1;
115 mvfr1.vfpHalfPrecision = 1;
116 miscRegs[MISCREG_MVFR1] = mvfr1;
117
118 miscRegs[MISCREG_MPIDR] = 0;
119
120 //XXX We need to initialize the rest of the state.
121}
122
123MiscReg
124ISA::readMiscRegNoEffect(int misc_reg)
125{
126 assert(misc_reg < NumMiscRegs);
127 if (misc_reg == MISCREG_SPSR) {

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357 bits(newVal, 7,0));
358 return;
359 case MISCREG_ITLBIASID:
360 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
361 return;
362 case MISCREG_DTLBIASID:
363 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
364 return;
365 }
366 }
367 setMiscRegNoEffect(misc_reg, newVal);
368}
369
370}