1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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154 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
155 Addr npc = tc->readNextPC() & ~PcModeMask;
156 if (cpsr.j)
157 npc = npc | (ULL(1) << PcJBitShift);
158 if (cpsr.t)
159 npc = npc | (ULL(1) << PcTBitShift);
160
161 tc->setNextPC(npc);
162 }
163 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
164 misc_reg < MISCREG_CP15_END) {
165 panic("Unimplemented CP15 register %s wrote with %#x.\n",
166 miscRegName[misc_reg], val);
167 }
168 switch (misc_reg) {
169 case MISCREG_CPACR:
170 {
171 CPACR newCpacr = 0;
172 CPACR valCpacr = val;
173 newCpacr.cp10 = valCpacr.cp10;
174 newCpacr.cp11 = valCpacr.cp11;
175 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
176 panic("Disabling coprocessors isn't implemented.\n");
177 }
178 newVal = newCpacr;
179 }
180 break;
181 case MISCREG_CSSELR:
182 warn("The csselr register isn't implemented.\n");
183 break;
184 case MISCREG_FPSCR:
185 {
186 const uint32_t ones = (uint32_t)(-1);
187 FPSCR fpscrMask = 0;
188 fpscrMask.ioc = ones;
189 fpscrMask.dzc = ones;
190 fpscrMask.ofc = ones;
191 fpscrMask.ufc = ones;
192 fpscrMask.ixc = ones;
193 fpscrMask.idc = ones;
194 fpscrMask.len = ones;
195 fpscrMask.stride = ones;
196 fpscrMask.rMode = ones;
197 fpscrMask.fz = ones;
198 fpscrMask.dn = ones;
199 fpscrMask.ahp = ones;
200 fpscrMask.qc = ones;
201 fpscrMask.v = ones;
202 fpscrMask.c = ones;
203 fpscrMask.z = ones;
204 fpscrMask.n = ones;
205 newVal = (newVal & (uint32_t)fpscrMask) |
206 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
207 }
208 break;
209 case MISCREG_FPEXC:
210 {
211 const uint32_t fpexcMask = 0x60000000;
212 newVal = (newVal & fpexcMask) |
213 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
214 }
215 break;
216 case MISCREG_SCTLR:
217 {
218 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
219 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
220 SCTLR new_sctlr = newVal;
221 new_sctlr.nmfi = (bool)sctlr.nmfi;
222 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
223 return;
224 }
225 case MISCREG_TLBTR:
226 case MISCREG_MVFR0:
227 case MISCREG_MVFR1:
228 case MISCREG_MPIDR:
229 case MISCREG_FPSID:
230 return;
231 case MISCREG_TLBIALLIS:
232 case MISCREG_TLBIALL:
233 warn("Need to flush all TLBs in MP\n");
234 tc->getITBPtr()->flushAll();
235 tc->getDTBPtr()->flushAll();
236 return;
237 case MISCREG_ITLBIALL:
238 tc->getITBPtr()->flushAll();
239 return;
240 case MISCREG_DTLBIALL:
241 tc->getDTBPtr()->flushAll();
242 return;
243 case MISCREG_TLBIMVAIS:
244 case MISCREG_TLBIMVA:
245 warn("Need to flush all TLBs in MP\n");
246 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
247 bits(newVal, 7,0));
248 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
249 bits(newVal, 7,0));
250 return;
251 case MISCREG_TLBIASIDIS:
252 case MISCREG_TLBIASID:
253 warn("Need to flush all TLBs in MP\n");
254 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
255 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
256 return;
257 case MISCREG_TLBIMVAAIS:
258 case MISCREG_TLBIMVAA:
259 warn("Need to flush all TLBs in MP\n");
260 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
261 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
262 return;
263 case MISCREG_ITLBIMVA:
264 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
265 bits(newVal, 7,0));
266 return;
267 case MISCREG_DTLBIMVA:
268 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
269 bits(newVal, 7,0));
270 return;
271 case MISCREG_ITLBIASID:
272 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
273 return;
274 case MISCREG_DTLBIASID:
275 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
276 return;
277 }
278 setMiscRegNoEffect(misc_reg, newVal);
279}
280
281}