1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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86 highestELIs64 = system->highestELIs64();
87 haveSecurity = system->haveSecurity();
88 haveLPAE = system->haveLPAE();
89 haveCrypto = system->haveCrypto();
90 haveVirtualization = system->haveVirtualization();
91 haveLargeAsid64 = system->haveLargeAsid64();
92 physAddrRange = system->physAddrRange();
93 haveSVE = system->haveSVE();
94 sveVL = system->sveVL();
95 } else {
96 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
97 haveSecurity = haveLPAE = haveVirtualization = false;
98 haveCrypto = true;
99 haveLargeAsid64 = false;
100 physAddrRange = 32; // dummy value
101 haveSVE = true;
102 sveVL = p->sve_vl_se;
103 }
104
105 // Initial rename mode depends on highestEL
106 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
107 highestELIs64 ? Enums::Full : Enums::Elem;
108
109 initializeMiscRegMetadata();

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386 // Physical address size
387 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
388 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
389 encodePhysAddrRange64(physAddrRange));
390 // Crypto
391 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
392 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
393 haveCrypto ? 0x1112 : 0x0);
394}
395
396void
397ISA::startup(ThreadContext *tc)
398{
399 pmu->setThreadContext(tc);
400
401 if (system) {

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635 case MISCREG_SPSEL:
636 {
637 return miscRegs[MISCREG_CPSR] & 0x1;
638 }
639 case MISCREG_CURRENTEL:
640 {
641 return miscRegs[MISCREG_CPSR] & 0xc;
642 }
643 case MISCREG_L2CTLR:
644 {
645 // mostly unimplemented, just set NumCPUs field from sim and return
646 L2CTLR l2ctlr = 0;
647 // b00:1CPU to b11:4CPUs
648 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
649 return l2ctlr;
650 }

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1875 case MISCREG_CURRENTEL:
1876 {
1877 CPSR cpsr = miscRegs[MISCREG_CPSR];
1878 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1879 newVal = cpsr;
1880 misc_reg = MISCREG_CPSR;
1881 }
1882 break;
1883 case MISCREG_AT_S1E1R_Xt:
1884 case MISCREG_AT_S1E1W_Xt:
1885 case MISCREG_AT_S1E0R_Xt:
1886 case MISCREG_AT_S1E0W_Xt:
1887 case MISCREG_AT_S1E2R_Xt:
1888 case MISCREG_AT_S1E2W_Xt:
1889 case MISCREG_AT_S12E1R_Xt:
1890 case MISCREG_AT_S12E1W_Xt:

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2015 val, fsr, newVal);
2016 }
2017 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
2018 return;
2019 }
2020 case MISCREG_SPSR_EL3:
2021 case MISCREG_SPSR_EL2:
2022 case MISCREG_SPSR_EL1:
2023 // Force bits 23:21 to 0
2024 newVal = val & ~(0x7 << 21);
2025 break;
2026 case MISCREG_L2CTLR:
2027 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2028 miscRegName[misc_reg], uint32_t(val));
2029 break;
2030
2031 // Generic Timer registers
2032 case MISCREG_CNTHV_CTL_EL2:
2033 case MISCREG_CNTHV_CVAL_EL2:

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