1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58

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89 } else {
90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
91 haveSecurity = haveLPAE = haveVirtualization = false;
92 haveCrypto = true;
93 haveLargeAsid64 = false;
94 physAddrRange = 32; // dummy value
95 }
96
97 initializeMiscRegMetadata();
98 preUnflattenMiscReg();
99
100 clear();
101}
102
103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
104

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367 haveCrypto ? 0x1112 : 0x0);
368}
369
370void
371ISA::startup(ThreadContext *tc)
372{
373 pmu->setThreadContext(tc);
374
375}
376
377
378MiscReg
379ISA::readMiscRegNoEffect(int misc_reg) const
380{
381 assert(misc_reg < NumMiscRegs);
382

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667 { // Timer | Virti | !M Profile | TrustZone | ARMv4
668 bool haveTimer = (system->getGenericTimer() != NULL);
669 return 0x00000001
670 | (haveSecurity ? 0x00000010 : 0x0)
671 | (haveVirtualization ? 0x00001000 : 0x0)
672 | (haveTimer ? 0x00010000 : 0x0);
673 }
674 case MISCREG_ID_AA64PFR0_EL1:
675 return 0x0000000000000002 // AArch{64,32} supported at EL0
676 | 0x0000000000000020 // EL1
677 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
678 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
679 case MISCREG_ID_AA64PFR1_EL1:
680 return 0; // bits [63:0] RES0 (reserved for future use)
681
682 // Generic Timer registers
683 case MISCREG_CNTHV_CTL_EL2:
684 case MISCREG_CNTHV_CVAL_EL2:
685 case MISCREG_CNTHV_TVAL_EL2:
686 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
687 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
688 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
689 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
690 return getGenericTimer(tc).readMiscReg(misc_reg);
691
692 default:
693 break;
694
695 }
696 return readMiscRegNoEffect(misc_reg);
697}
698
699void

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1960 case MISCREG_CNTHV_CVAL_EL2:
1961 case MISCREG_CNTHV_TVAL_EL2:
1962 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1963 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1964 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1965 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1966 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1967 break;
1968 }
1969 }
1970 setMiscRegNoEffect(misc_reg, newVal);
1971}
1972
1973BaseISADevice &
1974ISA::getGenericTimer(ThreadContext *tc)
1975{

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1986 }
1987
1988 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1989 timer->setThreadContext(tc);
1990
1991 return *timer.get();
1992}
1993
1994}
1995
1996ArmISA::ISA *
1997ArmISAParams::create()
1998{
1999 return new ArmISA::ISA(this);
2000}