1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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77
78 system = dynamic_cast<ArmSystem *>(p->system);
79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
87 physAddrRange = system->physAddrRange();
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
92 physAddrRange = 32; // dummy value
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();

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117 initID32(p);
118
119 // We always initialize AArch64 ID registers even
120 // if we are in AArch32. This is done since if we
121 // are in SE mode we don't know if our ArmProcess is
122 // AArch32 or AArch64
123 initID64(p);
124
125 if (FullSystem && system->highestELIs64()) {
126 // Initialize AArch64 state
127 clear64(p);
128 return;
129 }
130
131 // Initialize AArch32 state...
132

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339 // Large ASID support
340 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
341 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
342 haveLargeAsid64 ? 0x2 : 0x0);
343 // Physical address size
344 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
345 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
346 encodePhysAddrRange64(physAddrRange));
347}
348
349void
350ISA::startup(ThreadContext *tc)
351{
352 pmu->setThreadContext(tc);
353
354}

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