1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 44 unchanged lines hidden (view full) ---
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * For each entry:
62 * The first value is the misc register that is to be looked up
63 * the second value is the lower part of the translation
64 * the third the upper part
65 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
66 */
67const struct ISA::MiscRegInitializerEntry
68 ISA::MiscRegSwitch[] = {
69 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}},
70 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}},
71 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}},
72 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}},
73 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}},
74 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
75 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}},
76 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}},
77 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}},
78 // ESR_EL1 -> DFSR
79 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
80 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
81 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
82 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
83 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}},
84 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
85 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}},
86 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
87 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
88 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
89 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
90 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
91 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
92 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
93 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
94 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
95 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
96 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
97 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}},
98 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}},
99 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}},
100 // RMR_EL1 -> RMR
101 // RMR_EL2 -> HRMR
102 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}},
103 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}},
104 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}},
105 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}},
106 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}},
107 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}},
108 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}},
109 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}},
110 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}},
111 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}},
112 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}},
113 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
114 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
115 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
116 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
117 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
118 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */
119 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
120 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
121 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}},
122 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */
123 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}},
124 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */
125 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
126 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */
127 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
128 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */
129 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */
130 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}},
131 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}},
132 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}},
133 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}},
134 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}},
135 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}},
136 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}},
137 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}},
138 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}},
139 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}},
140 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}},
141 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}},
142 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}},
143 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}},
144 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}},
145 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
146 // DBGDTRRX_EL0 -> DBGDTRRXint
147 // DBGDTRTX_EL0 -> DBGDTRRXint
148 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}},
149 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}},
150 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}},
151 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}},
152 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}},
153 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}},
154 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}},
155 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}},
156 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}},
157 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}},
158 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}},
159 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}},
160 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}},
161 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}},
162 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}},
163 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}},
164 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}},
165 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}},
166 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}},
167 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}},
168 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}},
169 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}},
170 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}},
171 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}},
172 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}},
173 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}},
174/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}},
175 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}},
176 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}},
177 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}},
178 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}},
179 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}},
180 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}},
181 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}},
182 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}},
183 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}},
184 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}},
185 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */
186 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}},
187 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}},
188// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}},
189 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}},
190 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}},
191 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}},
192 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}},
193 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}},
194 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}},
195
196 // from ARM DDI 0487A.i, template text
197 // "AArch64 System register ___ can be mapped to
198 // AArch32 System register ___, but this is not
199 // architecturally mandated."
200 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005
201 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
202 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1
203 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2
204 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3
205};
206
207
208ISA::ISA(Params *p)
209 : SimObject(p),
210 system(NULL),
211 _decoderFlavour(p->decoderFlavour),
212 _vecRegRenameMode(p->vecRegRenameMode),
213 pmu(p->pmu),
214 lookUpMiscReg(NUM_MISCREGS, {0,0})
215{
216 miscRegs[MISCREG_SCTLR_RST] = 0;
217
218 // Hook up a dummy device if we haven't been configured with a
219 // real PMU. By using a dummy device, we don't need to check that
220 // the PMU exist every time we try to access a PMU register.
221 if (!pmu)
222 pmu = &dummyDevice;
--- 13 unchanged lines hidden (view full) ---
236 physAddrRange64 = system->physAddrRange64();
237 } else {
238 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
239 haveSecurity = haveLPAE = haveVirtualization = false;
240 haveLargeAsid64 = false;
241 physAddrRange64 = 32; // dummy value
242 }
243
244 /** Fill in the miscReg translation table */
245 for (auto sw : MiscRegSwitch) {
246 lookUpMiscReg[sw.index] = sw.entry;
247 }
248
249 preUnflattenMiscReg();
250
251 clear();
252}
253
254const ArmISAParams *
255ISA::params() const
256{
--- 1770 unchanged lines hidden ---
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 44 unchanged lines hidden (view full) ---
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * For each entry:
62 * The first value is the misc register that is to be looked up
63 * the second value is the lower part of the translation
64 * the third the upper part
65 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
66 */
67const struct ISA::MiscRegInitializerEntry
68 ISA::MiscRegSwitch[] = {
69 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}},
70 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}},
71 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}},
72 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}},
73 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}},
74 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
75 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}},
76 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}},
77 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}},
78 // ESR_EL1 -> DFSR
79 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
80 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
81 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
82 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
83 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}},
84 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
85 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}},
86 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
87 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
88 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
89 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
90 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
91 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
92 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
93 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
94 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
95 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
96 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
97 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}},
98 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}},
99 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}},
100 // RMR_EL1 -> RMR
101 // RMR_EL2 -> HRMR
102 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}},
103 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}},
104 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}},
105 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}},
106 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}},
107 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}},
108 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}},
109 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}},
110 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}},
111 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}},
112 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}},
113 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
114 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
115 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
116 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
117 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
118 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */
119 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
120 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
121 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}},
122 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */
123 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}},
124 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */
125 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
126 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */
127 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
128 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */
129 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */
130 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}},
131 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}},
132 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}},
133 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}},
134 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}},
135 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}},
136 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}},
137 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}},
138 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}},
139 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}},
140 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}},
141 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}},
142 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}},
143 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}},
144 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}},
145 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
146 // DBGDTRRX_EL0 -> DBGDTRRXint
147 // DBGDTRTX_EL0 -> DBGDTRRXint
148 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}},
149 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}},
150 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}},
151 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}},
152 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}},
153 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}},
154 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}},
155 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}},
156 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}},
157 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}},
158 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}},
159 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}},
160 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}},
161 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}},
162 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}},
163 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}},
164 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}},
165 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}},
166 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}},
167 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}},
168 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}},
169 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}},
170 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}},
171 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}},
172 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}},
173 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}},
174/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}},
175 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}},
176 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}},
177 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}},
178 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}},
179 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}},
180 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}},
181 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}},
182 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}},
183 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}},
184 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}},
185 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */
186 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}},
187 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}},
188// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}},
189 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}},
190 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}},
191 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}},
192 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}},
193 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}},
194 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}},
195
196 // from ARM DDI 0487A.i, template text
197 // "AArch64 System register ___ can be mapped to
198 // AArch32 System register ___, but this is not
199 // architecturally mandated."
200 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005
201 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
202 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1
203 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2
204 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3
205};
206
207
208ISA::ISA(Params *p)
209 : SimObject(p),
210 system(NULL),
211 _decoderFlavour(p->decoderFlavour),
212 _vecRegRenameMode(p->vecRegRenameMode),
213 pmu(p->pmu),
214 lookUpMiscReg(NUM_MISCREGS, {0,0})
215{
216 miscRegs[MISCREG_SCTLR_RST] = 0;
217
218 // Hook up a dummy device if we haven't been configured with a
219 // real PMU. By using a dummy device, we don't need to check that
220 // the PMU exist every time we try to access a PMU register.
221 if (!pmu)
222 pmu = &dummyDevice;
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236 physAddrRange64 = system->physAddrRange64();
237 } else {
238 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
239 haveSecurity = haveLPAE = haveVirtualization = false;
240 haveLargeAsid64 = false;
241 physAddrRange64 = 32; // dummy value
242 }
243
244 /** Fill in the miscReg translation table */
245 for (auto sw : MiscRegSwitch) {
246 lookUpMiscReg[sw.index] = sw.entry;
247 }
248
249 preUnflattenMiscReg();
250
251 clear();
252}
253
254const ArmISAParams *
255ISA::params() const
256{
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