1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "params/ArmISA.hh"
52#include "sim/faults.hh"
53#include "sim/stat_control.hh"
54#include "sim/system.hh"
55
56namespace ArmISA
57{
58
59ISA::ISA(Params *p)
60 : SimObject(p),
61 system(NULL),
62 _decoderFlavour(p->decoderFlavour),
63 _vecRegRenameMode(p->vecRegRenameMode),
64 pmu(p->pmu),
65 impdefAsNop(p->impdef_nop)
66{
67 miscRegs[MISCREG_SCTLR_RST] = 0;
68
69 // Hook up a dummy device if we haven't been configured with a
70 // real PMU. By using a dummy device, we don't need to check that
71 // the PMU exist every time we try to access a PMU register.
72 if (!pmu)
73 pmu = &dummyDevice;
74
75 // Give all ISA devices a pointer to this ISA
76 pmu->setISA(this);
77
78 system = dynamic_cast<ArmSystem *>(p->system);
79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
87 physAddrRange64 = system->physAddrRange64();
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
92 physAddrRange64 = 32; // dummy value
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();
99}
100
101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
102
103const ArmISAParams *
104ISA::params() const
105{
106 return dynamic_cast<const Params *>(_params);
107}
108
109void
110ISA::clear()
111{
112 const Params *p(params());
113
114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
115 memset(miscRegs, 0, sizeof(miscRegs));
116
117 // Initialize configurable default values
118 miscRegs[MISCREG_MIDR] = p->midr;
119 miscRegs[MISCREG_MIDR_EL1] = p->midr;
120 miscRegs[MISCREG_VPIDR] = p->midr;
121
122 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
123 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
124 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
125 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
126 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
127 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
128
129 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
130 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
131 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
132 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
133
134 if (FullSystem && system->highestELIs64()) {
135 // Initialize AArch64 state
136 clear64(p);
137 return;
138 }
139
140 // Initialize AArch32 state...
141
142 CPSR cpsr = 0;
143 cpsr.mode = MODE_USER;
144 miscRegs[MISCREG_CPSR] = cpsr;
145 updateRegMap(cpsr);
146
147 SCTLR sctlr = 0;
148 sctlr.te = (bool) sctlr_rst.te;
149 sctlr.nmfi = (bool) sctlr_rst.nmfi;
150 sctlr.v = (bool) sctlr_rst.v;
151 sctlr.u = 1;
152 sctlr.xp = 1;
153 sctlr.rao2 = 1;
154 sctlr.rao3 = 1;
155 sctlr.rao4 = 0xf; // SCTLR[6:3]
156 sctlr.uci = 1;
157 sctlr.dze = 1;
158 miscRegs[MISCREG_SCTLR_NS] = sctlr;
159 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
160 miscRegs[MISCREG_HCPTR] = 0;
161
162 // Start with an event in the mailbox
163 miscRegs[MISCREG_SEV_MAILBOX] = 1;
164
165 // Separate Instruction and Data TLBs
166 miscRegs[MISCREG_TLBTR] = 1;
167
168 MVFR0 mvfr0 = 0;
169 mvfr0.advSimdRegisters = 2;
170 mvfr0.singlePrecision = 2;
171 mvfr0.doublePrecision = 2;
172 mvfr0.vfpExceptionTrapping = 0;
173 mvfr0.divide = 1;
174 mvfr0.squareRoot = 1;
175 mvfr0.shortVectors = 1;
176 mvfr0.roundingModes = 1;
177 miscRegs[MISCREG_MVFR0] = mvfr0;
178
179 MVFR1 mvfr1 = 0;
180 mvfr1.flushToZero = 1;
181 mvfr1.defaultNaN = 1;
182 mvfr1.advSimdLoadStore = 1;
183 mvfr1.advSimdInteger = 1;
184 mvfr1.advSimdSinglePrecision = 1;
185 mvfr1.advSimdHalfPrecision = 1;
186 mvfr1.vfpHalfPrecision = 1;
187 miscRegs[MISCREG_MVFR1] = mvfr1;
188
189 // Reset values of PRRR and NMRR are implementation dependent
190
191 // @todo: PRRR and NMRR in secure state?
192 miscRegs[MISCREG_PRRR_NS] =
193 (1 << 19) | // 19
194 (0 << 18) | // 18
195 (0 << 17) | // 17
196 (1 << 16) | // 16
197 (2 << 14) | // 15:14
198 (0 << 12) | // 13:12
199 (2 << 10) | // 11:10
200 (2 << 8) | // 9:8
201 (2 << 6) | // 7:6
202 (2 << 4) | // 5:4
203 (1 << 2) | // 3:2
204 0; // 1:0
205 miscRegs[MISCREG_NMRR_NS] =
206 (1 << 30) | // 31:30
207 (0 << 26) | // 27:26
208 (0 << 24) | // 25:24
209 (3 << 22) | // 23:22
210 (2 << 20) | // 21:20
211 (0 << 18) | // 19:18
212 (0 << 16) | // 17:16
213 (1 << 14) | // 15:14
214 (0 << 12) | // 13:12
215 (2 << 10) | // 11:10
216 (0 << 8) | // 9:8
217 (3 << 6) | // 7:6
218 (2 << 4) | // 5:4
219 (0 << 2) | // 3:2
220 0; // 1:0
221
222 miscRegs[MISCREG_CPACR] = 0;
223
224 miscRegs[MISCREG_FPSID] = p->fpsid;
225
226 if (haveLPAE) {
227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
228 ttbcr.eae = 0;
229 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
230 // Enforce consistency with system-level settings
231 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
232 }
233
234 if (haveSecurity) {
235 miscRegs[MISCREG_SCTLR_S] = sctlr;
236 miscRegs[MISCREG_SCR] = 0;
237 miscRegs[MISCREG_VBAR_S] = 0;
238 } else {
239 // we're always non-secure
240 miscRegs[MISCREG_SCR] = 1;
241 }
242
243 //XXX We need to initialize the rest of the state.
244}
245
246void
247ISA::clear64(const ArmISAParams *p)
248{
249 CPSR cpsr = 0;
250 Addr rvbar = system->resetAddr64();
251 switch (system->highestEL()) {
252 // Set initial EL to highest implemented EL using associated stack
253 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
254 // value
255 case EL3:
256 cpsr.mode = MODE_EL3H;
257 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
258 break;
259 case EL2:
260 cpsr.mode = MODE_EL2H;
261 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
262 break;
263 case EL1:
264 cpsr.mode = MODE_EL1H;
265 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
266 break;
267 default:
268 panic("Invalid highest implemented exception level");
269 break;
270 }
271
272 // Initialize rest of CPSR
273 cpsr.daif = 0xf; // Mask all interrupts
274 cpsr.ss = 0;
275 cpsr.il = 0;
276 miscRegs[MISCREG_CPSR] = cpsr;
277 updateRegMap(cpsr);
278
279 // Initialize other control registers
280 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
281 if (haveSecurity) {
282 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
283 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
284 } else if (haveVirtualization) {
285 // also MISCREG_SCTLR_EL2 (by mapping)
286 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
287 } else {
288 // also MISCREG_SCTLR_EL1 (by mapping)
289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
290 // Always non-secure
291 miscRegs[MISCREG_SCR_EL3] = 1;
292 }
293
294 // Initialize configurable id registers
295 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
296 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
297 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
298 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
299 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
300
301 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
302 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
303 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
304 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
305 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
306
307 miscRegs[MISCREG_ID_DFR0_EL1] =
308 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
309
310 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
311
312 // Enforce consistency with system-level settings...
313
314 // EL3
315 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
316 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
317 haveSecurity ? 0x2 : 0x0);
318 // EL2
319 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
320 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
321 haveVirtualization ? 0x2 : 0x0);
322 // Large ASID support
323 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
324 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
325 haveLargeAsid64 ? 0x2 : 0x0);
326 // Physical address size
327 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
328 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
329 encodePhysAddrRange64(physAddrRange64));
330}
331
332MiscReg
333ISA::readMiscRegNoEffect(int misc_reg) const
334{
335 assert(misc_reg < NumMiscRegs);
336
337 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
338 const auto &map = getMiscIndices(misc_reg);
339 int lower = map.first, upper = map.second;
340 // NB!: apply architectural masks according to desired register,
341 // despite possibly getting value from different (mapped) register.
342 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
343 |(miscRegs[upper] << 32));
344 if (val & reg.res0()) {
345 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
346 miscRegName[misc_reg], val & reg.res0());
347 }
348 if ((val & reg.res1()) != reg.res1()) {
349 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
350 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
351 }
352 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
353}
354
355
356MiscReg
357ISA::readMiscReg(int misc_reg, ThreadContext *tc)
358{
359 CPSR cpsr = 0;
360 PCState pc = 0;
361 SCR scr = 0;
362
363 if (misc_reg == MISCREG_CPSR) {
364 cpsr = miscRegs[misc_reg];
365 pc = tc->pcState();
366 cpsr.j = pc.jazelle() ? 1 : 0;
367 cpsr.t = pc.thumb() ? 1 : 0;
368 return cpsr;
369 }
370
371#ifndef NDEBUG
372 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
373 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
374 warn("Unimplemented system register %s read.\n",
375 miscRegName[misc_reg]);
376 else
377 panic("Unimplemented system register %s read.\n",
378 miscRegName[misc_reg]);
379 }
380#endif
381
382 switch (unflattenMiscReg(misc_reg)) {
383 case MISCREG_HCR:
384 {
385 if (!haveVirtualization)
386 return 0;
387 else
388 return readMiscRegNoEffect(MISCREG_HCR);
389 }
390 case MISCREG_CPACR:
391 {
392 const uint32_t ones = (uint32_t)(-1);
393 CPACR cpacrMask = 0;
394 // Only cp10, cp11, and ase are implemented, nothing else should
395 // be readable? (straight copy from the write code)
396 cpacrMask.cp10 = ones;
397 cpacrMask.cp11 = ones;
398 cpacrMask.asedis = ones;
399
400 // Security Extensions may limit the readability of CPACR
401 if (haveSecurity) {
402 scr = readMiscRegNoEffect(MISCREG_SCR);
403 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
404 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
405 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
406 // NB: Skipping the full loop, here
407 if (!nsacr.cp10) cpacrMask.cp10 = 0;
408 if (!nsacr.cp11) cpacrMask.cp11 = 0;
409 }
410 }
411 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
412 val &= cpacrMask;
413 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
414 miscRegName[misc_reg], val);
415 return val;
416 }
417 case MISCREG_MPIDR:
418 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
419 scr = readMiscRegNoEffect(MISCREG_SCR);
420 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
421 return getMPIDR(system, tc);
422 } else {
423 return readMiscReg(MISCREG_VMPIDR, tc);
424 }
425 break;
426 case MISCREG_MPIDR_EL1:
427 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
428 return getMPIDR(system, tc) & 0xffffffff;
429 case MISCREG_VMPIDR:
430 // top bit defined as RES1
431 return readMiscRegNoEffect(misc_reg) | 0x80000000;
432 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
433 case MISCREG_REVIDR: // not implemented, so alias MIDR
434 case MISCREG_MIDR:
435 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
436 scr = readMiscRegNoEffect(MISCREG_SCR);
437 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
438 return readMiscRegNoEffect(misc_reg);
439 } else {
440 return readMiscRegNoEffect(MISCREG_VPIDR);
441 }
442 break;
443 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
445 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
446 case MISCREG_AIDR: // AUX ID set to 0
447 case MISCREG_TCMTR: // No TCM's
448 return 0;
449
450 case MISCREG_CLIDR:
451 warn_once("The clidr register always reports 0 caches.\n");
452 warn_once("clidr LoUIS field of 0b001 to match current "
453 "ARM implementations.\n");
454 return 0x00200000;
455 case MISCREG_CCSIDR:
456 warn_once("The ccsidr register isn't implemented and "
457 "always reads as 0.\n");
458 break;
459 case MISCREG_CTR: // AArch32, ARMv7, top bit set
460 case MISCREG_CTR_EL0: // AArch64
461 {
462 //all caches have the same line size in gem5
463 //4 byte words in ARM
464 unsigned lineSizeWords =
465 tc->getSystemPtr()->cacheLineSize() / 4;
466 unsigned log2LineSizeWords = 0;
467
468 while (lineSizeWords >>= 1) {
469 ++log2LineSizeWords;
470 }
471
472 CTR ctr = 0;
473 //log2 of minimun i-cache line size (words)
474 ctr.iCacheLineSize = log2LineSizeWords;
475 //b11 - gem5 uses pipt
476 ctr.l1IndexPolicy = 0x3;
477 //log2 of minimum d-cache line size (words)
478 ctr.dCacheLineSize = log2LineSizeWords;
479 //log2 of max reservation size (words)
480 ctr.erg = log2LineSizeWords;
481 //log2 of max writeback size (words)
482 ctr.cwg = log2LineSizeWords;
483 //b100 - gem5 format is ARMv7
484 ctr.format = 0x4;
485
486 return ctr;
487 }
488 case MISCREG_ACTLR:
489 warn("Not doing anything for miscreg ACTLR\n");
490 break;
491
492 case MISCREG_PMXEVTYPER_PMCCFILTR:
493 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
494 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
495 case MISCREG_PMCR ... MISCREG_PMOVSSET:
496 return pmu->readMiscReg(misc_reg);
497
498 case MISCREG_CPSR_Q:
499 panic("shouldn't be reading this register seperately\n");
500 case MISCREG_FPSCR_QC:
501 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
502 case MISCREG_FPSCR_EXC:
503 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
504 case MISCREG_FPSR:
505 {
506 const uint32_t ones = (uint32_t)(-1);
507 FPSCR fpscrMask = 0;
508 fpscrMask.ioc = ones;
509 fpscrMask.dzc = ones;
510 fpscrMask.ofc = ones;
511 fpscrMask.ufc = ones;
512 fpscrMask.ixc = ones;
513 fpscrMask.idc = ones;
514 fpscrMask.qc = ones;
515 fpscrMask.v = ones;
516 fpscrMask.c = ones;
517 fpscrMask.z = ones;
518 fpscrMask.n = ones;
519 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
520 }
521 case MISCREG_FPCR:
522 {
523 const uint32_t ones = (uint32_t)(-1);
524 FPSCR fpscrMask = 0;
525 fpscrMask.len = ones;
526 fpscrMask.stride = ones;
527 fpscrMask.rMode = ones;
528 fpscrMask.fz = ones;
529 fpscrMask.dn = ones;
530 fpscrMask.ahp = ones;
531 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
532 }
533 case MISCREG_NZCV:
534 {
535 CPSR cpsr = 0;
536 cpsr.nz = tc->readCCReg(CCREG_NZ);
537 cpsr.c = tc->readCCReg(CCREG_C);
538 cpsr.v = tc->readCCReg(CCREG_V);
539 return cpsr;
540 }
541 case MISCREG_DAIF:
542 {
543 CPSR cpsr = 0;
544 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
545 return cpsr;
546 }
547 case MISCREG_SP_EL0:
548 {
549 return tc->readIntReg(INTREG_SP0);
550 }
551 case MISCREG_SP_EL1:
552 {
553 return tc->readIntReg(INTREG_SP1);
554 }
555 case MISCREG_SP_EL2:
556 {
557 return tc->readIntReg(INTREG_SP2);
558 }
559 case MISCREG_SPSEL:
560 {
561 return miscRegs[MISCREG_CPSR] & 0x1;
562 }
563 case MISCREG_CURRENTEL:
564 {
565 return miscRegs[MISCREG_CPSR] & 0xc;
566 }
567 case MISCREG_L2CTLR:
568 {
569 // mostly unimplemented, just set NumCPUs field from sim and return
570 L2CTLR l2ctlr = 0;
571 // b00:1CPU to b11:4CPUs
572 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
573 return l2ctlr;
574 }
575 case MISCREG_DBGDIDR:
576 /* For now just implement the version number.
577 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
578 */
579 return 0x5 << 16;
580 case MISCREG_DBGDSCRint:
581 return 0;
582 case MISCREG_ISR:
583 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
584 readMiscRegNoEffect(MISCREG_HCR),
585 readMiscRegNoEffect(MISCREG_CPSR),
586 readMiscRegNoEffect(MISCREG_SCR));
587 case MISCREG_ISR_EL1:
588 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
589 readMiscRegNoEffect(MISCREG_HCR_EL2),
590 readMiscRegNoEffect(MISCREG_CPSR),
591 readMiscRegNoEffect(MISCREG_SCR_EL3));
592 case MISCREG_DCZID_EL0:
593 return 0x04; // DC ZVA clear 64-byte chunks
594 case MISCREG_HCPTR:
595 {
596 MiscReg val = readMiscRegNoEffect(misc_reg);
597 // The trap bit associated with CP14 is defined as RAZ
598 val &= ~(1 << 14);
599 // If a CP bit in NSACR is 0 then the corresponding bit in
600 // HCPTR is RAO/WI
601 bool secure_lookup = haveSecurity &&
602 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
603 readMiscRegNoEffect(MISCREG_CPSR));
604 if (!secure_lookup) {
605 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
606 val |= (mask ^ 0x7FFF) & 0xBFFF;
607 }
608 // Set the bits for unimplemented coprocessors to RAO/WI
609 val |= 0x33FF;
610 return (val);
611 }
612 case MISCREG_HDFAR: // alias for secure DFAR
613 return readMiscRegNoEffect(MISCREG_DFAR_S);
614 case MISCREG_HIFAR: // alias for secure IFAR
615 return readMiscRegNoEffect(MISCREG_IFAR_S);
616 case MISCREG_HVBAR: // bottom bits reserved
617 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
618 case MISCREG_SCTLR:
619 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
620 case MISCREG_SCTLR_EL1:
621 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
622 case MISCREG_SCTLR_EL2:
623 case MISCREG_SCTLR_EL3:
624 case MISCREG_HSCTLR:
625 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
626
627 case MISCREG_ID_PFR0:
628 // !ThumbEE | !Jazelle | Thumb | ARM
629 return 0x00000031;
630 case MISCREG_ID_PFR1:
631 { // Timer | Virti | !M Profile | TrustZone | ARMv4
632 bool haveTimer = (system->getGenericTimer() != NULL);
633 return 0x00000001
634 | (haveSecurity ? 0x00000010 : 0x0)
635 | (haveVirtualization ? 0x00001000 : 0x0)
636 | (haveTimer ? 0x00010000 : 0x0);
637 }
638 case MISCREG_ID_AA64PFR0_EL1:
639 return 0x0000000000000002 // AArch{64,32} supported at EL0
640 | 0x0000000000000020 // EL1
641 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
642 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
643 case MISCREG_ID_AA64PFR1_EL1:
644 return 0; // bits [63:0] RES0 (reserved for future use)
645
646 // Generic Timer registers
647 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
648 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
649 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
650 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
651 return getGenericTimer(tc).readMiscReg(misc_reg);
652
653 default:
654 break;
655
656 }
657 return readMiscRegNoEffect(misc_reg);
658}
659
660void
661ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
662{
663 assert(misc_reg < NumMiscRegs);
664
665 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
666 const auto &map = getMiscIndices(misc_reg);
667 int lower = map.first, upper = map.second;
668
669 auto v = (val & ~reg.wi()) | reg.rao();
670 if (upper > 0) {
671 miscRegs[lower] = bits(v, 31, 0);
672 miscRegs[upper] = bits(v, 63, 32);
673 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
674 misc_reg, lower, upper, v);
675 } else {
676 miscRegs[lower] = v;
677 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
678 misc_reg, lower, v);
679 }
680}
681
682void
683ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
684{
685
686 MiscReg newVal = val;
687 bool secure_lookup;
688 SCR scr;
689
690 if (misc_reg == MISCREG_CPSR) {
691 updateRegMap(val);
692
693
694 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
695 int old_mode = old_cpsr.mode;
696 CPSR cpsr = val;
697 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
698 getITBPtr(tc)->invalidateMiscReg();
699 getDTBPtr(tc)->invalidateMiscReg();
700 }
701
702 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
703 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
704 PCState pc = tc->pcState();
705 pc.nextThumb(cpsr.t);
706 pc.nextJazelle(cpsr.j);
707 pc.illegalExec(cpsr.il == 1);
708
709 // Follow slightly different semantics if a CheckerCPU object
710 // is connected
711 CheckerCPU *checker = tc->getCheckerCpuPtr();
712 if (checker) {
713 tc->pcStateNoRecord(pc);
714 } else {
715 tc->pcState(pc);
716 }
717 } else {
718#ifndef NDEBUG
719 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
720 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
721 warn("Unimplemented system register %s write with %#x.\n",
722 miscRegName[misc_reg], val);
723 else
724 panic("Unimplemented system register %s write with %#x.\n",
725 miscRegName[misc_reg], val);
726 }
727#endif
728 switch (unflattenMiscReg(misc_reg)) {
729 case MISCREG_CPACR:
730 {
731
732 const uint32_t ones = (uint32_t)(-1);
733 CPACR cpacrMask = 0;
734 // Only cp10, cp11, and ase are implemented, nothing else should
735 // be writable
736 cpacrMask.cp10 = ones;
737 cpacrMask.cp11 = ones;
738 cpacrMask.asedis = ones;
739
740 // Security Extensions may limit the writability of CPACR
741 if (haveSecurity) {
742 scr = readMiscRegNoEffect(MISCREG_SCR);
743 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
744 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
745 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
746 // NB: Skipping the full loop, here
747 if (!nsacr.cp10) cpacrMask.cp10 = 0;
748 if (!nsacr.cp11) cpacrMask.cp11 = 0;
749 }
750 }
751
752 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
753 newVal &= cpacrMask;
754 newVal |= old_val & ~cpacrMask;
755 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
756 miscRegName[misc_reg], newVal);
757 }
758 break;
759 case MISCREG_CPTR_EL2:
760 {
761 const uint32_t ones = (uint32_t)(-1);
762 CPTR cptrMask = 0;
763 cptrMask.tcpac = ones;
764 cptrMask.tta = ones;
765 cptrMask.tfp = ones;
766 newVal &= cptrMask;
767 cptrMask = 0;
768 cptrMask.res1_13_12_el2 = ones;
769 cptrMask.res1_9_0_el2 = ones;
770 newVal |= cptrMask;
771 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
772 miscRegName[misc_reg], newVal);
773 }
774 break;
775 case MISCREG_CPTR_EL3:
776 {
777 const uint32_t ones = (uint32_t)(-1);
778 CPTR cptrMask = 0;
779 cptrMask.tcpac = ones;
780 cptrMask.tta = ones;
781 cptrMask.tfp = ones;
782 newVal &= cptrMask;
783 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
784 miscRegName[misc_reg], newVal);
785 }
786 break;
787 case MISCREG_CSSELR:
788 warn_once("The csselr register isn't implemented.\n");
789 return;
790
791 case MISCREG_DC_ZVA_Xt:
792 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
793 return;
794
795 case MISCREG_FPSCR:
796 {
797 const uint32_t ones = (uint32_t)(-1);
798 FPSCR fpscrMask = 0;
799 fpscrMask.ioc = ones;
800 fpscrMask.dzc = ones;
801 fpscrMask.ofc = ones;
802 fpscrMask.ufc = ones;
803 fpscrMask.ixc = ones;
804 fpscrMask.idc = ones;
805 fpscrMask.ioe = ones;
806 fpscrMask.dze = ones;
807 fpscrMask.ofe = ones;
808 fpscrMask.ufe = ones;
809 fpscrMask.ixe = ones;
810 fpscrMask.ide = ones;
811 fpscrMask.len = ones;
812 fpscrMask.stride = ones;
813 fpscrMask.rMode = ones;
814 fpscrMask.fz = ones;
815 fpscrMask.dn = ones;
816 fpscrMask.ahp = ones;
817 fpscrMask.qc = ones;
818 fpscrMask.v = ones;
819 fpscrMask.c = ones;
820 fpscrMask.z = ones;
821 fpscrMask.n = ones;
822 newVal = (newVal & (uint32_t)fpscrMask) |
823 (readMiscRegNoEffect(MISCREG_FPSCR) &
824 ~(uint32_t)fpscrMask);
825 tc->getDecoderPtr()->setContext(newVal);
826 }
827 break;
828 case MISCREG_FPSR:
829 {
830 const uint32_t ones = (uint32_t)(-1);
831 FPSCR fpscrMask = 0;
832 fpscrMask.ioc = ones;
833 fpscrMask.dzc = ones;
834 fpscrMask.ofc = ones;
835 fpscrMask.ufc = ones;
836 fpscrMask.ixc = ones;
837 fpscrMask.idc = ones;
838 fpscrMask.qc = ones;
839 fpscrMask.v = ones;
840 fpscrMask.c = ones;
841 fpscrMask.z = ones;
842 fpscrMask.n = ones;
843 newVal = (newVal & (uint32_t)fpscrMask) |
844 (readMiscRegNoEffect(MISCREG_FPSCR) &
845 ~(uint32_t)fpscrMask);
846 misc_reg = MISCREG_FPSCR;
847 }
848 break;
849 case MISCREG_FPCR:
850 {
851 const uint32_t ones = (uint32_t)(-1);
852 FPSCR fpscrMask = 0;
853 fpscrMask.len = ones;
854 fpscrMask.stride = ones;
855 fpscrMask.rMode = ones;
856 fpscrMask.fz = ones;
857 fpscrMask.dn = ones;
858 fpscrMask.ahp = ones;
859 newVal = (newVal & (uint32_t)fpscrMask) |
860 (readMiscRegNoEffect(MISCREG_FPSCR) &
861 ~(uint32_t)fpscrMask);
862 misc_reg = MISCREG_FPSCR;
863 }
864 break;
865 case MISCREG_CPSR_Q:
866 {
867 assert(!(newVal & ~CpsrMaskQ));
868 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
869 misc_reg = MISCREG_CPSR;
870 }
871 break;
872 case MISCREG_FPSCR_QC:
873 {
874 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
875 (newVal & FpscrQcMask);
876 misc_reg = MISCREG_FPSCR;
877 }
878 break;
879 case MISCREG_FPSCR_EXC:
880 {
881 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
882 (newVal & FpscrExcMask);
883 misc_reg = MISCREG_FPSCR;
884 }
885 break;
886 case MISCREG_FPEXC:
887 {
888 // vfpv3 architecture, section B.6.1 of DDI04068
889 // bit 29 - valid only if fpexc[31] is 0
890 const uint32_t fpexcMask = 0x60000000;
891 newVal = (newVal & fpexcMask) |
892 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
893 }
894 break;
895 case MISCREG_HCR:
896 {
897 if (!haveVirtualization)
898 return;
899 }
900 break;
901 case MISCREG_IFSR:
902 {
903 // ARM ARM (ARM DDI 0406C.b) B4.1.96
904 const uint32_t ifsrMask =
905 mask(31, 13) | mask(11, 11) | mask(8, 6);
906 newVal = newVal & ~ifsrMask;
907 }
908 break;
909 case MISCREG_DFSR:
910 {
911 // ARM ARM (ARM DDI 0406C.b) B4.1.52
912 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
913 newVal = newVal & ~dfsrMask;
914 }
915 break;
916 case MISCREG_AMAIR0:
917 case MISCREG_AMAIR1:
918 {
919 // ARM ARM (ARM DDI 0406C.b) B4.1.5
920 // Valid only with LPAE
921 if (!haveLPAE)
922 return;
923 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
924 }
925 break;
926 case MISCREG_SCR:
927 getITBPtr(tc)->invalidateMiscReg();
928 getDTBPtr(tc)->invalidateMiscReg();
929 break;
930 case MISCREG_SCTLR:
931 {
932 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
933 scr = readMiscRegNoEffect(MISCREG_SCR);
934
935 MiscRegIndex sctlr_idx;
936 if (haveSecurity && !highestELIs64 && !scr.ns) {
937 sctlr_idx = MISCREG_SCTLR_S;
938 } else {
939 sctlr_idx = MISCREG_SCTLR_NS;
940 }
941
942 SCTLR sctlr = miscRegs[sctlr_idx];
943 SCTLR new_sctlr = newVal;
944 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
945 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
946 getITBPtr(tc)->invalidateMiscReg();
947 getDTBPtr(tc)->invalidateMiscReg();
948 }
949 case MISCREG_MIDR:
950 case MISCREG_ID_PFR0:
951 case MISCREG_ID_PFR1:
952 case MISCREG_ID_DFR0:
953 case MISCREG_ID_MMFR0:
954 case MISCREG_ID_MMFR1:
955 case MISCREG_ID_MMFR2:
956 case MISCREG_ID_MMFR3:
957 case MISCREG_ID_ISAR0:
958 case MISCREG_ID_ISAR1:
959 case MISCREG_ID_ISAR2:
960 case MISCREG_ID_ISAR3:
961 case MISCREG_ID_ISAR4:
962 case MISCREG_ID_ISAR5:
963
964 case MISCREG_MPIDR:
965 case MISCREG_FPSID:
966 case MISCREG_TLBTR:
967 case MISCREG_MVFR0:
968 case MISCREG_MVFR1:
969
970 case MISCREG_ID_AA64AFR0_EL1:
971 case MISCREG_ID_AA64AFR1_EL1:
972 case MISCREG_ID_AA64DFR0_EL1:
973 case MISCREG_ID_AA64DFR1_EL1:
974 case MISCREG_ID_AA64ISAR0_EL1:
975 case MISCREG_ID_AA64ISAR1_EL1:
976 case MISCREG_ID_AA64MMFR0_EL1:
977 case MISCREG_ID_AA64MMFR1_EL1:
978 case MISCREG_ID_AA64PFR0_EL1:
979 case MISCREG_ID_AA64PFR1_EL1:
980 // ID registers are constants.
981 return;
982
983 // TLB Invalidate All
984 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
985 {
986 assert32(tc);
987 scr = readMiscReg(MISCREG_SCR, tc);
988
989 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
990 tlbiOp(tc);
991 return;
992 }
993 // TLB Invalidate All, Inner Shareable
994 case MISCREG_TLBIALLIS:
995 {
996 assert32(tc);
997 scr = readMiscReg(MISCREG_SCR, tc);
998
999 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1000 tlbiOp.broadcast(tc);
1001 return;
1002 }
1003 // Instruction TLB Invalidate All
1004 case MISCREG_ITLBIALL:
1005 {
1006 assert32(tc);
1007 scr = readMiscReg(MISCREG_SCR, tc);
1008
1009 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1010 tlbiOp(tc);
1011 return;
1012 }
1013 // Data TLB Invalidate All
1014 case MISCREG_DTLBIALL:
1015 {
1016 assert32(tc);
1017 scr = readMiscReg(MISCREG_SCR, tc);
1018
1019 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1020 tlbiOp(tc);
1021 return;
1022 }
1023 // TLB Invalidate by VA
1024 // mcr tlbimval(is) is invalidating all matching entries
1025 // regardless of the level of lookup, since in gem5 we cache
1026 // in the tlb the last level of lookup only.
1027 case MISCREG_TLBIMVA:
1028 case MISCREG_TLBIMVAL:
1029 {
1030 assert32(tc);
1031 scr = readMiscReg(MISCREG_SCR, tc);
1032
1033 TLBIMVA tlbiOp(EL1,
1034 haveSecurity && !scr.ns,
1035 mbits(newVal, 31, 12),
1036 bits(newVal, 7,0));
1037
1038 tlbiOp(tc);
1039 return;
1040 }
1041 // TLB Invalidate by VA, Inner Shareable
1042 case MISCREG_TLBIMVAIS:
1043 case MISCREG_TLBIMVALIS:
1044 {
1045 assert32(tc);
1046 scr = readMiscReg(MISCREG_SCR, tc);
1047
1048 TLBIMVA tlbiOp(EL1,
1049 haveSecurity && !scr.ns,
1050 mbits(newVal, 31, 12),
1051 bits(newVal, 7,0));
1052
1053 tlbiOp.broadcast(tc);
1054 return;
1055 }
1056 // TLB Invalidate by ASID match
1057 case MISCREG_TLBIASID:
1058 {
1059 assert32(tc);
1060 scr = readMiscReg(MISCREG_SCR, tc);
1061
1062 TLBIASID tlbiOp(EL1,
1063 haveSecurity && !scr.ns,
1064 bits(newVal, 7,0));
1065
1066 tlbiOp(tc);
1067 return;
1068 }
1069 // TLB Invalidate by ASID match, Inner Shareable
1070 case MISCREG_TLBIASIDIS:
1071 {
1072 assert32(tc);
1073 scr = readMiscReg(MISCREG_SCR, tc);
1074
1075 TLBIASID tlbiOp(EL1,
1076 haveSecurity && !scr.ns,
1077 bits(newVal, 7,0));
1078
1079 tlbiOp.broadcast(tc);
1080 return;
1081 }
1082 // mcr tlbimvaal(is) is invalidating all matching entries
1083 // regardless of the level of lookup, since in gem5 we cache
1084 // in the tlb the last level of lookup only.
1085 // TLB Invalidate by VA, All ASID
1086 case MISCREG_TLBIMVAA:
1087 case MISCREG_TLBIMVAAL:
1088 {
1089 assert32(tc);
1090 scr = readMiscReg(MISCREG_SCR, tc);
1091
1092 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1093 mbits(newVal, 31,12), false);
1094
1095 tlbiOp(tc);
1096 return;
1097 }
1098 // TLB Invalidate by VA, All ASID, Inner Shareable
1099 case MISCREG_TLBIMVAAIS:
1100 case MISCREG_TLBIMVAALIS:
1101 {
1102 assert32(tc);
1103 scr = readMiscReg(MISCREG_SCR, tc);
1104
1105 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1106 mbits(newVal, 31,12), false);
1107
1108 tlbiOp.broadcast(tc);
1109 return;
1110 }
1111 // mcr tlbimvalh(is) is invalidating all matching entries
1112 // regardless of the level of lookup, since in gem5 we cache
1113 // in the tlb the last level of lookup only.
1114 // TLB Invalidate by VA, Hyp mode
1115 case MISCREG_TLBIMVAH:
1116 case MISCREG_TLBIMVALH:
1117 {
1118 assert32(tc);
1119 scr = readMiscReg(MISCREG_SCR, tc);
1120
1121 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1122 mbits(newVal, 31,12), true);
1123
1124 tlbiOp(tc);
1125 return;
1126 }
1127 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1128 case MISCREG_TLBIMVAHIS:
1129 case MISCREG_TLBIMVALHIS:
1130 {
1131 assert32(tc);
1132 scr = readMiscReg(MISCREG_SCR, tc);
1133
1134 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1135 mbits(newVal, 31,12), true);
1136
1137 tlbiOp.broadcast(tc);
1138 return;
1139 }
1140 // mcr tlbiipas2l(is) is invalidating all matching entries
1141 // regardless of the level of lookup, since in gem5 we cache
1142 // in the tlb the last level of lookup only.
1143 // TLB Invalidate by Intermediate Physical Address, Stage 2
1144 case MISCREG_TLBIIPAS2:
1145 case MISCREG_TLBIIPAS2L:
1146 {
1147 assert32(tc);
1148 scr = readMiscReg(MISCREG_SCR, tc);
1149
1150 TLBIIPA tlbiOp(EL1,
1151 haveSecurity && !scr.ns,
1152 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1153
1154 tlbiOp(tc);
1155 return;
1156 }
1157 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1158 // Inner Shareable
1159 case MISCREG_TLBIIPAS2IS:
1160 case MISCREG_TLBIIPAS2LIS:
1161 {
1162 assert32(tc);
1163 scr = readMiscReg(MISCREG_SCR, tc);
1164
1165 TLBIIPA tlbiOp(EL1,
1166 haveSecurity && !scr.ns,
1167 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1168
1169 tlbiOp.broadcast(tc);
1170 return;
1171 }
1172 // Instruction TLB Invalidate by VA
1173 case MISCREG_ITLBIMVA:
1174 {
1175 assert32(tc);
1176 scr = readMiscReg(MISCREG_SCR, tc);
1177
1178 ITLBIMVA tlbiOp(EL1,
1179 haveSecurity && !scr.ns,
1180 mbits(newVal, 31, 12),
1181 bits(newVal, 7,0));
1182
1183 tlbiOp(tc);
1184 return;
1185 }
1186 // Data TLB Invalidate by VA
1187 case MISCREG_DTLBIMVA:
1188 {
1189 assert32(tc);
1190 scr = readMiscReg(MISCREG_SCR, tc);
1191
1192 DTLBIMVA tlbiOp(EL1,
1193 haveSecurity && !scr.ns,
1194 mbits(newVal, 31, 12),
1195 bits(newVal, 7,0));
1196
1197 tlbiOp(tc);
1198 return;
1199 }
1200 // Instruction TLB Invalidate by ASID match
1201 case MISCREG_ITLBIASID:
1202 {
1203 assert32(tc);
1204 scr = readMiscReg(MISCREG_SCR, tc);
1205
1206 ITLBIASID tlbiOp(EL1,
1207 haveSecurity && !scr.ns,
1208 bits(newVal, 7,0));
1209
1210 tlbiOp(tc);
1211 return;
1212 }
1213 // Data TLB Invalidate by ASID match
1214 case MISCREG_DTLBIASID:
1215 {
1216 assert32(tc);
1217 scr = readMiscReg(MISCREG_SCR, tc);
1218
1219 DTLBIASID tlbiOp(EL1,
1220 haveSecurity && !scr.ns,
1221 bits(newVal, 7,0));
1222
1223 tlbiOp(tc);
1224 return;
1225 }
1226 // TLB Invalidate All, Non-Secure Non-Hyp
1227 case MISCREG_TLBIALLNSNH:
1228 {
1229 assert32(tc);
1230
1231 TLBIALLN tlbiOp(EL1, false);
1232 tlbiOp(tc);
1233 return;
1234 }
1235 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1236 case MISCREG_TLBIALLNSNHIS:
1237 {
1238 assert32(tc);
1239
1240 TLBIALLN tlbiOp(EL1, false);
1241 tlbiOp.broadcast(tc);
1242 return;
1243 }
1244 // TLB Invalidate All, Hyp mode
1245 case MISCREG_TLBIALLH:
1246 {
1247 assert32(tc);
1248
1249 TLBIALLN tlbiOp(EL1, true);
1250 tlbiOp(tc);
1251 return;
1252 }
1253 // TLB Invalidate All, Hyp mode, Inner Shareable
1254 case MISCREG_TLBIALLHIS:
1255 {
1256 assert32(tc);
1257
1258 TLBIALLN tlbiOp(EL1, true);
1259 tlbiOp.broadcast(tc);
1260 return;
1261 }
1262 // AArch64 TLB Invalidate All, EL3
1263 case MISCREG_TLBI_ALLE3:
1264 {
1265 assert64(tc);
1266
1267 TLBIALL tlbiOp(EL3, true);
1268 tlbiOp(tc);
1269 return;
1270 }
1271 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1272 case MISCREG_TLBI_ALLE3IS:
1273 {
1274 assert64(tc);
1275
1276 TLBIALL tlbiOp(EL3, true);
1277 tlbiOp.broadcast(tc);
1278 return;
1279 }
1280 // @todo: uncomment this to enable Virtualization
1281 // case MISCREG_TLBI_ALLE2IS:
1282 // case MISCREG_TLBI_ALLE2:
1283 // AArch64 TLB Invalidate All, EL1
1284 case MISCREG_TLBI_ALLE1:
1285 case MISCREG_TLBI_VMALLE1:
1286 case MISCREG_TLBI_VMALLS12E1:
1287 // @todo: handle VMID and stage 2 to enable Virtualization
1288 {
1289 assert64(tc);
1290 scr = readMiscReg(MISCREG_SCR, tc);
1291
1292 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1293 tlbiOp(tc);
1294 return;
1295 }
1296 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1297 case MISCREG_TLBI_ALLE1IS:
1298 case MISCREG_TLBI_VMALLE1IS:
1299 case MISCREG_TLBI_VMALLS12E1IS:
1300 // @todo: handle VMID and stage 2 to enable Virtualization
1301 {
1302 assert64(tc);
1303 scr = readMiscReg(MISCREG_SCR, tc);
1304
1305 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1306 tlbiOp.broadcast(tc);
1307 return;
1308 }
1309 // VAEx(IS) and VALEx(IS) are the same because TLBs
1310 // only store entries
1311 // from the last level of translation table walks
1312 // @todo: handle VMID to enable Virtualization
1313 // AArch64 TLB Invalidate by VA, EL3
1314 case MISCREG_TLBI_VAE3_Xt:
1315 case MISCREG_TLBI_VALE3_Xt:
1316 {
1317 assert64(tc);
1318
1319 TLBIMVA tlbiOp(EL3, true,
1320 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1321 0xbeef);
1322 tlbiOp(tc);
1323 return;
1324 }
1325 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1326 case MISCREG_TLBI_VAE3IS_Xt:
1327 case MISCREG_TLBI_VALE3IS_Xt:
1328 {
1329 assert64(tc);
1330
1331 TLBIMVA tlbiOp(EL3, true,
1332 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1333 0xbeef);
1334
1335 tlbiOp.broadcast(tc);
1336 return;
1337 }
1338 // AArch64 TLB Invalidate by VA, EL2
1339 case MISCREG_TLBI_VAE2_Xt:
1340 case MISCREG_TLBI_VALE2_Xt:
1341 {
1342 assert64(tc);
1343 scr = readMiscReg(MISCREG_SCR, tc);
1344
1345 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1346 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1347 0xbeef);
1348 tlbiOp(tc);
1349 return;
1350 }
1351 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1352 case MISCREG_TLBI_VAE2IS_Xt:
1353 case MISCREG_TLBI_VALE2IS_Xt:
1354 {
1355 assert64(tc);
1356 scr = readMiscReg(MISCREG_SCR, tc);
1357
1358 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1359 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1360 0xbeef);
1361
1362 tlbiOp.broadcast(tc);
1363 return;
1364 }
1365 // AArch64 TLB Invalidate by VA, EL1
1366 case MISCREG_TLBI_VAE1_Xt:
1367 case MISCREG_TLBI_VALE1_Xt:
1368 {
1369 assert64(tc);
1370 scr = readMiscReg(MISCREG_SCR, tc);
1371 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1372 bits(newVal, 55, 48);
1373
1374 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1375 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1376 asid);
1377
1378 tlbiOp(tc);
1379 return;
1380 }
1381 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1382 case MISCREG_TLBI_VAE1IS_Xt:
1383 case MISCREG_TLBI_VALE1IS_Xt:
1384 {
1385 assert64(tc);
1386 scr = readMiscReg(MISCREG_SCR, tc);
1387 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1388 bits(newVal, 55, 48);
1389
1390 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1391 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1392 asid);
1393
1394 tlbiOp.broadcast(tc);
1395 return;
1396 }
1397 // AArch64 TLB Invalidate by ASID, EL1
1398 // @todo: handle VMID to enable Virtualization
1399 case MISCREG_TLBI_ASIDE1_Xt:
1400 {
1401 assert64(tc);
1402 scr = readMiscReg(MISCREG_SCR, tc);
1403 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1404 bits(newVal, 55, 48);
1405
1406 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1407 tlbiOp(tc);
1408 return;
1409 }
1410 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1411 case MISCREG_TLBI_ASIDE1IS_Xt:
1412 {
1413 assert64(tc);
1414 scr = readMiscReg(MISCREG_SCR, tc);
1415 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1416 bits(newVal, 55, 48);
1417
1418 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1419 tlbiOp.broadcast(tc);
1420 return;
1421 }
1422 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1423 // entries from the last level of translation table walks
1424 // AArch64 TLB Invalidate by VA, All ASID, EL1
1425 case MISCREG_TLBI_VAAE1_Xt:
1426 case MISCREG_TLBI_VAALE1_Xt:
1427 {
1428 assert64(tc);
1429 scr = readMiscReg(MISCREG_SCR, tc);
1430
1431 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1432 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1433
1434 tlbiOp(tc);
1435 return;
1436 }
1437 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1438 case MISCREG_TLBI_VAAE1IS_Xt:
1439 case MISCREG_TLBI_VAALE1IS_Xt:
1440 {
1441 assert64(tc);
1442 scr = readMiscReg(MISCREG_SCR, tc);
1443
1444 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1445 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1446
1447 tlbiOp.broadcast(tc);
1448 return;
1449 }
1450 // AArch64 TLB Invalidate by Intermediate Physical Address,
1451 // Stage 2, EL1
1452 case MISCREG_TLBI_IPAS2E1_Xt:
1453 case MISCREG_TLBI_IPAS2LE1_Xt:
1454 {
1455 assert64(tc);
1456 scr = readMiscReg(MISCREG_SCR, tc);
1457
1458 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1459 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1460
1461 tlbiOp(tc);
1462 return;
1463 }
1464 // AArch64 TLB Invalidate by Intermediate Physical Address,
1465 // Stage 2, EL1, Inner Shareable
1466 case MISCREG_TLBI_IPAS2E1IS_Xt:
1467 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1468 {
1469 assert64(tc);
1470 scr = readMiscReg(MISCREG_SCR, tc);
1471
1472 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1473 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1474
1475 tlbiOp.broadcast(tc);
1476 return;
1477 }
1478 case MISCREG_ACTLR:
1479 warn("Not doing anything for write of miscreg ACTLR\n");
1480 break;
1481
1482 case MISCREG_PMXEVTYPER_PMCCFILTR:
1483 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1484 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1485 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1486 pmu->setMiscReg(misc_reg, newVal);
1487 break;
1488
1489
1490 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1491 {
1492 HSTR hstrMask = 0;
1493 hstrMask.tjdbx = 1;
1494 newVal &= ~((uint32_t) hstrMask);
1495 break;
1496 }
1497 case MISCREG_HCPTR:
1498 {
1499 // If a CP bit in NSACR is 0 then the corresponding bit in
1500 // HCPTR is RAO/WI. Same applies to NSASEDIS
1501 secure_lookup = haveSecurity &&
1502 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1503 readMiscRegNoEffect(MISCREG_CPSR));
1504 if (!secure_lookup) {
1505 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1506 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1507 newVal = (newVal & ~mask) | (oldValue & mask);
1508 }
1509 break;
1510 }
1511 case MISCREG_HDFAR: // alias for secure DFAR
1512 misc_reg = MISCREG_DFAR_S;
1513 break;
1514 case MISCREG_HIFAR: // alias for secure IFAR
1515 misc_reg = MISCREG_IFAR_S;
1516 break;
1517 case MISCREG_ATS1CPR:
1518 case MISCREG_ATS1CPW:
1519 case MISCREG_ATS1CUR:
1520 case MISCREG_ATS1CUW:
1521 case MISCREG_ATS12NSOPR:
1522 case MISCREG_ATS12NSOPW:
1523 case MISCREG_ATS12NSOUR:
1524 case MISCREG_ATS12NSOUW:
1525 case MISCREG_ATS1HR:
1526 case MISCREG_ATS1HW:
1527 {
1528 Request::Flags flags = 0;
1529 BaseTLB::Mode mode = BaseTLB::Read;
1530 TLB::ArmTranslationType tranType = TLB::NormalTran;
1531 Fault fault;
1532 switch(misc_reg) {
1533 case MISCREG_ATS1CPR:
1534 flags = TLB::MustBeOne;
1535 tranType = TLB::S1CTran;
1536 mode = BaseTLB::Read;
1537 break;
1538 case MISCREG_ATS1CPW:
1539 flags = TLB::MustBeOne;
1540 tranType = TLB::S1CTran;
1541 mode = BaseTLB::Write;
1542 break;
1543 case MISCREG_ATS1CUR:
1544 flags = TLB::MustBeOne | TLB::UserMode;
1545 tranType = TLB::S1CTran;
1546 mode = BaseTLB::Read;
1547 break;
1548 case MISCREG_ATS1CUW:
1549 flags = TLB::MustBeOne | TLB::UserMode;
1550 tranType = TLB::S1CTran;
1551 mode = BaseTLB::Write;
1552 break;
1553 case MISCREG_ATS12NSOPR:
1554 if (!haveSecurity)
1555 panic("Security Extensions required for ATS12NSOPR");
1556 flags = TLB::MustBeOne;
1557 tranType = TLB::S1S2NsTran;
1558 mode = BaseTLB::Read;
1559 break;
1560 case MISCREG_ATS12NSOPW:
1561 if (!haveSecurity)
1562 panic("Security Extensions required for ATS12NSOPW");
1563 flags = TLB::MustBeOne;
1564 tranType = TLB::S1S2NsTran;
1565 mode = BaseTLB::Write;
1566 break;
1567 case MISCREG_ATS12NSOUR:
1568 if (!haveSecurity)
1569 panic("Security Extensions required for ATS12NSOUR");
1570 flags = TLB::MustBeOne | TLB::UserMode;
1571 tranType = TLB::S1S2NsTran;
1572 mode = BaseTLB::Read;
1573 break;
1574 case MISCREG_ATS12NSOUW:
1575 if (!haveSecurity)
1576 panic("Security Extensions required for ATS12NSOUW");
1577 flags = TLB::MustBeOne | TLB::UserMode;
1578 tranType = TLB::S1S2NsTran;
1579 mode = BaseTLB::Write;
1580 break;
1581 case MISCREG_ATS1HR: // only really useful from secure mode.
1582 flags = TLB::MustBeOne;
1583 tranType = TLB::HypMode;
1584 mode = BaseTLB::Read;
1585 break;
1586 case MISCREG_ATS1HW:
1587 flags = TLB::MustBeOne;
1588 tranType = TLB::HypMode;
1589 mode = BaseTLB::Write;
1590 break;
1591 }
1592 // If we're in timing mode then doing the translation in
1593 // functional mode then we're slightly distorting performance
1594 // results obtained from simulations. The translation should be
1595 // done in the same mode the core is running in. NOTE: This
1596 // can't be an atomic translation because that causes problems
1597 // with unexpected atomic snoop requests.
1598 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1599
1600 auto req = std::make_shared<Request>(
1601 0, val, 0, flags, Request::funcMasterId,
1602 tc->pcState().pc(), tc->contextId());
1603
1604 fault = getDTBPtr(tc)->translateFunctional(
1605 req, tc, mode, tranType);
1606
1607 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1608 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1609
1610 MiscReg newVal;
1611 if (fault == NoFault) {
1612 Addr paddr = req->getPaddr();
1613 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1614 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1615 newVal = (paddr & mask(39, 12)) |
1616 (getDTBPtr(tc)->getAttr());
1617 } else {
1618 newVal = (paddr & 0xfffff000) |
1619 (getDTBPtr(tc)->getAttr());
1620 }
1621 DPRINTF(MiscRegs,
1622 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1623 val, newVal);
1624 } else {
1625 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1626 armFault->update(tc);
1627 // Set fault bit and FSR
1628 FSR fsr = armFault->getFsr(tc);
1629
1630 newVal = ((fsr >> 9) & 1) << 11;
1631 if (newVal) {
1632 // LPAE - rearange fault status
1633 newVal |= ((fsr >> 0) & 0x3f) << 1;
1634 } else {
1635 // VMSA - rearange fault status
1636 newVal |= ((fsr >> 0) & 0xf) << 1;
1637 newVal |= ((fsr >> 10) & 0x1) << 5;
1638 newVal |= ((fsr >> 12) & 0x1) << 6;
1639 }
1640 newVal |= 0x1; // F bit
1641 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1642 newVal |= armFault->isStage2() ? 0x200 : 0;
1643 DPRINTF(MiscRegs,
1644 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1645 val, fsr, newVal);
1646 }
1647 setMiscRegNoEffect(MISCREG_PAR, newVal);
1648 return;
1649 }
1650 case MISCREG_TTBCR:
1651 {
1652 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1653 const uint32_t ones = (uint32_t)(-1);
1654 TTBCR ttbcrMask = 0;
1655 TTBCR ttbcrNew = newVal;
1656
1657 // ARM DDI 0406C.b, ARMv7-32
1658 ttbcrMask.n = ones; // T0SZ
1659 if (haveSecurity) {
1660 ttbcrMask.pd0 = ones;
1661 ttbcrMask.pd1 = ones;
1662 }
1663 ttbcrMask.epd0 = ones;
1664 ttbcrMask.irgn0 = ones;
1665 ttbcrMask.orgn0 = ones;
1666 ttbcrMask.sh0 = ones;
1667 ttbcrMask.ps = ones; // T1SZ
1668 ttbcrMask.a1 = ones;
1669 ttbcrMask.epd1 = ones;
1670 ttbcrMask.irgn1 = ones;
1671 ttbcrMask.orgn1 = ones;
1672 ttbcrMask.sh1 = ones;
1673 if (haveLPAE)
1674 ttbcrMask.eae = ones;
1675
1676 if (haveLPAE && ttbcrNew.eae) {
1677 newVal = newVal & ttbcrMask;
1678 } else {
1679 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1680 }
1681 // Invalidate TLB MiscReg
1682 getITBPtr(tc)->invalidateMiscReg();
1683 getDTBPtr(tc)->invalidateMiscReg();
1684 break;
1685 }
1686 case MISCREG_TTBR0:
1687 case MISCREG_TTBR1:
1688 {
1689 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1690 if (haveLPAE) {
1691 if (ttbcr.eae) {
1692 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1693 // ARMv8 AArch32 bit 63-56 only
1694 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1695 newVal = (newVal & (~ttbrMask));
1696 }
1697 }
1698 // Invalidate TLB MiscReg
1699 getITBPtr(tc)->invalidateMiscReg();
1700 getDTBPtr(tc)->invalidateMiscReg();
1701 break;
1702 }
1703 case MISCREG_SCTLR_EL1:
1704 case MISCREG_CONTEXTIDR:
1705 case MISCREG_PRRR:
1706 case MISCREG_NMRR:
1707 case MISCREG_MAIR0:
1708 case MISCREG_MAIR1:
1709 case MISCREG_DACR:
1710 case MISCREG_VTTBR:
1711 case MISCREG_SCR_EL3:
1712 case MISCREG_HCR_EL2:
1713 case MISCREG_TCR_EL1:
1714 case MISCREG_TCR_EL2:
1715 case MISCREG_TCR_EL3:
1716 case MISCREG_SCTLR_EL2:
1717 case MISCREG_SCTLR_EL3:
1718 case MISCREG_HSCTLR:
1719 case MISCREG_TTBR0_EL1:
1720 case MISCREG_TTBR1_EL1:
1721 case MISCREG_TTBR0_EL2:
1722 case MISCREG_TTBR1_EL2:
1723 case MISCREG_TTBR0_EL3:
1724 getITBPtr(tc)->invalidateMiscReg();
1725 getDTBPtr(tc)->invalidateMiscReg();
1726 break;
1727 case MISCREG_NZCV:
1728 {
1729 CPSR cpsr = val;
1730
1731 tc->setCCReg(CCREG_NZ, cpsr.nz);
1732 tc->setCCReg(CCREG_C, cpsr.c);
1733 tc->setCCReg(CCREG_V, cpsr.v);
1734 }
1735 break;
1736 case MISCREG_DAIF:
1737 {
1738 CPSR cpsr = miscRegs[MISCREG_CPSR];
1739 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1740 newVal = cpsr;
1741 misc_reg = MISCREG_CPSR;
1742 }
1743 break;
1744 case MISCREG_SP_EL0:
1745 tc->setIntReg(INTREG_SP0, newVal);
1746 break;
1747 case MISCREG_SP_EL1:
1748 tc->setIntReg(INTREG_SP1, newVal);
1749 break;
1750 case MISCREG_SP_EL2:
1751 tc->setIntReg(INTREG_SP2, newVal);
1752 break;
1753 case MISCREG_SPSEL:
1754 {
1755 CPSR cpsr = miscRegs[MISCREG_CPSR];
1756 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1757 newVal = cpsr;
1758 misc_reg = MISCREG_CPSR;
1759 }
1760 break;
1761 case MISCREG_CURRENTEL:
1762 {
1763 CPSR cpsr = miscRegs[MISCREG_CPSR];
1764 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1765 newVal = cpsr;
1766 misc_reg = MISCREG_CPSR;
1767 }
1768 break;
1769 case MISCREG_AT_S1E1R_Xt:
1770 case MISCREG_AT_S1E1W_Xt:
1771 case MISCREG_AT_S1E0R_Xt:
1772 case MISCREG_AT_S1E0W_Xt:
1773 case MISCREG_AT_S1E2R_Xt:
1774 case MISCREG_AT_S1E2W_Xt:
1775 case MISCREG_AT_S12E1R_Xt:
1776 case MISCREG_AT_S12E1W_Xt:
1777 case MISCREG_AT_S12E0R_Xt:
1778 case MISCREG_AT_S12E0W_Xt:
1779 case MISCREG_AT_S1E3R_Xt:
1780 case MISCREG_AT_S1E3W_Xt:
1781 {
1782 RequestPtr req = std::make_shared<Request>();
1783 Request::Flags flags = 0;
1784 BaseTLB::Mode mode = BaseTLB::Read;
1785 TLB::ArmTranslationType tranType = TLB::NormalTran;
1786 Fault fault;
1787 switch(misc_reg) {
1788 case MISCREG_AT_S1E1R_Xt:
1789 flags = TLB::MustBeOne;
1790 tranType = TLB::S1E1Tran;
1791 mode = BaseTLB::Read;
1792 break;
1793 case MISCREG_AT_S1E1W_Xt:
1794 flags = TLB::MustBeOne;
1795 tranType = TLB::S1E1Tran;
1796 mode = BaseTLB::Write;
1797 break;
1798 case MISCREG_AT_S1E0R_Xt:
1799 flags = TLB::MustBeOne | TLB::UserMode;
1800 tranType = TLB::S1E0Tran;
1801 mode = BaseTLB::Read;
1802 break;
1803 case MISCREG_AT_S1E0W_Xt:
1804 flags = TLB::MustBeOne | TLB::UserMode;
1805 tranType = TLB::S1E0Tran;
1806 mode = BaseTLB::Write;
1807 break;
1808 case MISCREG_AT_S1E2R_Xt:
1809 flags = TLB::MustBeOne;
1810 tranType = TLB::S1E2Tran;
1811 mode = BaseTLB::Read;
1812 break;
1813 case MISCREG_AT_S1E2W_Xt:
1814 flags = TLB::MustBeOne;
1815 tranType = TLB::S1E2Tran;
1816 mode = BaseTLB::Write;
1817 break;
1818 case MISCREG_AT_S12E0R_Xt:
1819 flags = TLB::MustBeOne | TLB::UserMode;
1820 tranType = TLB::S12E0Tran;
1821 mode = BaseTLB::Read;
1822 break;
1823 case MISCREG_AT_S12E0W_Xt:
1824 flags = TLB::MustBeOne | TLB::UserMode;
1825 tranType = TLB::S12E0Tran;
1826 mode = BaseTLB::Write;
1827 break;
1828 case MISCREG_AT_S12E1R_Xt:
1829 flags = TLB::MustBeOne;
1830 tranType = TLB::S12E1Tran;
1831 mode = BaseTLB::Read;
1832 break;
1833 case MISCREG_AT_S12E1W_Xt:
1834 flags = TLB::MustBeOne;
1835 tranType = TLB::S12E1Tran;
1836 mode = BaseTLB::Write;
1837 break;
1838 case MISCREG_AT_S1E3R_Xt:
1839 flags = TLB::MustBeOne;
1840 tranType = TLB::S1E3Tran;
1841 mode = BaseTLB::Read;
1842 break;
1843 case MISCREG_AT_S1E3W_Xt:
1844 flags = TLB::MustBeOne;
1845 tranType = TLB::S1E3Tran;
1846 mode = BaseTLB::Write;
1847 break;
1848 }
1849 // If we're in timing mode then doing the translation in
1850 // functional mode then we're slightly distorting performance
1851 // results obtained from simulations. The translation should be
1852 // done in the same mode the core is running in. NOTE: This
1853 // can't be an atomic translation because that causes problems
1854 // with unexpected atomic snoop requests.
1855 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1856 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1857 tc->pcState().pc());
1858 req->setContext(tc->contextId());
1859 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1860 tranType);
1861
1862 MiscReg newVal;
1863 if (fault == NoFault) {
1864 Addr paddr = req->getPaddr();
1865 uint64_t attr = getDTBPtr(tc)->getAttr();
1866 uint64_t attr1 = attr >> 56;
1867 if (!attr1 || attr1 ==0x44) {
1868 attr |= 0x100;
1869 attr &= ~ uint64_t(0x80);
1870 }
1871 newVal = (paddr & mask(47, 12)) | attr;
1872 DPRINTF(MiscRegs,
1873 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1874 val, newVal);
1875 } else {
1876 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1877 armFault->update(tc);
1878 // Set fault bit and FSR
1879 FSR fsr = armFault->getFsr(tc);
1880
1881 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1882 if (cpsr.width) { // AArch32
1883 newVal = ((fsr >> 9) & 1) << 11;
1884 // rearrange fault status
1885 newVal |= ((fsr >> 0) & 0x3f) << 1;
1886 newVal |= 0x1; // F bit
1887 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1888 newVal |= armFault->isStage2() ? 0x200 : 0;
1889 } else { // AArch64
1890 newVal = 1; // F bit
1891 newVal |= fsr << 1; // FST
1892 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1893 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1894 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1895 newVal |= 1 << 11; // RES1
1896 }
1897 DPRINTF(MiscRegs,
1898 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1899 val, fsr, newVal);
1900 }
1901 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1902 return;
1903 }
1904 case MISCREG_SPSR_EL3:
1905 case MISCREG_SPSR_EL2:
1906 case MISCREG_SPSR_EL1:
1907 // Force bits 23:21 to 0
1908 newVal = val & ~(0x7 << 21);
1909 break;
1910 case MISCREG_L2CTLR:
1911 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1912 miscRegName[misc_reg], uint32_t(val));
1913 break;
1914
1915 // Generic Timer registers
1916 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1917 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1918 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1919 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1920 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1921 break;
1922 }
1923 }
1924 setMiscRegNoEffect(misc_reg, newVal);
1925}
1926
1927BaseISADevice &
1928ISA::getGenericTimer(ThreadContext *tc)
1929{
1930 // We only need to create an ISA interface the first time we try
1931 // to access the timer.
1932 if (timer)
1933 return *timer.get();
1934
1935 assert(system);
1936 GenericTimer *generic_timer(system->getGenericTimer());
1937 if (!generic_timer) {
1938 panic("Trying to get a generic timer from a system that hasn't "
1939 "been configured to use a generic timer.\n");
1940 }
1941
1942 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1943 return *timer.get();
1944}
1945
1946}
1947
1948ArmISA::ISA *
1949ArmISAParams::create()
1950{
1951 return new ArmISA::ISA(this);
1952}