1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * When two mapping registers are given, they are the 32b lower and
62 * upper halves, respectively, of the 64b register being mapped.
63 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
64 */
65void
66ISA::initializeMiscRegMetadata()
67{
68 InitReg(MISCREG_ACTLR_EL1).mapsTo(MISCREG_ACTLR_NS);
69 InitReg(MISCREG_AFSR0_EL1).mapsTo(MISCREG_ADFSR_NS);
70 InitReg(MISCREG_AFSR1_EL1).mapsTo(MISCREG_AIFSR_NS);
71 InitReg(MISCREG_AMAIR_EL1).mapsTo(MISCREG_AMAIR0_NS,
72 MISCREG_AMAIR1_NS);
73 InitReg(MISCREG_CONTEXTIDR_EL1).mapsTo(MISCREG_CONTEXTIDR_NS);
74 InitReg(MISCREG_CPACR_EL1).mapsTo(MISCREG_CPACR);
75 InitReg(MISCREG_CSSELR_EL1).mapsTo(MISCREG_CSSELR_NS);
76 InitReg(MISCREG_DACR32_EL2).mapsTo(MISCREG_DACR_NS);
77 InitReg(MISCREG_FAR_EL1).mapsTo(MISCREG_DFAR_NS,
78 MISCREG_IFAR_NS);
79 // ESR_EL1 -> DFSR
80 InitReg(MISCREG_HACR_EL2).mapsTo(MISCREG_HACR);
81 InitReg(MISCREG_ACTLR_EL2).mapsTo(MISCREG_HACTLR);
82 InitReg(MISCREG_AFSR0_EL2).mapsTo(MISCREG_HADFSR);
83 InitReg(MISCREG_AFSR1_EL2).mapsTo(MISCREG_HAIFSR);
84 InitReg(MISCREG_AMAIR_EL2).mapsTo(MISCREG_HAMAIR0,
85 MISCREG_HAMAIR1);
86 InitReg(MISCREG_CPTR_EL2).mapsTo(MISCREG_HCPTR);
87 InitReg(MISCREG_HCR_EL2).mapsTo(MISCREG_HCR /*,
88 MISCREG_HCR2*/);
89 InitReg(MISCREG_MDCR_EL2).mapsTo(MISCREG_HDCR);
90 InitReg(MISCREG_FAR_EL2).mapsTo(MISCREG_HDFAR,
91 MISCREG_HIFAR);
92 InitReg(MISCREG_MAIR_EL2).mapsTo(MISCREG_HMAIR0,
93 MISCREG_HMAIR1);
94 InitReg(MISCREG_HPFAR_EL2).mapsTo(MISCREG_HPFAR);
95 InitReg(MISCREG_SCTLR_EL2).mapsTo(MISCREG_HSCTLR);
96 InitReg(MISCREG_ESR_EL2).mapsTo(MISCREG_HSR);
97 InitReg(MISCREG_HSTR_EL2).mapsTo(MISCREG_HSTR);
98 InitReg(MISCREG_TCR_EL2).mapsTo(MISCREG_HTCR);
99 InitReg(MISCREG_TPIDR_EL2).mapsTo(MISCREG_HTPIDR);
100 InitReg(MISCREG_TTBR0_EL2).mapsTo(MISCREG_HTTBR);
101 InitReg(MISCREG_VBAR_EL2).mapsTo(MISCREG_HVBAR);
102 InitReg(MISCREG_IFSR32_EL2).mapsTo(MISCREG_IFSR_NS);
103 InitReg(MISCREG_MAIR_EL1).mapsTo(MISCREG_PRRR_NS,
104 MISCREG_NMRR_NS);
105 InitReg(MISCREG_PAR_EL1).mapsTo(MISCREG_PAR_NS);
106 // RMR_EL1 -> RMR
107 // RMR_EL2 -> HRMR
108 InitReg(MISCREG_SCTLR_EL1).mapsTo(MISCREG_SCTLR_NS);
109 InitReg(MISCREG_SDER32_EL3).mapsTo(MISCREG_SDER);
110 InitReg(MISCREG_TPIDR_EL1).mapsTo(MISCREG_TPIDRPRW_NS);
111 InitReg(MISCREG_TPIDRRO_EL0).mapsTo(MISCREG_TPIDRURO_NS);
112 InitReg(MISCREG_TPIDR_EL0).mapsTo(MISCREG_TPIDRURW_NS);
113 InitReg(MISCREG_TCR_EL1).mapsTo(MISCREG_TTBCR_NS);
114 InitReg(MISCREG_TTBR0_EL1).mapsTo(MISCREG_TTBR0_NS);
115 InitReg(MISCREG_TTBR1_EL1).mapsTo(MISCREG_TTBR1_NS);
116 InitReg(MISCREG_VBAR_EL1).mapsTo(MISCREG_VBAR_NS);
117 InitReg(MISCREG_VMPIDR_EL2).mapsTo(MISCREG_VMPIDR);
118 InitReg(MISCREG_VPIDR_EL2).mapsTo(MISCREG_VPIDR);
119 InitReg(MISCREG_VTCR_EL2).mapsTo(MISCREG_VTCR);
120 InitReg(MISCREG_VTTBR_EL2).mapsTo(MISCREG_VTTBR);
121 InitReg(MISCREG_CNTFRQ_EL0).mapsTo(MISCREG_CNTFRQ);
122 InitReg(MISCREG_CNTHCTL_EL2).mapsTo(MISCREG_CNTHCTL);
123 InitReg(MISCREG_CNTHP_CTL_EL2).mapsTo(MISCREG_CNTHP_CTL);
124 InitReg(MISCREG_CNTHP_CVAL_EL2).mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
125 InitReg(MISCREG_CNTHP_TVAL_EL2).mapsTo(MISCREG_CNTHP_TVAL);
126 InitReg(MISCREG_CNTKCTL_EL1).mapsTo(MISCREG_CNTKCTL);
127 InitReg(MISCREG_CNTP_CTL_EL0).mapsTo(MISCREG_CNTP_CTL_NS);
128 InitReg(MISCREG_CNTP_CVAL_EL0).mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
129 InitReg(MISCREG_CNTP_TVAL_EL0).mapsTo(MISCREG_CNTP_TVAL_NS);
130 InitReg(MISCREG_CNTPCT_EL0).mapsTo(MISCREG_CNTPCT); /* 64b */
131 InitReg(MISCREG_CNTV_CTL_EL0).mapsTo(MISCREG_CNTV_CTL);
132 InitReg(MISCREG_CNTV_CVAL_EL0).mapsTo(MISCREG_CNTV_CVAL); /* 64b */
133 InitReg(MISCREG_CNTV_TVAL_EL0).mapsTo(MISCREG_CNTV_TVAL);
134 InitReg(MISCREG_CNTVCT_EL0).mapsTo(MISCREG_CNTVCT); /* 64b */
135 InitReg(MISCREG_CNTVOFF_EL2).mapsTo(MISCREG_CNTVOFF); /* 64b */
136 InitReg(MISCREG_DBGAUTHSTATUS_EL1).mapsTo(MISCREG_DBGAUTHSTATUS);
137 InitReg(MISCREG_DBGBCR0_EL1).mapsTo(MISCREG_DBGBCR0);
138 InitReg(MISCREG_DBGBCR1_EL1).mapsTo(MISCREG_DBGBCR1);
139 InitReg(MISCREG_DBGBCR2_EL1).mapsTo(MISCREG_DBGBCR2);
140 InitReg(MISCREG_DBGBCR3_EL1).mapsTo(MISCREG_DBGBCR3);
141 InitReg(MISCREG_DBGBCR4_EL1).mapsTo(MISCREG_DBGBCR4);
142 InitReg(MISCREG_DBGBCR5_EL1).mapsTo(MISCREG_DBGBCR5);
143 InitReg(MISCREG_DBGBVR0_EL1).mapsTo(MISCREG_DBGBVR0 /*,
144 MISCREG_DBGBXVR0 */);
145 InitReg(MISCREG_DBGBVR1_EL1).mapsTo(MISCREG_DBGBVR1 /*,
146 MISCREG_DBGBXVR1 */);
147 InitReg(MISCREG_DBGBVR2_EL1).mapsTo(MISCREG_DBGBVR2 /*,
148 MISCREG_DBGBXVR2 */);
149 InitReg(MISCREG_DBGBVR3_EL1).mapsTo(MISCREG_DBGBVR3 /*,
150 MISCREG_DBGBXVR3 */);
151 InitReg(MISCREG_DBGBVR4_EL1).mapsTo(MISCREG_DBGBVR4 /*,
152 MISCREG_DBGBXVR4 */);
153 InitReg(MISCREG_DBGBVR5_EL1).mapsTo(MISCREG_DBGBVR5 /*,
154 MISCREG_DBGBXVR5 */);
155 InitReg(MISCREG_DBGCLAIMSET_EL1).mapsTo(MISCREG_DBGCLAIMSET);
156 InitReg(MISCREG_DBGCLAIMCLR_EL1).mapsTo(MISCREG_DBGCLAIMCLR);
157 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
158 // DBGDTRRX_EL0 -> DBGDTRRXint
159 // DBGDTRTX_EL0 -> DBGDTRRXint
160 InitReg(MISCREG_DBGPRCR_EL1).mapsTo(MISCREG_DBGPRCR);
161 InitReg(MISCREG_DBGVCR32_EL2).mapsTo(MISCREG_DBGVCR);
162 InitReg(MISCREG_DBGWCR0_EL1).mapsTo(MISCREG_DBGWCR0);
163 InitReg(MISCREG_DBGWCR1_EL1).mapsTo(MISCREG_DBGWCR1);
164 InitReg(MISCREG_DBGWCR2_EL1).mapsTo(MISCREG_DBGWCR2);
165 InitReg(MISCREG_DBGWCR3_EL1).mapsTo(MISCREG_DBGWCR3);
166 InitReg(MISCREG_DBGWVR0_EL1).mapsTo(MISCREG_DBGWVR0);
167 InitReg(MISCREG_DBGWVR1_EL1).mapsTo(MISCREG_DBGWVR1);
168 InitReg(MISCREG_DBGWVR2_EL1).mapsTo(MISCREG_DBGWVR2);
169 InitReg(MISCREG_DBGWVR3_EL1).mapsTo(MISCREG_DBGWVR3);
170 InitReg(MISCREG_ID_DFR0_EL1).mapsTo(MISCREG_ID_DFR0);
171 InitReg(MISCREG_MDCCSR_EL0).mapsTo(MISCREG_DBGDSCRint);
172 InitReg(MISCREG_MDRAR_EL1).mapsTo(MISCREG_DBGDRAR);
173 InitReg(MISCREG_MDSCR_EL1).mapsTo(MISCREG_DBGDSCRext);
174 InitReg(MISCREG_OSDLR_EL1).mapsTo(MISCREG_DBGOSDLR);
175 InitReg(MISCREG_OSDTRRX_EL1).mapsTo(MISCREG_DBGDTRRXext);
176 InitReg(MISCREG_OSDTRTX_EL1).mapsTo(MISCREG_DBGDTRTXext);
177 InitReg(MISCREG_OSECCR_EL1).mapsTo(MISCREG_DBGOSECCR);
178 InitReg(MISCREG_OSLAR_EL1).mapsTo(MISCREG_DBGOSLAR);
179 InitReg(MISCREG_OSLSR_EL1).mapsTo(MISCREG_DBGOSLSR);
180 InitReg(MISCREG_PMCCNTR_EL0).mapsTo(MISCREG_PMCCNTR);
181 InitReg(MISCREG_PMCEID0_EL0).mapsTo(MISCREG_PMCEID0);
182 InitReg(MISCREG_PMCEID1_EL0).mapsTo(MISCREG_PMCEID1);
183 InitReg(MISCREG_PMCNTENSET_EL0).mapsTo(MISCREG_PMCNTENSET);
184 InitReg(MISCREG_PMCNTENCLR_EL0).mapsTo(MISCREG_PMCNTENCLR);
185 InitReg(MISCREG_PMCR_EL0).mapsTo(MISCREG_PMCR);
186/* InitReg(MISCREG_PMEVCNTR0_EL0).mapsTo(MISCREG_PMEVCNTR0);
187 InitReg(MISCREG_PMEVCNTR1_EL0).mapsTo(MISCREG_PMEVCNTR1);
188 InitReg(MISCREG_PMEVCNTR2_EL0).mapsTo(MISCREG_PMEVCNTR2);
189 InitReg(MISCREG_PMEVCNTR3_EL0).mapsTo(MISCREG_PMEVCNTR3);
190 InitReg(MISCREG_PMEVCNTR4_EL0).mapsTo(MISCREG_PMEVCNTR4);
191 InitReg(MISCREG_PMEVCNTR5_EL0).mapsTo(MISCREG_PMEVCNTR5);
192 InitReg(MISCREG_PMEVTYPER0_EL0).mapsTo(MISCREG_PMEVTYPER0);
193 InitReg(MISCREG_PMEVTYPER1_EL0).mapsTo(MISCREG_PMEVTYPER1);
194 InitReg(MISCREG_PMEVTYPER2_EL0).mapsTo(MISCREG_PMEVTYPER2);
195 InitReg(MISCREG_PMEVTYPER3_EL0).mapsTo(MISCREG_PMEVTYPER3);
196 InitReg(MISCREG_PMEVTYPER4_EL0).mapsTo(MISCREG_PMEVTYPER4);
197 InitReg(MISCREG_PMEVTYPER5_EL0).mapsTo(MISCREG_PMEVTYPER5); */
198 InitReg(MISCREG_PMINTENCLR_EL1).mapsTo(MISCREG_PMINTENCLR);
199 InitReg(MISCREG_PMINTENSET_EL1).mapsTo(MISCREG_PMINTENSET);
200// InitReg(MISCREG_PMOVSCLR_EL0).mapsTo(MISCREG_PMOVSCLR);
201 InitReg(MISCREG_PMOVSSET_EL0).mapsTo(MISCREG_PMOVSSET);
202 InitReg(MISCREG_PMSELR_EL0).mapsTo(MISCREG_PMSELR);
203 InitReg(MISCREG_PMSWINC_EL0).mapsTo(MISCREG_PMSWINC);
204 InitReg(MISCREG_PMUSERENR_EL0).mapsTo(MISCREG_PMUSERENR);
205 InitReg(MISCREG_PMXEVCNTR_EL0).mapsTo(MISCREG_PMXEVCNTR);
206 InitReg(MISCREG_PMXEVTYPER_EL0).mapsTo(MISCREG_PMXEVTYPER);
207
208 // from ARM DDI 0487A.i, template text
209 // "AArch64 System register ___ can be mapped to
210 // AArch32 System register ___, but this is not
211 // architecturally mandated."
212 InitReg(MISCREG_SCR_EL3).mapsTo(MISCREG_SCR); // D7-2005
213 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
214 InitReg(MISCREG_SPSR_EL1).mapsTo(MISCREG_SPSR_SVC); // C5.2.17 SPSR_EL1
215 InitReg(MISCREG_SPSR_EL2).mapsTo(MISCREG_SPSR_HYP); // C5.2.18 SPSR_EL2
216 InitReg(MISCREG_SPSR_EL3).mapsTo(MISCREG_SPSR_MON); // C5.2.19 SPSR_EL3
217}
218
219ISA::ISA(Params *p)
220 : SimObject(p),
221 system(NULL),
222 _decoderFlavour(p->decoderFlavour),
223 _vecRegRenameMode(p->vecRegRenameMode),
224 pmu(p->pmu),
225 lookUpMiscReg(NUM_MISCREGS)
226{
227 miscRegs[MISCREG_SCTLR_RST] = 0;
228
229 // Hook up a dummy device if we haven't been configured with a
230 // real PMU. By using a dummy device, we don't need to check that
231 // the PMU exist every time we try to access a PMU register.
232 if (!pmu)
233 pmu = &dummyDevice;
234
235 // Give all ISA devices a pointer to this ISA
236 pmu->setISA(this);
237
238 system = dynamic_cast<ArmSystem *>(p->system);
239
240 // Cache system-level properties
241 if (FullSystem && system) {
242 highestELIs64 = system->highestELIs64();
243 haveSecurity = system->haveSecurity();
244 haveLPAE = system->haveLPAE();
245 haveVirtualization = system->haveVirtualization();
246 haveLargeAsid64 = system->haveLargeAsid64();
247 physAddrRange64 = system->physAddrRange64();
248 } else {
249 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
250 haveSecurity = haveLPAE = haveVirtualization = false;
251 haveLargeAsid64 = false;
252 physAddrRange64 = 32; // dummy value
253 }
254
255 initializeMiscRegMetadata();
256 preUnflattenMiscReg();
257
258 clear();
259}
260
261const ArmISAParams *
262ISA::params() const
263{
264 return dynamic_cast<const Params *>(_params);
265}
266
267void
268ISA::clear()
269{
270 const Params *p(params());
271
272 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
273 memset(miscRegs, 0, sizeof(miscRegs));
274
275 // Initialize configurable default values
276 miscRegs[MISCREG_MIDR] = p->midr;
277 miscRegs[MISCREG_MIDR_EL1] = p->midr;
278 miscRegs[MISCREG_VPIDR] = p->midr;
279
280 if (FullSystem && system->highestELIs64()) {
281 // Initialize AArch64 state
282 clear64(p);
283 return;
284 }
285
286 // Initialize AArch32 state...
287
288 CPSR cpsr = 0;
289 cpsr.mode = MODE_USER;
290 miscRegs[MISCREG_CPSR] = cpsr;
291 updateRegMap(cpsr);
292
293 SCTLR sctlr = 0;
294 sctlr.te = (bool) sctlr_rst.te;
295 sctlr.nmfi = (bool) sctlr_rst.nmfi;
296 sctlr.v = (bool) sctlr_rst.v;
297 sctlr.u = 1;
298 sctlr.xp = 1;
299 sctlr.rao2 = 1;
300 sctlr.rao3 = 1;
301 sctlr.rao4 = 0xf; // SCTLR[6:3]
302 sctlr.uci = 1;
303 sctlr.dze = 1;
304 miscRegs[MISCREG_SCTLR_NS] = sctlr;
305 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
306 miscRegs[MISCREG_HCPTR] = 0;
307
308 // Start with an event in the mailbox
309 miscRegs[MISCREG_SEV_MAILBOX] = 1;
310
311 // Separate Instruction and Data TLBs
312 miscRegs[MISCREG_TLBTR] = 1;
313
314 MVFR0 mvfr0 = 0;
315 mvfr0.advSimdRegisters = 2;
316 mvfr0.singlePrecision = 2;
317 mvfr0.doublePrecision = 2;
318 mvfr0.vfpExceptionTrapping = 0;
319 mvfr0.divide = 1;
320 mvfr0.squareRoot = 1;
321 mvfr0.shortVectors = 1;
322 mvfr0.roundingModes = 1;
323 miscRegs[MISCREG_MVFR0] = mvfr0;
324
325 MVFR1 mvfr1 = 0;
326 mvfr1.flushToZero = 1;
327 mvfr1.defaultNaN = 1;
328 mvfr1.advSimdLoadStore = 1;
329 mvfr1.advSimdInteger = 1;
330 mvfr1.advSimdSinglePrecision = 1;
331 mvfr1.advSimdHalfPrecision = 1;
332 mvfr1.vfpHalfPrecision = 1;
333 miscRegs[MISCREG_MVFR1] = mvfr1;
334
335 // Reset values of PRRR and NMRR are implementation dependent
336
337 // @todo: PRRR and NMRR in secure state?
338 miscRegs[MISCREG_PRRR_NS] =
339 (1 << 19) | // 19
340 (0 << 18) | // 18
341 (0 << 17) | // 17
342 (1 << 16) | // 16
343 (2 << 14) | // 15:14
344 (0 << 12) | // 13:12
345 (2 << 10) | // 11:10
346 (2 << 8) | // 9:8
347 (2 << 6) | // 7:6
348 (2 << 4) | // 5:4
349 (1 << 2) | // 3:2
350 0; // 1:0
351 miscRegs[MISCREG_NMRR_NS] =
352 (1 << 30) | // 31:30
353 (0 << 26) | // 27:26
354 (0 << 24) | // 25:24
355 (3 << 22) | // 23:22
356 (2 << 20) | // 21:20
357 (0 << 18) | // 19:18
358 (0 << 16) | // 17:16
359 (1 << 14) | // 15:14
360 (0 << 12) | // 13:12
361 (2 << 10) | // 11:10
362 (0 << 8) | // 9:8
363 (3 << 6) | // 7:6
364 (2 << 4) | // 5:4
365 (0 << 2) | // 3:2
366 0; // 1:0
367
368 miscRegs[MISCREG_CPACR] = 0;
369
370 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
371 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
372 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
373 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
374
375 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
376 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
377 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
378 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
379 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
380 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
381
382 miscRegs[MISCREG_FPSID] = p->fpsid;
383
384 if (haveLPAE) {
385 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
386 ttbcr.eae = 0;
387 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
388 // Enforce consistency with system-level settings
389 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
390 }
391
392 if (haveSecurity) {
393 miscRegs[MISCREG_SCTLR_S] = sctlr;
394 miscRegs[MISCREG_SCR] = 0;
395 miscRegs[MISCREG_VBAR_S] = 0;
396 } else {
397 // we're always non-secure
398 miscRegs[MISCREG_SCR] = 1;
399 }
400
401 //XXX We need to initialize the rest of the state.
402}
403
404void
405ISA::clear64(const ArmISAParams *p)
406{
407 CPSR cpsr = 0;
408 Addr rvbar = system->resetAddr64();
409 switch (system->highestEL()) {
410 // Set initial EL to highest implemented EL using associated stack
411 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
412 // value
413 case EL3:
414 cpsr.mode = MODE_EL3H;
415 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
416 break;
417 case EL2:
418 cpsr.mode = MODE_EL2H;
419 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
420 break;
421 case EL1:
422 cpsr.mode = MODE_EL1H;
423 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
424 break;
425 default:
426 panic("Invalid highest implemented exception level");
427 break;
428 }
429
430 // Initialize rest of CPSR
431 cpsr.daif = 0xf; // Mask all interrupts
432 cpsr.ss = 0;
433 cpsr.il = 0;
434 miscRegs[MISCREG_CPSR] = cpsr;
435 updateRegMap(cpsr);
436
437 // Initialize other control registers
438 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
439 if (haveSecurity) {
440 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
441 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
442 } else if (haveVirtualization) {
443 // also MISCREG_SCTLR_EL2 (by mapping)
444 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
445 } else {
446 // also MISCREG_SCTLR_EL1 (by mapping)
447 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
448 // Always non-secure
449 miscRegs[MISCREG_SCR_EL3] = 1;
450 }
451
452 // Initialize configurable id registers
453 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
454 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
455 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
456 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
457 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
458
459 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
460 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
461 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
462 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
463 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
464
465 miscRegs[MISCREG_ID_DFR0_EL1] =
466 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
467
468 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
469
470 // Enforce consistency with system-level settings...
471
472 // EL3
473 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
474 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
475 haveSecurity ? 0x2 : 0x0);
476 // EL2
477 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
478 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
479 haveVirtualization ? 0x2 : 0x0);
480 // Large ASID support
481 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
482 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
483 haveLargeAsid64 ? 0x2 : 0x0);
484 // Physical address size
485 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
486 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
487 encodePhysAddrRange64(physAddrRange64));
488}
489
490MiscReg
491ISA::readMiscRegNoEffect(int misc_reg) const
492{
493 assert(misc_reg < NumMiscRegs);
494
495 auto regs = getMiscIndices(misc_reg);
496 int lower = regs.first, upper = regs.second;
497 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
498 |(miscRegs[upper] << 32));
499}
500
501
502MiscReg
503ISA::readMiscReg(int misc_reg, ThreadContext *tc)
504{
505 CPSR cpsr = 0;
506 PCState pc = 0;
507 SCR scr = 0;
508
509 if (misc_reg == MISCREG_CPSR) {
510 cpsr = miscRegs[misc_reg];
511 pc = tc->pcState();
512 cpsr.j = pc.jazelle() ? 1 : 0;
513 cpsr.t = pc.thumb() ? 1 : 0;
514 return cpsr;
515 }
516
517#ifndef NDEBUG
518 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
519 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
520 warn("Unimplemented system register %s read.\n",
521 miscRegName[misc_reg]);
522 else
523 panic("Unimplemented system register %s read.\n",
524 miscRegName[misc_reg]);
525 }
526#endif
527
528 switch (unflattenMiscReg(misc_reg)) {
529 case MISCREG_HCR:
530 {
531 if (!haveVirtualization)
532 return 0;
533 else
534 return readMiscRegNoEffect(MISCREG_HCR);
535 }
536 case MISCREG_CPACR:
537 {
538 const uint32_t ones = (uint32_t)(-1);
539 CPACR cpacrMask = 0;
540 // Only cp10, cp11, and ase are implemented, nothing else should
541 // be readable? (straight copy from the write code)
542 cpacrMask.cp10 = ones;
543 cpacrMask.cp11 = ones;
544 cpacrMask.asedis = ones;
545
546 // Security Extensions may limit the readability of CPACR
547 if (haveSecurity) {
548 scr = readMiscRegNoEffect(MISCREG_SCR);
549 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
550 if (scr.ns && (cpsr.mode != MODE_MON)) {
551 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
552 // NB: Skipping the full loop, here
553 if (!nsacr.cp10) cpacrMask.cp10 = 0;
554 if (!nsacr.cp11) cpacrMask.cp11 = 0;
555 }
556 }
557 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
558 val &= cpacrMask;
559 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
560 miscRegName[misc_reg], val);
561 return val;
562 }
563 case MISCREG_MPIDR:
564 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
565 scr = readMiscRegNoEffect(MISCREG_SCR);
566 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
567 return getMPIDR(system, tc);
568 } else {
569 return readMiscReg(MISCREG_VMPIDR, tc);
570 }
571 break;
572 case MISCREG_MPIDR_EL1:
573 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
574 return getMPIDR(system, tc) & 0xffffffff;
575 case MISCREG_VMPIDR:
576 // top bit defined as RES1
577 return readMiscRegNoEffect(misc_reg) | 0x80000000;
578 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
579 case MISCREG_REVIDR: // not implemented, so alias MIDR
580 case MISCREG_MIDR:
581 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
582 scr = readMiscRegNoEffect(MISCREG_SCR);
583 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
584 return readMiscRegNoEffect(misc_reg);
585 } else {
586 return readMiscRegNoEffect(MISCREG_VPIDR);
587 }
588 break;
589 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
590 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
591 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
592 case MISCREG_AIDR: // AUX ID set to 0
593 case MISCREG_TCMTR: // No TCM's
594 return 0;
595
596 case MISCREG_CLIDR:
597 warn_once("The clidr register always reports 0 caches.\n");
598 warn_once("clidr LoUIS field of 0b001 to match current "
599 "ARM implementations.\n");
600 return 0x00200000;
601 case MISCREG_CCSIDR:
602 warn_once("The ccsidr register isn't implemented and "
603 "always reads as 0.\n");
604 break;
605 case MISCREG_CTR: // AArch32, ARMv7, top bit set
606 case MISCREG_CTR_EL0: // AArch64
607 {
608 //all caches have the same line size in gem5
609 //4 byte words in ARM
610 unsigned lineSizeWords =
611 tc->getSystemPtr()->cacheLineSize() / 4;
612 unsigned log2LineSizeWords = 0;
613
614 while (lineSizeWords >>= 1) {
615 ++log2LineSizeWords;
616 }
617
618 CTR ctr = 0;
619 //log2 of minimun i-cache line size (words)
620 ctr.iCacheLineSize = log2LineSizeWords;
621 //b11 - gem5 uses pipt
622 ctr.l1IndexPolicy = 0x3;
623 //log2 of minimum d-cache line size (words)
624 ctr.dCacheLineSize = log2LineSizeWords;
625 //log2 of max reservation size (words)
626 ctr.erg = log2LineSizeWords;
627 //log2 of max writeback size (words)
628 ctr.cwg = log2LineSizeWords;
629 //b100 - gem5 format is ARMv7
630 ctr.format = 0x4;
631
632 return ctr;
633 }
634 case MISCREG_ACTLR:
635 warn("Not doing anything for miscreg ACTLR\n");
636 break;
637
638 case MISCREG_PMXEVTYPER_PMCCFILTR:
639 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
640 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
641 case MISCREG_PMCR ... MISCREG_PMOVSSET:
642 return pmu->readMiscReg(misc_reg);
643
644 case MISCREG_CPSR_Q:
645 panic("shouldn't be reading this register seperately\n");
646 case MISCREG_FPSCR_QC:
647 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
648 case MISCREG_FPSCR_EXC:
649 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
650 case MISCREG_FPSR:
651 {
652 const uint32_t ones = (uint32_t)(-1);
653 FPSCR fpscrMask = 0;
654 fpscrMask.ioc = ones;
655 fpscrMask.dzc = ones;
656 fpscrMask.ofc = ones;
657 fpscrMask.ufc = ones;
658 fpscrMask.ixc = ones;
659 fpscrMask.idc = ones;
660 fpscrMask.qc = ones;
661 fpscrMask.v = ones;
662 fpscrMask.c = ones;
663 fpscrMask.z = ones;
664 fpscrMask.n = ones;
665 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
666 }
667 case MISCREG_FPCR:
668 {
669 const uint32_t ones = (uint32_t)(-1);
670 FPSCR fpscrMask = 0;
671 fpscrMask.ioe = ones;
672 fpscrMask.dze = ones;
673 fpscrMask.ofe = ones;
674 fpscrMask.ufe = ones;
675 fpscrMask.ixe = ones;
676 fpscrMask.ide = ones;
677 fpscrMask.len = ones;
678 fpscrMask.stride = ones;
679 fpscrMask.rMode = ones;
680 fpscrMask.fz = ones;
681 fpscrMask.dn = ones;
682 fpscrMask.ahp = ones;
683 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
684 }
685 case MISCREG_NZCV:
686 {
687 CPSR cpsr = 0;
688 cpsr.nz = tc->readCCReg(CCREG_NZ);
689 cpsr.c = tc->readCCReg(CCREG_C);
690 cpsr.v = tc->readCCReg(CCREG_V);
691 return cpsr;
692 }
693 case MISCREG_DAIF:
694 {
695 CPSR cpsr = 0;
696 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
697 return cpsr;
698 }
699 case MISCREG_SP_EL0:
700 {
701 return tc->readIntReg(INTREG_SP0);
702 }
703 case MISCREG_SP_EL1:
704 {
705 return tc->readIntReg(INTREG_SP1);
706 }
707 case MISCREG_SP_EL2:
708 {
709 return tc->readIntReg(INTREG_SP2);
710 }
711 case MISCREG_SPSEL:
712 {
713 return miscRegs[MISCREG_CPSR] & 0x1;
714 }
715 case MISCREG_CURRENTEL:
716 {
717 return miscRegs[MISCREG_CPSR] & 0xc;
718 }
719 case MISCREG_L2CTLR:
720 {
721 // mostly unimplemented, just set NumCPUs field from sim and return
722 L2CTLR l2ctlr = 0;
723 // b00:1CPU to b11:4CPUs
724 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
725 return l2ctlr;
726 }
727 case MISCREG_DBGDIDR:
728 /* For now just implement the version number.
729 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
730 */
731 return 0x5 << 16;
732 case MISCREG_DBGDSCRint:
733 return 0;
734 case MISCREG_ISR:
735 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
736 readMiscRegNoEffect(MISCREG_HCR),
737 readMiscRegNoEffect(MISCREG_CPSR),
738 readMiscRegNoEffect(MISCREG_SCR));
739 case MISCREG_ISR_EL1:
740 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
741 readMiscRegNoEffect(MISCREG_HCR_EL2),
742 readMiscRegNoEffect(MISCREG_CPSR),
743 readMiscRegNoEffect(MISCREG_SCR_EL3));
744 case MISCREG_DCZID_EL0:
745 return 0x04; // DC ZVA clear 64-byte chunks
746 case MISCREG_HCPTR:
747 {
748 MiscReg val = readMiscRegNoEffect(misc_reg);
749 // The trap bit associated with CP14 is defined as RAZ
750 val &= ~(1 << 14);
751 // If a CP bit in NSACR is 0 then the corresponding bit in
752 // HCPTR is RAO/WI
753 bool secure_lookup = haveSecurity &&
754 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
755 readMiscRegNoEffect(MISCREG_CPSR));
756 if (!secure_lookup) {
757 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
758 val |= (mask ^ 0x7FFF) & 0xBFFF;
759 }
760 // Set the bits for unimplemented coprocessors to RAO/WI
761 val |= 0x33FF;
762 return (val);
763 }
764 case MISCREG_HDFAR: // alias for secure DFAR
765 return readMiscRegNoEffect(MISCREG_DFAR_S);
766 case MISCREG_HIFAR: // alias for secure IFAR
767 return readMiscRegNoEffect(MISCREG_IFAR_S);
768 case MISCREG_HVBAR: // bottom bits reserved
769 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
770 case MISCREG_SCTLR:
771 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
772 case MISCREG_SCTLR_EL1:
773 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
774 case MISCREG_SCTLR_EL2:
775 case MISCREG_SCTLR_EL3:
776 case MISCREG_HSCTLR:
777 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
778
779 case MISCREG_ID_PFR0:
780 // !ThumbEE | !Jazelle | Thumb | ARM
781 return 0x00000031;
782 case MISCREG_ID_PFR1:
783 { // Timer | Virti | !M Profile | TrustZone | ARMv4
784 bool haveTimer = (system->getGenericTimer() != NULL);
785 return 0x00000001
786 | (haveSecurity ? 0x00000010 : 0x0)
787 | (haveVirtualization ? 0x00001000 : 0x0)
788 | (haveTimer ? 0x00010000 : 0x0);
789 }
790 case MISCREG_ID_AA64PFR0_EL1:
791 return 0x0000000000000002 // AArch{64,32} supported at EL0
792 | 0x0000000000000020 // EL1
793 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
794 | (haveSecurity ? 0x0000000000002000 : 0); // EL3
795 case MISCREG_ID_AA64PFR1_EL1:
796 return 0; // bits [63:0] RES0 (reserved for future use)
797
798 // Generic Timer registers
799 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
800 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
801 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
802 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
803 return getGenericTimer(tc).readMiscReg(misc_reg);
804
805 default:
806 break;
807
808 }
809 return readMiscRegNoEffect(misc_reg);
810}
811
812void
813ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
814{
815 assert(misc_reg < NumMiscRegs);
816
817 auto regs = getMiscIndices(misc_reg);
818 int lower = regs.first, upper = regs.second;
819 if (upper > 0) {
820 miscRegs[lower] = bits(val, 31, 0);
821 miscRegs[upper] = bits(val, 63, 32);
822 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
823 misc_reg, lower, upper, val);
824 } else {
825 miscRegs[lower] = val;
826 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
827 misc_reg, lower, val);
828 }
829}
830
831namespace {
832
833template<typename T>
834TLB *
835getITBPtr(T *tc)
836{
837 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
838 assert(tlb);
839 return tlb;
840}
841
842template<typename T>
843TLB *
844getDTBPtr(T *tc)
845{
846 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
847 assert(tlb);
848 return tlb;
849}
850
851} // anonymous namespace
852
853void
854ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
855{
856
857 MiscReg newVal = val;
858 int x;
859 bool secure_lookup;
860 bool hyp;
861 System *sys;
862 ThreadContext *oc;
863 uint8_t target_el;
864 uint16_t asid;
865 SCR scr;
866
867 if (misc_reg == MISCREG_CPSR) {
868 updateRegMap(val);
869
870
871 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
872 int old_mode = old_cpsr.mode;
873 CPSR cpsr = val;
874 if (old_mode != cpsr.mode) {
875 getITBPtr(tc)->invalidateMiscReg();
876 getDTBPtr(tc)->invalidateMiscReg();
877 }
878
879 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
880 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
881 PCState pc = tc->pcState();
882 pc.nextThumb(cpsr.t);
883 pc.nextJazelle(cpsr.j);
884
885 // Follow slightly different semantics if a CheckerCPU object
886 // is connected
887 CheckerCPU *checker = tc->getCheckerCpuPtr();
888 if (checker) {
889 tc->pcStateNoRecord(pc);
890 } else {
891 tc->pcState(pc);
892 }
893 } else {
894#ifndef NDEBUG
895 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
896 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
897 warn("Unimplemented system register %s write with %#x.\n",
898 miscRegName[misc_reg], val);
899 else
900 panic("Unimplemented system register %s write with %#x.\n",
901 miscRegName[misc_reg], val);
902 }
903#endif
904 switch (unflattenMiscReg(misc_reg)) {
905 case MISCREG_CPACR:
906 {
907
908 const uint32_t ones = (uint32_t)(-1);
909 CPACR cpacrMask = 0;
910 // Only cp10, cp11, and ase are implemented, nothing else should
911 // be writable
912 cpacrMask.cp10 = ones;
913 cpacrMask.cp11 = ones;
914 cpacrMask.asedis = ones;
915
916 // Security Extensions may limit the writability of CPACR
917 if (haveSecurity) {
918 scr = readMiscRegNoEffect(MISCREG_SCR);
919 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
920 if (scr.ns && (cpsr.mode != MODE_MON)) {
921 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
922 // NB: Skipping the full loop, here
923 if (!nsacr.cp10) cpacrMask.cp10 = 0;
924 if (!nsacr.cp11) cpacrMask.cp11 = 0;
925 }
926 }
927
928 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
929 newVal &= cpacrMask;
930 newVal |= old_val & ~cpacrMask;
931 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
932 miscRegName[misc_reg], newVal);
933 }
934 break;
935 case MISCREG_CPACR_EL1:
936 {
937 const uint32_t ones = (uint32_t)(-1);
938 CPACR cpacrMask = 0;
939 cpacrMask.tta = ones;
940 cpacrMask.fpen = ones;
941 newVal &= cpacrMask;
942 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
943 miscRegName[misc_reg], newVal);
944 }
945 break;
946 case MISCREG_CPTR_EL2:
947 {
948 const uint32_t ones = (uint32_t)(-1);
949 CPTR cptrMask = 0;
950 cptrMask.tcpac = ones;
951 cptrMask.tta = ones;
952 cptrMask.tfp = ones;
953 newVal &= cptrMask;
954 cptrMask = 0;
955 cptrMask.res1_13_12_el2 = ones;
956 cptrMask.res1_9_0_el2 = ones;
957 newVal |= cptrMask;
958 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
959 miscRegName[misc_reg], newVal);
960 }
961 break;
962 case MISCREG_CPTR_EL3:
963 {
964 const uint32_t ones = (uint32_t)(-1);
965 CPTR cptrMask = 0;
966 cptrMask.tcpac = ones;
967 cptrMask.tta = ones;
968 cptrMask.tfp = ones;
969 newVal &= cptrMask;
970 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
971 miscRegName[misc_reg], newVal);
972 }
973 break;
974 case MISCREG_CSSELR:
975 warn_once("The csselr register isn't implemented.\n");
976 return;
977
978 case MISCREG_DC_ZVA_Xt:
979 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
980 return;
981
982 case MISCREG_FPSCR:
983 {
984 const uint32_t ones = (uint32_t)(-1);
985 FPSCR fpscrMask = 0;
986 fpscrMask.ioc = ones;
987 fpscrMask.dzc = ones;
988 fpscrMask.ofc = ones;
989 fpscrMask.ufc = ones;
990 fpscrMask.ixc = ones;
991 fpscrMask.idc = ones;
992 fpscrMask.ioe = ones;
993 fpscrMask.dze = ones;
994 fpscrMask.ofe = ones;
995 fpscrMask.ufe = ones;
996 fpscrMask.ixe = ones;
997 fpscrMask.ide = ones;
998 fpscrMask.len = ones;
999 fpscrMask.stride = ones;
1000 fpscrMask.rMode = ones;
1001 fpscrMask.fz = ones;
1002 fpscrMask.dn = ones;
1003 fpscrMask.ahp = ones;
1004 fpscrMask.qc = ones;
1005 fpscrMask.v = ones;
1006 fpscrMask.c = ones;
1007 fpscrMask.z = ones;
1008 fpscrMask.n = ones;
1009 newVal = (newVal & (uint32_t)fpscrMask) |
1010 (readMiscRegNoEffect(MISCREG_FPSCR) &
1011 ~(uint32_t)fpscrMask);
1012 tc->getDecoderPtr()->setContext(newVal);
1013 }
1014 break;
1015 case MISCREG_FPSR:
1016 {
1017 const uint32_t ones = (uint32_t)(-1);
1018 FPSCR fpscrMask = 0;
1019 fpscrMask.ioc = ones;
1020 fpscrMask.dzc = ones;
1021 fpscrMask.ofc = ones;
1022 fpscrMask.ufc = ones;
1023 fpscrMask.ixc = ones;
1024 fpscrMask.idc = ones;
1025 fpscrMask.qc = ones;
1026 fpscrMask.v = ones;
1027 fpscrMask.c = ones;
1028 fpscrMask.z = ones;
1029 fpscrMask.n = ones;
1030 newVal = (newVal & (uint32_t)fpscrMask) |
1031 (readMiscRegNoEffect(MISCREG_FPSCR) &
1032 ~(uint32_t)fpscrMask);
1033 misc_reg = MISCREG_FPSCR;
1034 }
1035 break;
1036 case MISCREG_FPCR:
1037 {
1038 const uint32_t ones = (uint32_t)(-1);
1039 FPSCR fpscrMask = 0;
1040 fpscrMask.ioe = ones;
1041 fpscrMask.dze = ones;
1042 fpscrMask.ofe = ones;
1043 fpscrMask.ufe = ones;
1044 fpscrMask.ixe = ones;
1045 fpscrMask.ide = ones;
1046 fpscrMask.len = ones;
1047 fpscrMask.stride = ones;
1048 fpscrMask.rMode = ones;
1049 fpscrMask.fz = ones;
1050 fpscrMask.dn = ones;
1051 fpscrMask.ahp = ones;
1052 newVal = (newVal & (uint32_t)fpscrMask) |
1053 (readMiscRegNoEffect(MISCREG_FPSCR) &
1054 ~(uint32_t)fpscrMask);
1055 misc_reg = MISCREG_FPSCR;
1056 }
1057 break;
1058 case MISCREG_CPSR_Q:
1059 {
1060 assert(!(newVal & ~CpsrMaskQ));
1061 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1062 misc_reg = MISCREG_CPSR;
1063 }
1064 break;
1065 case MISCREG_FPSCR_QC:
1066 {
1067 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1068 (newVal & FpscrQcMask);
1069 misc_reg = MISCREG_FPSCR;
1070 }
1071 break;
1072 case MISCREG_FPSCR_EXC:
1073 {
1074 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1075 (newVal & FpscrExcMask);
1076 misc_reg = MISCREG_FPSCR;
1077 }
1078 break;
1079 case MISCREG_FPEXC:
1080 {
1081 // vfpv3 architecture, section B.6.1 of DDI04068
1082 // bit 29 - valid only if fpexc[31] is 0
1083 const uint32_t fpexcMask = 0x60000000;
1084 newVal = (newVal & fpexcMask) |
1085 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1086 }
1087 break;
1088 case MISCREG_HCR:
1089 {
1090 if (!haveVirtualization)
1091 return;
1092 }
1093 break;
1094 case MISCREG_IFSR:
1095 {
1096 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1097 const uint32_t ifsrMask =
1098 mask(31, 13) | mask(11, 11) | mask(8, 6);
1099 newVal = newVal & ~ifsrMask;
1100 }
1101 break;
1102 case MISCREG_DFSR:
1103 {
1104 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1105 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1106 newVal = newVal & ~dfsrMask;
1107 }
1108 break;
1109 case MISCREG_AMAIR0:
1110 case MISCREG_AMAIR1:
1111 {
1112 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1113 // Valid only with LPAE
1114 if (!haveLPAE)
1115 return;
1116 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1117 }
1118 break;
1119 case MISCREG_SCR:
1120 getITBPtr(tc)->invalidateMiscReg();
1121 getDTBPtr(tc)->invalidateMiscReg();
1122 break;
1123 case MISCREG_SCTLR:
1124 {
1125 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1126 scr = readMiscRegNoEffect(MISCREG_SCR);
1127 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1128 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1129 SCTLR sctlr = miscRegs[sctlr_idx];
1130 SCTLR new_sctlr = newVal;
1131 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1132 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1133 getITBPtr(tc)->invalidateMiscReg();
1134 getDTBPtr(tc)->invalidateMiscReg();
1135 }
1136 case MISCREG_MIDR:
1137 case MISCREG_ID_PFR0:
1138 case MISCREG_ID_PFR1:
1139 case MISCREG_ID_DFR0:
1140 case MISCREG_ID_MMFR0:
1141 case MISCREG_ID_MMFR1:
1142 case MISCREG_ID_MMFR2:
1143 case MISCREG_ID_MMFR3:
1144 case MISCREG_ID_ISAR0:
1145 case MISCREG_ID_ISAR1:
1146 case MISCREG_ID_ISAR2:
1147 case MISCREG_ID_ISAR3:
1148 case MISCREG_ID_ISAR4:
1149 case MISCREG_ID_ISAR5:
1150
1151 case MISCREG_MPIDR:
1152 case MISCREG_FPSID:
1153 case MISCREG_TLBTR:
1154 case MISCREG_MVFR0:
1155 case MISCREG_MVFR1:
1156
1157 case MISCREG_ID_AA64AFR0_EL1:
1158 case MISCREG_ID_AA64AFR1_EL1:
1159 case MISCREG_ID_AA64DFR0_EL1:
1160 case MISCREG_ID_AA64DFR1_EL1:
1161 case MISCREG_ID_AA64ISAR0_EL1:
1162 case MISCREG_ID_AA64ISAR1_EL1:
1163 case MISCREG_ID_AA64MMFR0_EL1:
1164 case MISCREG_ID_AA64MMFR1_EL1:
1165 case MISCREG_ID_AA64PFR0_EL1:
1166 case MISCREG_ID_AA64PFR1_EL1:
1167 // ID registers are constants.
1168 return;
1169
1170 // TLBI all entries, EL0&1 inner sharable (ignored)
1171 case MISCREG_TLBIALLIS:
1172 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1173 assert32(tc);
1174 target_el = 1; // el 0 and 1 are handled together
1175 scr = readMiscReg(MISCREG_SCR, tc);
1176 secure_lookup = haveSecurity && !scr.ns;
1177 sys = tc->getSystemPtr();
1178 for (x = 0; x < sys->numContexts(); x++) {
1179 oc = sys->getThreadContext(x);
1180 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1181 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1182
1183 // If CheckerCPU is connected, need to notify it of a flush
1184 CheckerCPU *checker = oc->getCheckerCpuPtr();
1185 if (checker) {
1186 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1187 target_el);
1188 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1189 target_el);
1190 }
1191 }
1192 return;
1193 // TLBI all entries, EL0&1, instruction side
1194 case MISCREG_ITLBIALL:
1195 assert32(tc);
1196 target_el = 1; // el 0 and 1 are handled together
1197 scr = readMiscReg(MISCREG_SCR, tc);
1198 secure_lookup = haveSecurity && !scr.ns;
1199 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1200 return;
1201 // TLBI all entries, EL0&1, data side
1202 case MISCREG_DTLBIALL:
1203 assert32(tc);
1204 target_el = 1; // el 0 and 1 are handled together
1205 scr = readMiscReg(MISCREG_SCR, tc);
1206 secure_lookup = haveSecurity && !scr.ns;
1207 getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1208 return;
1209 // TLBI based on VA, EL0&1 inner sharable (ignored)
1210 case MISCREG_TLBIMVAIS:
1211 case MISCREG_TLBIMVA:
1212 assert32(tc);
1213 target_el = 1; // el 0 and 1 are handled together
1214 scr = readMiscReg(MISCREG_SCR, tc);
1215 secure_lookup = haveSecurity && !scr.ns;
1216 sys = tc->getSystemPtr();
1217 for (x = 0; x < sys->numContexts(); x++) {
1218 oc = sys->getThreadContext(x);
1219 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1220 bits(newVal, 7,0),
1221 secure_lookup, target_el);
1222 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1223 bits(newVal, 7,0),
1224 secure_lookup, target_el);
1225
1226 CheckerCPU *checker = oc->getCheckerCpuPtr();
1227 if (checker) {
1228 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1229 bits(newVal, 7,0), secure_lookup, target_el);
1230 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1231 bits(newVal, 7,0), secure_lookup, target_el);
1232 }
1233 }
1234 return;
1235 // TLBI by ASID, EL0&1, inner sharable
1236 case MISCREG_TLBIASIDIS:
1237 case MISCREG_TLBIASID:
1238 assert32(tc);
1239 target_el = 1; // el 0 and 1 are handled together
1240 scr = readMiscReg(MISCREG_SCR, tc);
1241 secure_lookup = haveSecurity && !scr.ns;
1242 sys = tc->getSystemPtr();
1243 for (x = 0; x < sys->numContexts(); x++) {
1244 oc = sys->getThreadContext(x);
1245 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1246 secure_lookup, target_el);
1247 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1248 secure_lookup, target_el);
1249 CheckerCPU *checker = oc->getCheckerCpuPtr();
1250 if (checker) {
1251 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1252 secure_lookup, target_el);
1253 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1254 secure_lookup, target_el);
1255 }
1256 }
1257 return;
1258 // TLBI by address, EL0&1, inner sharable (ignored)
1259 case MISCREG_TLBIMVAAIS:
1260 case MISCREG_TLBIMVAA:
1261 assert32(tc);
1262 target_el = 1; // el 0 and 1 are handled together
1263 scr = readMiscReg(MISCREG_SCR, tc);
1264 secure_lookup = haveSecurity && !scr.ns;
1265 hyp = 0;
1266 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1267 return;
1268 // TLBI by address, EL2, hypervisor mode
1269 case MISCREG_TLBIMVAH:
1270 case MISCREG_TLBIMVAHIS:
1271 assert32(tc);
1272 target_el = 1; // aarch32, use hyp bit
1273 scr = readMiscReg(MISCREG_SCR, tc);
1274 secure_lookup = haveSecurity && !scr.ns;
1275 hyp = 1;
1276 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1277 return;
1278 // TLBI by address and asid, EL0&1, instruction side only
1279 case MISCREG_ITLBIMVA:
1280 assert32(tc);
1281 target_el = 1; // el 0 and 1 are handled together
1282 scr = readMiscReg(MISCREG_SCR, tc);
1283 secure_lookup = haveSecurity && !scr.ns;
1284 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1285 bits(newVal, 7,0), secure_lookup, target_el);
1286 return;
1287 // TLBI by address and asid, EL0&1, data side only
1288 case MISCREG_DTLBIMVA:
1289 assert32(tc);
1290 target_el = 1; // el 0 and 1 are handled together
1291 scr = readMiscReg(MISCREG_SCR, tc);
1292 secure_lookup = haveSecurity && !scr.ns;
1293 getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1294 bits(newVal, 7,0), secure_lookup, target_el);
1295 return;
1296 // TLBI by ASID, EL0&1, instrution side only
1297 case MISCREG_ITLBIASID:
1298 assert32(tc);
1299 target_el = 1; // el 0 and 1 are handled together
1300 scr = readMiscReg(MISCREG_SCR, tc);
1301 secure_lookup = haveSecurity && !scr.ns;
1302 getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1303 target_el);
1304 return;
1305 // TLBI by ASID EL0&1 data size only
1306 case MISCREG_DTLBIASID:
1307 assert32(tc);
1308 target_el = 1; // el 0 and 1 are handled together
1309 scr = readMiscReg(MISCREG_SCR, tc);
1310 secure_lookup = haveSecurity && !scr.ns;
1311 getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1312 target_el);
1313 return;
1314 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1315 case MISCREG_TLBIALLNSNH:
1316 case MISCREG_TLBIALLNSNHIS:
1317 assert32(tc);
1318 target_el = 1; // el 0 and 1 are handled together
1319 hyp = 0;
1320 tlbiALLN(tc, hyp, target_el);
1321 return;
1322 // TLBI all entries, EL2, hyp,
1323 case MISCREG_TLBIALLH:
1324 case MISCREG_TLBIALLHIS:
1325 assert32(tc);
1326 target_el = 1; // aarch32, use hyp bit
1327 hyp = 1;
1328 tlbiALLN(tc, hyp, target_el);
1329 return;
1330 // AArch64 TLBI: invalidate all entries EL3
1331 case MISCREG_TLBI_ALLE3IS:
1332 case MISCREG_TLBI_ALLE3:
1333 assert64(tc);
1334 target_el = 3;
1335 secure_lookup = true;
1336 tlbiALL(tc, secure_lookup, target_el);
1337 return;
1338 // @todo: uncomment this to enable Virtualization
1339 // case MISCREG_TLBI_ALLE2IS:
1340 // case MISCREG_TLBI_ALLE2:
1341 // TLBI all entries, EL0&1
1342 case MISCREG_TLBI_ALLE1IS:
1343 case MISCREG_TLBI_ALLE1:
1344 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1345 case MISCREG_TLBI_VMALLE1IS:
1346 case MISCREG_TLBI_VMALLE1:
1347 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1348 case MISCREG_TLBI_VMALLS12E1IS:
1349 case MISCREG_TLBI_VMALLS12E1:
1350 // @todo: handle VMID and stage 2 to enable Virtualization
1351 assert64(tc);
1352 target_el = 1; // el 0 and 1 are handled together
1353 scr = readMiscReg(MISCREG_SCR, tc);
1354 secure_lookup = haveSecurity && !scr.ns;
1355 tlbiALL(tc, secure_lookup, target_el);
1356 return;
1357 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1358 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1359 // from the last level of translation table walks
1360 // @todo: handle VMID to enable Virtualization
1361 // TLBI all entries, EL0&1
1362 case MISCREG_TLBI_VAE3IS_Xt:
1363 case MISCREG_TLBI_VAE3_Xt:
1364 // TLBI by VA, EL3 regime stage 1, last level walk
1365 case MISCREG_TLBI_VALE3IS_Xt:
1366 case MISCREG_TLBI_VALE3_Xt:
1367 assert64(tc);
1368 target_el = 3;
1369 asid = 0xbeef; // does not matter, tlbi is global
1370 secure_lookup = true;
1371 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1372 return;
1373 // TLBI by VA, EL2
1374 case MISCREG_TLBI_VAE2IS_Xt:
1375 case MISCREG_TLBI_VAE2_Xt:
1376 // TLBI by VA, EL2, stage1 last level walk
1377 case MISCREG_TLBI_VALE2IS_Xt:
1378 case MISCREG_TLBI_VALE2_Xt:
1379 assert64(tc);
1380 target_el = 2;
1381 asid = 0xbeef; // does not matter, tlbi is global
1382 scr = readMiscReg(MISCREG_SCR, tc);
1383 secure_lookup = haveSecurity && !scr.ns;
1384 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1385 return;
1386 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1387 case MISCREG_TLBI_VAE1IS_Xt:
1388 case MISCREG_TLBI_VAE1_Xt:
1389 case MISCREG_TLBI_VALE1IS_Xt:
1390 case MISCREG_TLBI_VALE1_Xt:
1391 assert64(tc);
1392 asid = bits(newVal, 63, 48);
1393 target_el = 1; // el 0 and 1 are handled together
1394 scr = readMiscReg(MISCREG_SCR, tc);
1395 secure_lookup = haveSecurity && !scr.ns;
1396 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1397 return;
1398 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1399 // @todo: handle VMID to enable Virtualization
1400 case MISCREG_TLBI_ASIDE1IS_Xt:
1401 case MISCREG_TLBI_ASIDE1_Xt:
1402 assert64(tc);
1403 target_el = 1; // el 0 and 1 are handled together
1404 scr = readMiscReg(MISCREG_SCR, tc);
1405 secure_lookup = haveSecurity && !scr.ns;
1406 sys = tc->getSystemPtr();
1407 for (x = 0; x < sys->numContexts(); x++) {
1408 oc = sys->getThreadContext(x);
1409 asid = bits(newVal, 63, 48);
1410 if (!haveLargeAsid64)
1411 asid &= mask(8);
1412 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1413 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1414 CheckerCPU *checker = oc->getCheckerCpuPtr();
1415 if (checker) {
1416 getITBPtr(checker)->flushAsid(asid,
1417 secure_lookup, target_el);
1418 getDTBPtr(checker)->flushAsid(asid,
1419 secure_lookup, target_el);
1420 }
1421 }
1422 return;
1423 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1424 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1425 // entries from the last level of translation table walks
1426 // @todo: handle VMID to enable Virtualization
1427 case MISCREG_TLBI_VAAE1IS_Xt:
1428 case MISCREG_TLBI_VAAE1_Xt:
1429 case MISCREG_TLBI_VAALE1IS_Xt:
1430 case MISCREG_TLBI_VAALE1_Xt:
1431 assert64(tc);
1432 target_el = 1; // el 0 and 1 are handled together
1433 scr = readMiscReg(MISCREG_SCR, tc);
1434 secure_lookup = haveSecurity && !scr.ns;
1435 sys = tc->getSystemPtr();
1436 for (x = 0; x < sys->numContexts(); x++) {
1437 // @todo: extra controls on TLBI broadcast?
1438 oc = sys->getThreadContext(x);
1439 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1440 getITBPtr(oc)->flushMva(va,
1441 secure_lookup, false, target_el);
1442 getDTBPtr(oc)->flushMva(va,
1443 secure_lookup, false, target_el);
1444
1445 CheckerCPU *checker = oc->getCheckerCpuPtr();
1446 if (checker) {
1447 getITBPtr(checker)->flushMva(va,
1448 secure_lookup, false, target_el);
1449 getDTBPtr(checker)->flushMva(va,
1450 secure_lookup, false, target_el);
1451 }
1452 }
1453 return;
1454 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1455 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1456 case MISCREG_TLBI_IPAS2LE1_Xt:
1457 case MISCREG_TLBI_IPAS2E1IS_Xt:
1458 case MISCREG_TLBI_IPAS2E1_Xt:
1459 assert64(tc);
1460 target_el = 1; // EL 0 and 1 are handled together
1461 scr = readMiscReg(MISCREG_SCR, tc);
1462 secure_lookup = haveSecurity && !scr.ns;
1463 sys = tc->getSystemPtr();
1464 for (x = 0; x < sys->numContexts(); x++) {
1465 oc = sys->getThreadContext(x);
1466 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1467 getITBPtr(oc)->flushIpaVmid(ipa,
1468 secure_lookup, false, target_el);
1469 getDTBPtr(oc)->flushIpaVmid(ipa,
1470 secure_lookup, false, target_el);
1471
1472 CheckerCPU *checker = oc->getCheckerCpuPtr();
1473 if (checker) {
1474 getITBPtr(checker)->flushIpaVmid(ipa,
1475 secure_lookup, false, target_el);
1476 getDTBPtr(checker)->flushIpaVmid(ipa,
1477 secure_lookup, false, target_el);
1478 }
1479 }
1480 return;
1481 case MISCREG_ACTLR:
1482 warn("Not doing anything for write of miscreg ACTLR\n");
1483 break;
1484
1485 case MISCREG_PMXEVTYPER_PMCCFILTR:
1486 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1487 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1488 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1489 pmu->setMiscReg(misc_reg, newVal);
1490 break;
1491
1492
1493 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1494 {
1495 HSTR hstrMask = 0;
1496 hstrMask.tjdbx = 1;
1497 newVal &= ~((uint32_t) hstrMask);
1498 break;
1499 }
1500 case MISCREG_HCPTR:
1501 {
1502 // If a CP bit in NSACR is 0 then the corresponding bit in
1503 // HCPTR is RAO/WI. Same applies to NSASEDIS
1504 secure_lookup = haveSecurity &&
1505 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1506 readMiscRegNoEffect(MISCREG_CPSR));
1507 if (!secure_lookup) {
1508 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1509 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1510 newVal = (newVal & ~mask) | (oldValue & mask);
1511 }
1512 break;
1513 }
1514 case MISCREG_HDFAR: // alias for secure DFAR
1515 misc_reg = MISCREG_DFAR_S;
1516 break;
1517 case MISCREG_HIFAR: // alias for secure IFAR
1518 misc_reg = MISCREG_IFAR_S;
1519 break;
1520 case MISCREG_ATS1CPR:
1521 case MISCREG_ATS1CPW:
1522 case MISCREG_ATS1CUR:
1523 case MISCREG_ATS1CUW:
1524 case MISCREG_ATS12NSOPR:
1525 case MISCREG_ATS12NSOPW:
1526 case MISCREG_ATS12NSOUR:
1527 case MISCREG_ATS12NSOUW:
1528 case MISCREG_ATS1HR:
1529 case MISCREG_ATS1HW:
1530 {
1531 Request::Flags flags = 0;
1532 BaseTLB::Mode mode = BaseTLB::Read;
1533 TLB::ArmTranslationType tranType = TLB::NormalTran;
1534 Fault fault;
1535 switch(misc_reg) {
1536 case MISCREG_ATS1CPR:
1537 flags = TLB::MustBeOne;
1538 tranType = TLB::S1CTran;
1539 mode = BaseTLB::Read;
1540 break;
1541 case MISCREG_ATS1CPW:
1542 flags = TLB::MustBeOne;
1543 tranType = TLB::S1CTran;
1544 mode = BaseTLB::Write;
1545 break;
1546 case MISCREG_ATS1CUR:
1547 flags = TLB::MustBeOne | TLB::UserMode;
1548 tranType = TLB::S1CTran;
1549 mode = BaseTLB::Read;
1550 break;
1551 case MISCREG_ATS1CUW:
1552 flags = TLB::MustBeOne | TLB::UserMode;
1553 tranType = TLB::S1CTran;
1554 mode = BaseTLB::Write;
1555 break;
1556 case MISCREG_ATS12NSOPR:
1557 if (!haveSecurity)
1558 panic("Security Extensions required for ATS12NSOPR");
1559 flags = TLB::MustBeOne;
1560 tranType = TLB::S1S2NsTran;
1561 mode = BaseTLB::Read;
1562 break;
1563 case MISCREG_ATS12NSOPW:
1564 if (!haveSecurity)
1565 panic("Security Extensions required for ATS12NSOPW");
1566 flags = TLB::MustBeOne;
1567 tranType = TLB::S1S2NsTran;
1568 mode = BaseTLB::Write;
1569 break;
1570 case MISCREG_ATS12NSOUR:
1571 if (!haveSecurity)
1572 panic("Security Extensions required for ATS12NSOUR");
1573 flags = TLB::MustBeOne | TLB::UserMode;
1574 tranType = TLB::S1S2NsTran;
1575 mode = BaseTLB::Read;
1576 break;
1577 case MISCREG_ATS12NSOUW:
1578 if (!haveSecurity)
1579 panic("Security Extensions required for ATS12NSOUW");
1580 flags = TLB::MustBeOne | TLB::UserMode;
1581 tranType = TLB::S1S2NsTran;
1582 mode = BaseTLB::Write;
1583 break;
1584 case MISCREG_ATS1HR: // only really useful from secure mode.
1585 flags = TLB::MustBeOne;
1586 tranType = TLB::HypMode;
1587 mode = BaseTLB::Read;
1588 break;
1589 case MISCREG_ATS1HW:
1590 flags = TLB::MustBeOne;
1591 tranType = TLB::HypMode;
1592 mode = BaseTLB::Write;
1593 break;
1594 }
1595 // If we're in timing mode then doing the translation in
1596 // functional mode then we're slightly distorting performance
1597 // results obtained from simulations. The translation should be
1598 // done in the same mode the core is running in. NOTE: This
1599 // can't be an atomic translation because that causes problems
1600 // with unexpected atomic snoop requests.
1601 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1602 Request req(0, val, 0, flags, Request::funcMasterId,
1603 tc->pcState().pc(), tc->contextId());
1604 fault = getDTBPtr(tc)->translateFunctional(
1605 &req, tc, mode, tranType);
1606 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1607 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1608
1609 MiscReg newVal;
1610 if (fault == NoFault) {
1611 Addr paddr = req.getPaddr();
1612 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1613 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1614 newVal = (paddr & mask(39, 12)) |
1615 (getDTBPtr(tc)->getAttr());
1616 } else {
1617 newVal = (paddr & 0xfffff000) |
1618 (getDTBPtr(tc)->getAttr());
1619 }
1620 DPRINTF(MiscRegs,
1621 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1622 val, newVal);
1623 } else {
1624 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1625 // Set fault bit and FSR
1626 FSR fsr = armFault->getFsr(tc);
1627
1628 newVal = ((fsr >> 9) & 1) << 11;
1629 if (newVal) {
1630 // LPAE - rearange fault status
1631 newVal |= ((fsr >> 0) & 0x3f) << 1;
1632 } else {
1633 // VMSA - rearange fault status
1634 newVal |= ((fsr >> 0) & 0xf) << 1;
1635 newVal |= ((fsr >> 10) & 0x1) << 5;
1636 newVal |= ((fsr >> 12) & 0x1) << 6;
1637 }
1638 newVal |= 0x1; // F bit
1639 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1640 newVal |= armFault->isStage2() ? 0x200 : 0;
1641 DPRINTF(MiscRegs,
1642 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1643 val, fsr, newVal);
1644 }
1645 setMiscRegNoEffect(MISCREG_PAR, newVal);
1646 return;
1647 }
1648 case MISCREG_TTBCR:
1649 {
1650 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1651 const uint32_t ones = (uint32_t)(-1);
1652 TTBCR ttbcrMask = 0;
1653 TTBCR ttbcrNew = newVal;
1654
1655 // ARM DDI 0406C.b, ARMv7-32
1656 ttbcrMask.n = ones; // T0SZ
1657 if (haveSecurity) {
1658 ttbcrMask.pd0 = ones;
1659 ttbcrMask.pd1 = ones;
1660 }
1661 ttbcrMask.epd0 = ones;
1662 ttbcrMask.irgn0 = ones;
1663 ttbcrMask.orgn0 = ones;
1664 ttbcrMask.sh0 = ones;
1665 ttbcrMask.ps = ones; // T1SZ
1666 ttbcrMask.a1 = ones;
1667 ttbcrMask.epd1 = ones;
1668 ttbcrMask.irgn1 = ones;
1669 ttbcrMask.orgn1 = ones;
1670 ttbcrMask.sh1 = ones;
1671 if (haveLPAE)
1672 ttbcrMask.eae = ones;
1673
1674 if (haveLPAE && ttbcrNew.eae) {
1675 newVal = newVal & ttbcrMask;
1676 } else {
1677 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1678 }
1679 }
1680 M5_FALLTHROUGH;
1681 case MISCREG_TTBR0:
1682 case MISCREG_TTBR1:
1683 {
1684 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1685 if (haveLPAE) {
1686 if (ttbcr.eae) {
1687 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1688 // ARMv8 AArch32 bit 63-56 only
1689 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1690 newVal = (newVal & (~ttbrMask));
1691 }
1692 }
1693 }
1694 M5_FALLTHROUGH;
1695 case MISCREG_SCTLR_EL1:
1696 {
1697 getITBPtr(tc)->invalidateMiscReg();
1698 getDTBPtr(tc)->invalidateMiscReg();
1699 setMiscRegNoEffect(misc_reg, newVal);
1700 }
1701 M5_FALLTHROUGH;
1702 case MISCREG_CONTEXTIDR:
1703 case MISCREG_PRRR:
1704 case MISCREG_NMRR:
1705 case MISCREG_MAIR0:
1706 case MISCREG_MAIR1:
1707 case MISCREG_DACR:
1708 case MISCREG_VTTBR:
1709 case MISCREG_SCR_EL3:
1710 case MISCREG_HCR_EL2:
1711 case MISCREG_TCR_EL1:
1712 case MISCREG_TCR_EL2:
1713 case MISCREG_TCR_EL3:
1714 case MISCREG_SCTLR_EL2:
1715 case MISCREG_SCTLR_EL3:
1716 case MISCREG_HSCTLR:
1717 case MISCREG_TTBR0_EL1:
1718 case MISCREG_TTBR1_EL1:
1719 case MISCREG_TTBR0_EL2:
1720 case MISCREG_TTBR0_EL3:
1721 getITBPtr(tc)->invalidateMiscReg();
1722 getDTBPtr(tc)->invalidateMiscReg();
1723 break;
1724 case MISCREG_NZCV:
1725 {
1726 CPSR cpsr = val;
1727
1728 tc->setCCReg(CCREG_NZ, cpsr.nz);
1729 tc->setCCReg(CCREG_C, cpsr.c);
1730 tc->setCCReg(CCREG_V, cpsr.v);
1731 }
1732 break;
1733 case MISCREG_DAIF:
1734 {
1735 CPSR cpsr = miscRegs[MISCREG_CPSR];
1736 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1737 newVal = cpsr;
1738 misc_reg = MISCREG_CPSR;
1739 }
1740 break;
1741 case MISCREG_SP_EL0:
1742 tc->setIntReg(INTREG_SP0, newVal);
1743 break;
1744 case MISCREG_SP_EL1:
1745 tc->setIntReg(INTREG_SP1, newVal);
1746 break;
1747 case MISCREG_SP_EL2:
1748 tc->setIntReg(INTREG_SP2, newVal);
1749 break;
1750 case MISCREG_SPSEL:
1751 {
1752 CPSR cpsr = miscRegs[MISCREG_CPSR];
1753 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1754 newVal = cpsr;
1755 misc_reg = MISCREG_CPSR;
1756 }
1757 break;
1758 case MISCREG_CURRENTEL:
1759 {
1760 CPSR cpsr = miscRegs[MISCREG_CPSR];
1761 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1762 newVal = cpsr;
1763 misc_reg = MISCREG_CPSR;
1764 }
1765 break;
1766 case MISCREG_AT_S1E1R_Xt:
1767 case MISCREG_AT_S1E1W_Xt:
1768 case MISCREG_AT_S1E0R_Xt:
1769 case MISCREG_AT_S1E0W_Xt:
1770 case MISCREG_AT_S1E2R_Xt:
1771 case MISCREG_AT_S1E2W_Xt:
1772 case MISCREG_AT_S12E1R_Xt:
1773 case MISCREG_AT_S12E1W_Xt:
1774 case MISCREG_AT_S12E0R_Xt:
1775 case MISCREG_AT_S12E0W_Xt:
1776 case MISCREG_AT_S1E3R_Xt:
1777 case MISCREG_AT_S1E3W_Xt:
1778 {
1779 RequestPtr req = new Request;
1780 Request::Flags flags = 0;
1781 BaseTLB::Mode mode = BaseTLB::Read;
1782 TLB::ArmTranslationType tranType = TLB::NormalTran;
1783 Fault fault;
1784 switch(misc_reg) {
1785 case MISCREG_AT_S1E1R_Xt:
1786 flags = TLB::MustBeOne;
1787 tranType = TLB::S1E1Tran;
1788 mode = BaseTLB::Read;
1789 break;
1790 case MISCREG_AT_S1E1W_Xt:
1791 flags = TLB::MustBeOne;
1792 tranType = TLB::S1E1Tran;
1793 mode = BaseTLB::Write;
1794 break;
1795 case MISCREG_AT_S1E0R_Xt:
1796 flags = TLB::MustBeOne | TLB::UserMode;
1797 tranType = TLB::S1E0Tran;
1798 mode = BaseTLB::Read;
1799 break;
1800 case MISCREG_AT_S1E0W_Xt:
1801 flags = TLB::MustBeOne | TLB::UserMode;
1802 tranType = TLB::S1E0Tran;
1803 mode = BaseTLB::Write;
1804 break;
1805 case MISCREG_AT_S1E2R_Xt:
1806 flags = TLB::MustBeOne;
1807 tranType = TLB::S1E2Tran;
1808 mode = BaseTLB::Read;
1809 break;
1810 case MISCREG_AT_S1E2W_Xt:
1811 flags = TLB::MustBeOne;
1812 tranType = TLB::S1E2Tran;
1813 mode = BaseTLB::Write;
1814 break;
1815 case MISCREG_AT_S12E0R_Xt:
1816 flags = TLB::MustBeOne | TLB::UserMode;
1817 tranType = TLB::S12E0Tran;
1818 mode = BaseTLB::Read;
1819 break;
1820 case MISCREG_AT_S12E0W_Xt:
1821 flags = TLB::MustBeOne | TLB::UserMode;
1822 tranType = TLB::S12E0Tran;
1823 mode = BaseTLB::Write;
1824 break;
1825 case MISCREG_AT_S12E1R_Xt:
1826 flags = TLB::MustBeOne;
1827 tranType = TLB::S12E1Tran;
1828 mode = BaseTLB::Read;
1829 break;
1830 case MISCREG_AT_S12E1W_Xt:
1831 flags = TLB::MustBeOne;
1832 tranType = TLB::S12E1Tran;
1833 mode = BaseTLB::Write;
1834 break;
1835 case MISCREG_AT_S1E3R_Xt:
1836 flags = TLB::MustBeOne;
1837 tranType = TLB::S1E3Tran;
1838 mode = BaseTLB::Read;
1839 break;
1840 case MISCREG_AT_S1E3W_Xt:
1841 flags = TLB::MustBeOne;
1842 tranType = TLB::S1E3Tran;
1843 mode = BaseTLB::Write;
1844 break;
1845 }
1846 // If we're in timing mode then doing the translation in
1847 // functional mode then we're slightly distorting performance
1848 // results obtained from simulations. The translation should be
1849 // done in the same mode the core is running in. NOTE: This
1850 // can't be an atomic translation because that causes problems
1851 // with unexpected atomic snoop requests.
1852 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1853 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1854 tc->pcState().pc());
1855 req->setContext(tc->contextId());
1856 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1857 tranType);
1858
1859 MiscReg newVal;
1860 if (fault == NoFault) {
1861 Addr paddr = req->getPaddr();
1862 uint64_t attr = getDTBPtr(tc)->getAttr();
1863 uint64_t attr1 = attr >> 56;
1864 if (!attr1 || attr1 ==0x44) {
1865 attr |= 0x100;
1866 attr &= ~ uint64_t(0x80);
1867 }
1868 newVal = (paddr & mask(47, 12)) | attr;
1869 DPRINTF(MiscRegs,
1870 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1871 val, newVal);
1872 } else {
1873 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1874 // Set fault bit and FSR
1875 FSR fsr = armFault->getFsr(tc);
1876
1877 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1878 if (cpsr.width) { // AArch32
1879 newVal = ((fsr >> 9) & 1) << 11;
1880 // rearrange fault status
1881 newVal |= ((fsr >> 0) & 0x3f) << 1;
1882 newVal |= 0x1; // F bit
1883 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1884 newVal |= armFault->isStage2() ? 0x200 : 0;
1885 } else { // AArch64
1886 newVal = 1; // F bit
1887 newVal |= fsr << 1; // FST
1888 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1889 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1890 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1891 newVal |= 1 << 11; // RES1
1892 }
1893 DPRINTF(MiscRegs,
1894 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1895 val, fsr, newVal);
1896 }
1897 delete req;
1898 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1899 return;
1900 }
1901 case MISCREG_SPSR_EL3:
1902 case MISCREG_SPSR_EL2:
1903 case MISCREG_SPSR_EL1:
1904 // Force bits 23:21 to 0
1905 newVal = val & ~(0x7 << 21);
1906 break;
1907 case MISCREG_L2CTLR:
1908 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1909 miscRegName[misc_reg], uint32_t(val));
1910 break;
1911
1912 // Generic Timer registers
1913 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1914 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1915 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1916 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1917 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1918 break;
1919 }
1920 }
1921 setMiscRegNoEffect(misc_reg, newVal);
1922}
1923
1924void
1925ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1926 bool secure_lookup, uint8_t target_el)
1927{
1928 if (!haveLargeAsid64)
1929 asid &= mask(8);
1930 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1931 System *sys = tc->getSystemPtr();
1932 for (int x = 0; x < sys->numContexts(); x++) {
1933 ThreadContext *oc = sys->getThreadContext(x);
1934 getITBPtr(oc)->flushMvaAsid(va, asid,
1935 secure_lookup, target_el);
1936 getDTBPtr(oc)->flushMvaAsid(va, asid,
1937 secure_lookup, target_el);
1938
1939 CheckerCPU *checker = oc->getCheckerCpuPtr();
1940 if (checker) {
1941 getITBPtr(checker)->flushMvaAsid(
1942 va, asid, secure_lookup, target_el);
1943 getDTBPtr(checker)->flushMvaAsid(
1944 va, asid, secure_lookup, target_el);
1945 }
1946 }
1947}
1948
1949void
1950ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1951{
1952 System *sys = tc->getSystemPtr();
1953 for (int x = 0; x < sys->numContexts(); x++) {
1954 ThreadContext *oc = sys->getThreadContext(x);
1955 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1956 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1957
1958 // If CheckerCPU is connected, need to notify it of a flush
1959 CheckerCPU *checker = oc->getCheckerCpuPtr();
1960 if (checker) {
1961 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1962 target_el);
1963 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1964 target_el);
1965 }
1966 }
1967}
1968
1969void
1970ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1971{
1972 System *sys = tc->getSystemPtr();
1973 for (int x = 0; x < sys->numContexts(); x++) {
1974 ThreadContext *oc = sys->getThreadContext(x);
1975 getITBPtr(oc)->flushAllNs(hyp, target_el);
1976 getDTBPtr(oc)->flushAllNs(hyp, target_el);
1977
1978 CheckerCPU *checker = oc->getCheckerCpuPtr();
1979 if (checker) {
1980 getITBPtr(checker)->flushAllNs(hyp, target_el);
1981 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1982 }
1983 }
1984}
1985
1986void
1987ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1988 uint8_t target_el)
1989{
1990 System *sys = tc->getSystemPtr();
1991 for (int x = 0; x < sys->numContexts(); x++) {
1992 ThreadContext *oc = sys->getThreadContext(x);
1993 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
1994 secure_lookup, hyp, target_el);
1995 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
1996 secure_lookup, hyp, target_el);
1997
1998 CheckerCPU *checker = oc->getCheckerCpuPtr();
1999 if (checker) {
2000 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
2001 secure_lookup, hyp, target_el);
2002 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
2003 secure_lookup, hyp, target_el);
2004 }
2005 }
2006}
2007
2008BaseISADevice &
2009ISA::getGenericTimer(ThreadContext *tc)
2010{
2011 // We only need to create an ISA interface the first time we try
2012 // to access the timer.
2013 if (timer)
2014 return *timer.get();
2015
2016 assert(system);
2017 GenericTimer *generic_timer(system->getGenericTimer());
2018 if (!generic_timer) {
2019 panic("Trying to get a generic timer from a system that hasn't "
2020 "been configured to use a generic timer.\n");
2021 }
2022
2023 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2024 return *timer.get();
2025}
2026
2027}
2028
2029ArmISA::ISA *
2030ArmISAParams::create()
2031{
2032 return new ArmISA::ISA(this);
2033}