1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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154 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
155 Addr npc = tc->readNextPC() & ~PcModeMask;
156 if (cpsr.j)
157 npc = npc | (ULL(1) << PcJBitShift);
158 if (cpsr.t)
159 npc = npc | (ULL(1) << PcTBitShift);
160
161 tc->setNextPC(npc);
162 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
163 misc_reg < MISCREG_CP15_END) {
164 panic("Unimplemented CP15 register %s wrote with %#x.\n",
165 miscRegName[misc_reg], val);
166 } else {
167 switch (misc_reg) {
168 case MISCREG_ITSTATE:
169 {
170 ITSTATE itstate = newVal;
171 CPSR cpsr = miscRegs[MISCREG_CPSR];
172 cpsr.it1 = itstate.bottom2;
173 cpsr.it2 = itstate.top6;
174 miscRegs[MISCREG_CPSR] = cpsr;
175 DPRINTF(MiscRegs,
176 "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
177 (uint8_t)itstate, (uint32_t)cpsr);
178 }
179 break;
180 case MISCREG_CPACR:
181 {
182 CPACR newCpacr = 0;
183 CPACR valCpacr = val;
184 newCpacr.cp10 = valCpacr.cp10;
185 newCpacr.cp11 = valCpacr.cp11;
186 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
187 panic("Disabling coprocessors isn't implemented.\n");
188 }
189 newVal = newCpacr;
190 }
191 break;
192 case MISCREG_CSSELR:
193 warn("The csselr register isn't implemented.\n");
194 break;
195 case MISCREG_FPSCR:
196 {
197 const uint32_t ones = (uint32_t)(-1);
198 FPSCR fpscrMask = 0;
199 fpscrMask.ioc = ones;
200 fpscrMask.dzc = ones;
201 fpscrMask.ofc = ones;
202 fpscrMask.ufc = ones;
203 fpscrMask.ixc = ones;
204 fpscrMask.idc = ones;
205 fpscrMask.len = ones;
206 fpscrMask.stride = ones;
207 fpscrMask.rMode = ones;
208 fpscrMask.fz = ones;
209 fpscrMask.dn = ones;
210 fpscrMask.ahp = ones;
211 fpscrMask.qc = ones;
212 fpscrMask.v = ones;
213 fpscrMask.c = ones;
214 fpscrMask.z = ones;
215 fpscrMask.n = ones;
216 newVal = (newVal & (uint32_t)fpscrMask) |
217 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
218 }
219 break;
220 case MISCREG_FPEXC:
221 {
222 const uint32_t fpexcMask = 0x60000000;
223 newVal = (newVal & fpexcMask) |
224 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
225 }
226 break;
227 case MISCREG_SCTLR:
228 {
229 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
230 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
231 SCTLR new_sctlr = newVal;
232 new_sctlr.nmfi = (bool)sctlr.nmfi;
233 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
234 return;
235 }
236 case MISCREG_TLBTR:
237 case MISCREG_MVFR0:
238 case MISCREG_MVFR1:
239 case MISCREG_MPIDR:
240 case MISCREG_FPSID:
241 return;
242 case MISCREG_TLBIALLIS:
243 case MISCREG_TLBIALL:
244 warn("Need to flush all TLBs in MP\n");
245 tc->getITBPtr()->flushAll();
246 tc->getDTBPtr()->flushAll();
247 return;
248 case MISCREG_ITLBIALL:
249 tc->getITBPtr()->flushAll();
250 return;
251 case MISCREG_DTLBIALL:
252 tc->getDTBPtr()->flushAll();
253 return;
254 case MISCREG_TLBIMVAIS:
255 case MISCREG_TLBIMVA:
256 warn("Need to flush all TLBs in MP\n");
257 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
258 bits(newVal, 7,0));
259 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
260 bits(newVal, 7,0));
261 return;
262 case MISCREG_TLBIASIDIS:
263 case MISCREG_TLBIASID:
264 warn("Need to flush all TLBs in MP\n");
265 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
266 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
267 return;
268 case MISCREG_TLBIMVAAIS:
269 case MISCREG_TLBIMVAA:
270 warn("Need to flush all TLBs in MP\n");
271 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
272 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
273 return;
274 case MISCREG_ITLBIMVA:
275 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
276 bits(newVal, 7,0));
277 return;
278 case MISCREG_DTLBIMVA:
279 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
280 bits(newVal, 7,0));
281 return;
282 case MISCREG_ITLBIASID:
283 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
284 return;
285 case MISCREG_DTLBIASID:
286 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
287 return;
288 }
289 }
290 setMiscRegNoEffect(misc_reg, newVal);
291}
292
293}