interrupts.hh (9656:06ec4e8fc7cd) interrupts.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010,2012 ARM Limited
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 31 unchanged lines hidden (view full) ---

42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/registers.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 31 unchanged lines hidden (view full) ---

42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/registers.hh"
50#include "arch/arm/utility.hh"
50#include "cpu/thread_context.hh"
51#include "debug/Interrupt.hh"
52#include "params/ArmInterrupts.hh"
53#include "sim/sim_object.hh"
54
55namespace ArmISA
56{
57

--- 60 unchanged lines hidden (view full) ---

118 void
119 clearAll()
120 {
121 DPRINTF(Interrupt, "Interrupts all cleared\n");
122 intStatus = 0;
123 memset(interrupts, 0, sizeof(interrupts));
124 }
125
51#include "cpu/thread_context.hh"
52#include "debug/Interrupt.hh"
53#include "params/ArmInterrupts.hh"
54#include "sim/sim_object.hh"
55
56namespace ArmISA
57{
58

--- 60 unchanged lines hidden (view full) ---

119 void
120 clearAll()
121 {
122 DPRINTF(Interrupt, "Interrupts all cleared\n");
123 intStatus = 0;
124 memset(interrupts, 0, sizeof(interrupts));
125 }
126
127 enum InterruptMask {
128 INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
129 INT_MASK_T, // taken regardless of mask
130 INT_MASK_P // pending
131 };
132
133 bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
134
126 bool
127 checkInterrupts(ThreadContext *tc) const
128 {
135 bool
136 checkInterrupts(ThreadContext *tc) const
137 {
129 if (!intStatus)
138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
139
140 if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
130 return false;
131
132 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
141 return false;
142
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
144 SCR scr = tc->readMiscReg(MISCREG_SCR);
133
145
134 return ((interrupts[INT_IRQ] && !cpsr.i) ||
135 (interrupts[INT_FIQ] && !cpsr.f) ||
136 (interrupts[INT_ABT] && !cpsr.a) ||
137 (interrupts[INT_RST]) ||
138 (interrupts[INT_SEV]));
146 bool isHypMode = cpsr.mode == MODE_HYP;
147 bool isSecure = inSecureState(scr, cpsr);
148 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
149 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
150 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
151
152 bool take_irq = takeInt(tc, INT_IRQ);
153 bool take_fiq = takeInt(tc, INT_FIQ);
154 bool take_ea = takeInt(tc, INT_ABT);
155
156 return ((interrupts[INT_IRQ] && take_irq) ||
157 (interrupts[INT_FIQ] && take_fiq) ||
158 (interrupts[INT_ABT] && take_ea) ||
159 ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
160 ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
161 (hcr.va && allowVAbort) ||
162 (interrupts[INT_RST]) ||
163 (interrupts[INT_SEV])
164 );
139 }
140
141 /**
165 }
166
167 /**
142 * Check the raw interrupt state.
143 * This function is used to check if a wfi operation should sleep. If there
144 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
145 * @return any interrupts pending
146 */
147 bool
168 * This function is used to check if a wfi operation should sleep. If there
169 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
170 * @return any interrupts pending
171 */
172 bool
148 checkRaw() const
173 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
149 {
174 {
150 return intStatus;
175 uint64_t maskedIntStatus;
176 bool virtWake;
177
178 maskedIntStatus = intStatus & ~((1 << INT_VIRT_IRQ) |
179 (1 << INT_VIRT_FIQ));
180 virtWake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
181 virtWake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
182 virtWake |= hcr.va && hcr.amo;
183 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
184 return maskedIntStatus || virtWake;
151 }
152
185 }
186
187 uint32_t
188 getISR(HCR hcr, CPSR cpsr, SCR scr)
189 {
190 bool useHcrMux;
191 CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
192
193 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
194 isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
195 : interrupts[INT_IRQ];
196 isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
197 : interrupts[INT_FIQ];
198 isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
199 return isr;
200 }
201
153 /**
154 * Check the state of a particular interrupt, ignoring CPSR masks.
155 *
156 * This method is primarily used when running the target CPU in a
157 * hardware VM (e.g., KVM) to check if interrupts should be
158 * delivered upon guest entry.
159 *
160 * @param interrupt Interrupt type to check the state of.

--- 6 unchanged lines hidden (view full) ---

167 panic("Interrupt number out of range.\n");
168
169 return interrupts[interrupt];
170 }
171
172 Fault
173 getInterrupt(ThreadContext *tc)
174 {
202 /**
203 * Check the state of a particular interrupt, ignoring CPSR masks.
204 *
205 * This method is primarily used when running the target CPU in a
206 * hardware VM (e.g., KVM) to check if interrupts should be
207 * delivered upon guest entry.
208 *
209 * @param interrupt Interrupt type to check the state of.

--- 6 unchanged lines hidden (view full) ---

216 panic("Interrupt number out of range.\n");
217
218 return interrupts[interrupt];
219 }
220
221 Fault
222 getInterrupt(ThreadContext *tc)
223 {
175 if (!intStatus)
224 HCR hcr = tc->readMiscReg(MISCREG_HCR);
225 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
226 SCR scr = tc->readMiscReg(MISCREG_SCR);
227
228 // Calculate a few temp vars so we can work out if there's a pending
229 // virtual interrupt, and if its allowed to happen
230 // ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
231 bool isHypMode = cpsr.mode == MODE_HYP;
232 bool isSecure = inSecureState(scr, cpsr);
233 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
234 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
235 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
236
237 if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
238 (hcr.va && allowVAbort)) )
176 return NoFault;
177
239 return NoFault;
240
178 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
241 bool take_irq = takeInt(tc, INT_IRQ);
242 bool take_fiq = takeInt(tc, INT_FIQ);
243 bool take_ea = takeInt(tc, INT_ABT);
179
244
180 if (interrupts[INT_IRQ] && !cpsr.i)
245
246 if (interrupts[INT_IRQ] && take_irq)
181 return new Interrupt;
247 return new Interrupt;
182 if (interrupts[INT_FIQ] && !cpsr.f)
248 if ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq)
249 return new VirtualInterrupt;
250 if (interrupts[INT_FIQ] && take_fiq)
183 return new FastInterrupt;
251 return new FastInterrupt;
184 if (interrupts[INT_ABT] && !cpsr.a)
185 return new DataAbort(0, false, 0,
186 ArmFault::AsynchronousExternalAbort);
252 if ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq)
253 return new VirtualFastInterrupt;
254 if (interrupts[INT_ABT] && take_ea)
255 return new SystemError;
256 if (hcr.va && allowVAbort)
257 return new VirtualDataAbort(0, TlbEntry::DomainType::NoAccess, false,
258 ArmFault::AsynchronousExternalAbort);
187 if (interrupts[INT_RST])
259 if (interrupts[INT_RST])
188 return new Reset;
260 return new Reset;
189 if (interrupts[INT_SEV])
261 if (interrupts[INT_SEV])
190 return new ArmSev;
262 return new ArmSev;
191
192 panic("intStatus and interrupts not in sync\n");
193 }
194
195 void
196 updateIntrInfo(ThreadContext *tc)
197 {
198 ; // nothing to do

--- 19 unchanged lines hidden --- 		263
264 panic("intStatus and interrupts not in sync\n");
265 }
266
267 void
268 updateIntrInfo(ThreadContext *tc)
269 {
270 ; // nothing to do

--- 19 unchanged lines hidden ---