interrupts.hh (6757:d86d3d6e5326) interrupts.hh (7400:f6c9b27c4dbe)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2006 The Regents of The University of Michigan
14 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 ARM Limited
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the

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29 * Authors: Ali Saidi
30 */
31
32#ifndef __ARCH_ARM_INTERRUPT_HH__
33#define __ARCH_ARM_INTERRUPT_HH__
34
35#include "arch/arm/faults.hh"
36#include "arch/arm/isa_traits.hh"
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the

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40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
37#include "arch/arm/registers.hh"
38#include "cpu/thread_context.hh"
39#include "params/ArmInterrupts.hh"
40#include "sim/sim_object.hh"
41
42namespace ArmISA
43{
44
45class Interrupts : public SimObject
46{
47 private:
48 BaseCPU * cpu;
49
49#include "arch/arm/registers.hh"
50#include "cpu/thread_context.hh"
51#include "params/ArmInterrupts.hh"
52#include "sim/sim_object.hh"
53
54namespace ArmISA
55{
56
57class Interrupts : public SimObject
58{
59 private:
60 BaseCPU * cpu;
61
62 bool interrupts[NumInterruptTypes];
50 uint64_t intStatus;
51
52 public:
53
54 void
55 setCPU(BaseCPU * _cpu)
56 {
57 cpu = _cpu;

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69 {
70 clearAll();
71 }
72
73
74 void
75 post(int int_num, int index)
76 {
63 uint64_t intStatus;
64
65 public:
66
67 void
68 setCPU(BaseCPU * _cpu)
69 {
70 cpu = _cpu;

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82 {
83 clearAll();
84 }
85
86
87 void
88 post(int int_num, int index)
89 {
90 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
91
92 if (int_num < 0 || int_num >= NumInterruptTypes)
93 panic("int_num out of bounds\n");
94
95 if (index != 0)
96 panic("No support for other interrupt indexes\n");
97
98 interrupts[int_num] = true;
99 intStatus |= ULL(1) << int_num;
77 }
78
79 void
80 clear(int int_num, int index)
81 {
100 }
101
102 void
103 clear(int int_num, int index)
104 {
105 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
106
107 if (int_num < 0 || int_num >= NumInterruptTypes)
108 panic("int_num out of bounds\n");
109
110 if (index != 0)
111 panic("No support for other interrupt indexes\n");
112
113 interrupts[int_num] = false;
114 intStatus &= ~(ULL(1) << int_num);
115
82 }
83
84 void
85 clearAll()
86 {
116 }
117
118 void
119 clearAll()
120 {
121 DPRINTF(Interrupt, "Interrupts all cleared\n");
87 intStatus = 0;
122 intStatus = 0;
123 memset(interrupts, 0, sizeof(interrupts));
88 }
89
90 bool
91 checkInterrupts(ThreadContext *tc) const
92 {
124 }
125
126 bool
127 checkInterrupts(ThreadContext *tc) const
128 {
93 return intStatus;
129 if (!intStatus)
130 return false;
131
132 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
133
134 return ((interrupts[INT_IRQ] && !cpsr.i) ||
135 (interrupts[INT_FIQ] && !cpsr.f) ||
136 (interrupts[INT_ABT] && !cpsr.a) ||
137 (interrupts[INT_RST]));
94 }
95
96 Fault
97 getInterrupt(ThreadContext *tc)
98 {
138 }
139
140 Fault
141 getInterrupt(ThreadContext *tc)
142 {
99 warn_once("ARM Interrupts not handled\n");
100 return NoFault;
143 if (!intStatus)
144 return NoFault;
145
146 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
147
148 if (interrupts[INT_IRQ] && !cpsr.i)
149 return new Interrupt;
150 if (interrupts[INT_FIQ] && !cpsr.f)
151 return new FastInterrupt;
152 if (interrupts[INT_ABT] && !cpsr.a)
153 return new DataAbort(0, false, 0,
154 ArmFault::AsynchronousExternalAbort);
155 if (interrupts[INT_RST])
156 return new Reset;
157
158 panic("intStatus and interrupts not in sync\n");
101 }
102
103 void
104 updateIntrInfo(ThreadContext *tc)
105 {
159 }
160
161 void
162 updateIntrInfo(ThreadContext *tc)
163 {
106
164 ; // nothing to do
107 }
108
109 void
110 serialize(std::ostream &os)
111 {
165 }
166
167 void
168 serialize(std::ostream &os)
169 {
170 SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
171 SERIALIZE_SCALAR(intStatus);
112 }
113
114 void
115 unserialize(Checkpoint *cp, const std::string &section)
116 {
172 }
173
174 void
175 unserialize(Checkpoint *cp, const std::string &section)
176 {
177 UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
178 UNSERIALIZE_SCALAR(intStatus);
117 }
118};
119} // namespace ARM_ISA
120
121#endif // __ARCH_ARM_INTERRUPT_HH__
179 }
180};
181} // namespace ARM_ISA
182
183#endif // __ARCH_ARM_INTERRUPT_HH__