interrupts.hh (11581:d6cfd0be73b2) interrupts.hh (13640:16606ea0ede6)
1/*
2 * Copyright (c) 2010, 2012-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137 {
138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
139
140 if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
141 return false;
142
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
144
1/*
2 * Copyright (c) 2010, 2012-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 128 unchanged lines hidden (view full) ---

137 {
138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
139
140 if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
141 return false;
142
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
144
145 bool isHypMode = cpsr.mode == MODE_HYP;
145 bool isHypMode = currEL(tc) == EL2;
146 bool isSecure = inSecureState(tc);
147 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
148 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
149 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
150
151 if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
152 (hcr.va && allowVAbort)) )
153 return false;

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227 assert(checkInterrupts(tc));
228
229 HCR hcr = tc->readMiscReg(MISCREG_HCR);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
231
232 // Calculate a few temp vars so we can work out if there's a pending
233 // virtual interrupt, and if its allowed to happen
234 // ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
146 bool isSecure = inSecureState(tc);
147 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
148 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
149 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
150
151 if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
152 (hcr.va && allowVAbort)) )
153 return false;

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227 assert(checkInterrupts(tc));
228
229 HCR hcr = tc->readMiscReg(MISCREG_HCR);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
231
232 // Calculate a few temp vars so we can work out if there's a pending
233 // virtual interrupt, and if its allowed to happen
234 // ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
235 bool isHypMode = cpsr.mode == MODE_HYP;
235 bool isHypMode = currEL(tc) == EL2;
236 bool isSecure = inSecureState(tc);
237 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
238 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
239 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
240
241 bool take_irq = takeInt(tc, INT_IRQ);
242 bool take_fiq = takeInt(tc, INT_FIQ);
243 bool take_ea = takeInt(tc, INT_ABT);

--- 46 unchanged lines hidden --- 		236 bool isSecure = inSecureState(tc);
237 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
238 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
239 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
240
241 bool take_irq = takeInt(tc, INT_IRQ);
242 bool take_fiq = takeInt(tc, INT_FIQ);
243 bool take_ea = takeInt(tc, INT_ABT);

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