1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/registers.hh"
50#include "arch/arm/utility.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Interrupt.hh"
53#include "params/ArmInterrupts.hh"
54#include "sim/sim_object.hh"
55
56namespace ArmISA
57{
58
59class Interrupts : public SimObject
60{
61 private:
62 BaseCPU * cpu;
63
64 bool interrupts[NumInterruptTypes];
65 uint64_t intStatus;
66
67 public:
68
69 void
70 setCPU(BaseCPU * _cpu)
71 {
72 cpu = _cpu;
73 }
74
75 typedef ArmInterruptsParams Params;
76
77 const Params *
78 params() const
79 {
80 return dynamic_cast<const Params *>(_params);
81 }
82
83 Interrupts(Params * p) : SimObject(p), cpu(NULL)
84 {
85 clearAll();
86 }
87
88
89 void
90 post(int int_num, int index)
91 {
92 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
93
94 if (int_num < 0 || int_num >= NumInterruptTypes)
95 panic("int_num out of bounds\n");
96
97 if (index != 0)
98 panic("No support for other interrupt indexes\n");
99
100 interrupts[int_num] = true;
101 intStatus |= ULL(1) << int_num;
102 }
103
104 void
105 clear(int int_num, int index)
106 {
107 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
108
109 if (int_num < 0 || int_num >= NumInterruptTypes)
110 panic("int_num out of bounds\n");
111
112 if (index != 0)
113 panic("No support for other interrupt indexes\n");
114
115 interrupts[int_num] = false;
116 intStatus &= ~(ULL(1) << int_num);
117 }
118
119 void
120 clearAll()
121 {
122 DPRINTF(Interrupt, "Interrupts all cleared\n");
123 intStatus = 0;
124 memset(interrupts, 0, sizeof(interrupts));
125 }
126
127 enum InterruptMask {
128 INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
129 INT_MASK_T, // taken regardless of mask
130 INT_MASK_P // pending
131 };
132
133 bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
134
135 bool
136 checkInterrupts(ThreadContext *tc) const
137 {
138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
139
140 if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
141 return false;
142
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
144 SCR scr = tc->readMiscReg(MISCREG_SCR);
145
146 bool isHypMode = cpsr.mode == MODE_HYP;
147 bool isSecure = inSecureState(scr, cpsr);
148 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
149 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
150 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
151
152 bool take_irq = takeInt(tc, INT_IRQ);
153 bool take_fiq = takeInt(tc, INT_FIQ);
154 bool take_ea = takeInt(tc, INT_ABT);
155
156 return ((interrupts[INT_IRQ] && take_irq) ||
157 (interrupts[INT_FIQ] && take_fiq) ||
158 (interrupts[INT_ABT] && take_ea) ||
159 ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
160 ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
161 (hcr.va && allowVAbort) ||
162 (interrupts[INT_RST]) ||
163 (interrupts[INT_SEV])
164 );
165 }
166
167 /**
168 * This function is used to check if a wfi operation should sleep. If there
169 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
170 * @return any interrupts pending
171 */
172 bool
173 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
174 {
175 uint64_t maskedIntStatus;
176 bool virtWake;
177
178 maskedIntStatus = intStatus & ~((1 << INT_VIRT_IRQ) |
179 (1 << INT_VIRT_FIQ));
180 virtWake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
181 virtWake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
182 virtWake |= hcr.va && hcr.amo;
183 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
184 return maskedIntStatus || virtWake;
185 }
186
187 uint32_t
188 getISR(HCR hcr, CPSR cpsr, SCR scr)
189 {
190 bool useHcrMux;
191 CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
192
193 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
194 isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
195 : interrupts[INT_IRQ];
196 isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
197 : interrupts[INT_FIQ];
198 isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
199 return isr;
200 }
201
202 /**
203 * Check the state of a particular interrupt, ignoring CPSR masks.
204 *
205 * This method is primarily used when running the target CPU in a
206 * hardware VM (e.g., KVM) to check if interrupts should be
207 * delivered upon guest entry.
208 *
209 * @param interrupt Interrupt type to check the state of.
210 * @return true if the interrupt is asserted, false otherwise.
211 */
212 bool
213 checkRaw(InterruptTypes interrupt) const
214 {
215 if (interrupt >= NumInterruptTypes)
216 panic("Interrupt number out of range.\n");
217
218 return interrupts[interrupt];
219 }
220
221 Fault
222 getInterrupt(ThreadContext *tc)
223 {
224 HCR hcr = tc->readMiscReg(MISCREG_HCR);
225 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
226 SCR scr = tc->readMiscReg(MISCREG_SCR);
227
228 // Calculate a few temp vars so we can work out if there's a pending
229 // virtual interrupt, and if its allowed to happen
230 // ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
231 bool isHypMode = cpsr.mode == MODE_HYP;
232 bool isSecure = inSecureState(scr, cpsr);
233 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
234 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
235 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
236
237 if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
238 (hcr.va && allowVAbort)) )
239 return NoFault;
240
241 bool take_irq = takeInt(tc, INT_IRQ);
242 bool take_fiq = takeInt(tc, INT_FIQ);
243 bool take_ea = takeInt(tc, INT_ABT);
244
245
246 if (interrupts[INT_IRQ] && take_irq)
247 return std::make_shared<Interrupt>();
248 if ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq)
249 return std::make_shared<VirtualInterrupt>();
250 if (interrupts[INT_FIQ] && take_fiq)
251 return std::make_shared<FastInterrupt>();
252 if ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq)
253 return std::make_shared<VirtualFastInterrupt>();
254 if (interrupts[INT_ABT] && take_ea)
255 return std::make_shared<SystemError>();
256 if (hcr.va && allowVAbort)
257 return std::make_shared<VirtualDataAbort>(
258 0, TlbEntry::DomainType::NoAccess, false,
259 ArmFault::AsynchronousExternalAbort);
260 if (interrupts[INT_RST])
261 return std::make_shared<Reset>();
262 if (interrupts[INT_SEV])
263 return std::make_shared<ArmSev>();
264
265 panic("intStatus and interrupts not in sync\n");
266 }
267
268 void
269 updateIntrInfo(ThreadContext *tc)
270 {
271 ; // nothing to do
272 }
273
274 void
| 1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/registers.hh"
50#include "arch/arm/utility.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Interrupt.hh"
53#include "params/ArmInterrupts.hh"
54#include "sim/sim_object.hh"
55
56namespace ArmISA
57{
58
59class Interrupts : public SimObject
60{
61 private:
62 BaseCPU * cpu;
63
64 bool interrupts[NumInterruptTypes];
65 uint64_t intStatus;
66
67 public:
68
69 void
70 setCPU(BaseCPU * _cpu)
71 {
72 cpu = _cpu;
73 }
74
75 typedef ArmInterruptsParams Params;
76
77 const Params *
78 params() const
79 {
80 return dynamic_cast<const Params *>(_params);
81 }
82
83 Interrupts(Params * p) : SimObject(p), cpu(NULL)
84 {
85 clearAll();
86 }
87
88
89 void
90 post(int int_num, int index)
91 {
92 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
93
94 if (int_num < 0 || int_num >= NumInterruptTypes)
95 panic("int_num out of bounds\n");
96
97 if (index != 0)
98 panic("No support for other interrupt indexes\n");
99
100 interrupts[int_num] = true;
101 intStatus |= ULL(1) << int_num;
102 }
103
104 void
105 clear(int int_num, int index)
106 {
107 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
108
109 if (int_num < 0 || int_num >= NumInterruptTypes)
110 panic("int_num out of bounds\n");
111
112 if (index != 0)
113 panic("No support for other interrupt indexes\n");
114
115 interrupts[int_num] = false;
116 intStatus &= ~(ULL(1) << int_num);
117 }
118
119 void
120 clearAll()
121 {
122 DPRINTF(Interrupt, "Interrupts all cleared\n");
123 intStatus = 0;
124 memset(interrupts, 0, sizeof(interrupts));
125 }
126
127 enum InterruptMask {
128 INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
129 INT_MASK_T, // taken regardless of mask
130 INT_MASK_P // pending
131 };
132
133 bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
134
135 bool
136 checkInterrupts(ThreadContext *tc) const
137 {
138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
139
140 if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
141 return false;
142
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
144 SCR scr = tc->readMiscReg(MISCREG_SCR);
145
146 bool isHypMode = cpsr.mode == MODE_HYP;
147 bool isSecure = inSecureState(scr, cpsr);
148 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
149 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
150 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
151
152 bool take_irq = takeInt(tc, INT_IRQ);
153 bool take_fiq = takeInt(tc, INT_FIQ);
154 bool take_ea = takeInt(tc, INT_ABT);
155
156 return ((interrupts[INT_IRQ] && take_irq) ||
157 (interrupts[INT_FIQ] && take_fiq) ||
158 (interrupts[INT_ABT] && take_ea) ||
159 ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
160 ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
161 (hcr.va && allowVAbort) ||
162 (interrupts[INT_RST]) ||
163 (interrupts[INT_SEV])
164 );
165 }
166
167 /**
168 * This function is used to check if a wfi operation should sleep. If there
169 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
170 * @return any interrupts pending
171 */
172 bool
173 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
174 {
175 uint64_t maskedIntStatus;
176 bool virtWake;
177
178 maskedIntStatus = intStatus & ~((1 << INT_VIRT_IRQ) |
179 (1 << INT_VIRT_FIQ));
180 virtWake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
181 virtWake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
182 virtWake |= hcr.va && hcr.amo;
183 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
184 return maskedIntStatus || virtWake;
185 }
186
187 uint32_t
188 getISR(HCR hcr, CPSR cpsr, SCR scr)
189 {
190 bool useHcrMux;
191 CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
192
193 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
194 isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
195 : interrupts[INT_IRQ];
196 isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
197 : interrupts[INT_FIQ];
198 isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
199 return isr;
200 }
201
202 /**
203 * Check the state of a particular interrupt, ignoring CPSR masks.
204 *
205 * This method is primarily used when running the target CPU in a
206 * hardware VM (e.g., KVM) to check if interrupts should be
207 * delivered upon guest entry.
208 *
209 * @param interrupt Interrupt type to check the state of.
210 * @return true if the interrupt is asserted, false otherwise.
211 */
212 bool
213 checkRaw(InterruptTypes interrupt) const
214 {
215 if (interrupt >= NumInterruptTypes)
216 panic("Interrupt number out of range.\n");
217
218 return interrupts[interrupt];
219 }
220
221 Fault
222 getInterrupt(ThreadContext *tc)
223 {
224 HCR hcr = tc->readMiscReg(MISCREG_HCR);
225 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
226 SCR scr = tc->readMiscReg(MISCREG_SCR);
227
228 // Calculate a few temp vars so we can work out if there's a pending
229 // virtual interrupt, and if its allowed to happen
230 // ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
231 bool isHypMode = cpsr.mode == MODE_HYP;
232 bool isSecure = inSecureState(scr, cpsr);
233 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
234 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
235 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
236
237 if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
238 (hcr.va && allowVAbort)) )
239 return NoFault;
240
241 bool take_irq = takeInt(tc, INT_IRQ);
242 bool take_fiq = takeInt(tc, INT_FIQ);
243 bool take_ea = takeInt(tc, INT_ABT);
244
245
246 if (interrupts[INT_IRQ] && take_irq)
247 return std::make_shared<Interrupt>();
248 if ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq)
249 return std::make_shared<VirtualInterrupt>();
250 if (interrupts[INT_FIQ] && take_fiq)
251 return std::make_shared<FastInterrupt>();
252 if ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq)
253 return std::make_shared<VirtualFastInterrupt>();
254 if (interrupts[INT_ABT] && take_ea)
255 return std::make_shared<SystemError>();
256 if (hcr.va && allowVAbort)
257 return std::make_shared<VirtualDataAbort>(
258 0, TlbEntry::DomainType::NoAccess, false,
259 ArmFault::AsynchronousExternalAbort);
260 if (interrupts[INT_RST])
261 return std::make_shared<Reset>();
262 if (interrupts[INT_SEV])
263 return std::make_shared<ArmSev>();
264
265 panic("intStatus and interrupts not in sync\n");
266 }
267
268 void
269 updateIntrInfo(ThreadContext *tc)
270 {
271 ; // nothing to do
272 }
273
274 void
|