3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/interrupts.hh"
41
42#include "arch/arm/system.hh"
43
44ArmISA::Interrupts *
45ArmInterruptsParams::create()
46{
47 return new ArmISA::Interrupts(this);
48}
49
50bool
51ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
52{
53 // Table G1-17~19 of ARM V8 ARM
54 InterruptMask mask;
55 bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
56
57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
58 SCR scr;
59 HCR hcr;
60 hcr = tc->readMiscReg(MISCREG_HCR);
| 3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/interrupts.hh"
41
42#include "arch/arm/system.hh"
43
44ArmISA::Interrupts *
45ArmInterruptsParams::create()
46{
47 return new ArmISA::Interrupts(this);
48}
49
50bool
51ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
52{
53 // Table G1-17~19 of ARM V8 ARM
54 InterruptMask mask;
55 bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
56
57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
58 SCR scr;
59 HCR hcr;
60 hcr = tc->readMiscReg(MISCREG_HCR);
|
62 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
63
64 if (!highest_el_is_64)
65 scr = tc->readMiscReg(MISCREG_SCR);
66 else
67 scr = tc->readMiscReg(MISCREG_SCR_EL3);
68
69 bool is_secure = inSecureState(tc);
70
71 switch(int_type) {
72 case INT_FIQ:
73 cpsr_mask_bit = cpsr.f;
74 scr_routing_bit = scr.fiq;
75 scr_fwaw_bit = scr.fw;
76 hcr_mask_override_bit = hcr.fmo;
77 break;
78 case INT_IRQ:
79 cpsr_mask_bit = cpsr.i;
80 scr_routing_bit = scr.irq;
81 scr_fwaw_bit = 1;
82 hcr_mask_override_bit = hcr.imo;
83 break;
84 case INT_ABT:
85 cpsr_mask_bit = cpsr.a;
86 scr_routing_bit = scr.ea;
87 scr_fwaw_bit = scr.aw;
88 hcr_mask_override_bit = hcr.amo;
89 break;
90 default:
91 panic("Unhandled interrupt type!");
92 }
93
94 if (hcr.tge)
95 hcr_mask_override_bit = 1;
96
97 if (!highest_el_is_64) {
98 // AArch32
99 if (!scr_routing_bit) {
100 // SCR IRQ == 0
101 if (!hcr_mask_override_bit)
102 mask = INT_MASK_M;
103 else {
104 if (!is_secure && (el == EL0 || el == EL1))
105 mask = INT_MASK_T;
106 else
107 mask = INT_MASK_M;
108 }
109 } else {
110 // SCR IRQ == 1
111 if ((!is_secure) &&
112 (hcr_mask_override_bit ||
113 (!scr_fwaw_bit && !hcr_mask_override_bit)))
114 mask = INT_MASK_T;
115 else
116 mask = INT_MASK_M;
117 }
118 } else {
119 // AArch64
120 if (!scr_routing_bit) {
121 // SCR IRQ == 0
122 if (!scr.rw) {
123 // SCR RW == 0
124 if (!hcr_mask_override_bit) {
125 if (el == EL3)
126 mask = INT_MASK_P;
127 else
128 mask = INT_MASK_M;
129 } else {
130 if (el == EL3)
131 mask = INT_MASK_T;
132 else if (is_secure || el == EL2)
133 mask = INT_MASK_M;
134 else
135 mask = INT_MASK_T;
136 }
137 } else {
138 // SCR RW == 1
139 if (!hcr_mask_override_bit) {
140 if (el == EL3 || el == EL2)
141 mask = INT_MASK_P;
142 else
143 mask = INT_MASK_M;
144 } else {
145 if (el == EL3)
146 mask = INT_MASK_P;
147 else if (is_secure || el == EL2)
148 mask = INT_MASK_M;
149 else
150 mask = INT_MASK_T;
151 }
152 }
153 } else {
154 // SCR IRQ == 1
155 if (el == EL3)
156 mask = INT_MASK_M;
157 else
158 mask = INT_MASK_T;
159 }
160 }
161
162 return ((mask == INT_MASK_T) ||
163 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
164 (mask != INT_MASK_P);
165}
166
| 62 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
63
64 if (!highest_el_is_64)
65 scr = tc->readMiscReg(MISCREG_SCR);
66 else
67 scr = tc->readMiscReg(MISCREG_SCR_EL3);
68
69 bool is_secure = inSecureState(tc);
70
71 switch(int_type) {
72 case INT_FIQ:
73 cpsr_mask_bit = cpsr.f;
74 scr_routing_bit = scr.fiq;
75 scr_fwaw_bit = scr.fw;
76 hcr_mask_override_bit = hcr.fmo;
77 break;
78 case INT_IRQ:
79 cpsr_mask_bit = cpsr.i;
80 scr_routing_bit = scr.irq;
81 scr_fwaw_bit = 1;
82 hcr_mask_override_bit = hcr.imo;
83 break;
84 case INT_ABT:
85 cpsr_mask_bit = cpsr.a;
86 scr_routing_bit = scr.ea;
87 scr_fwaw_bit = scr.aw;
88 hcr_mask_override_bit = hcr.amo;
89 break;
90 default:
91 panic("Unhandled interrupt type!");
92 }
93
94 if (hcr.tge)
95 hcr_mask_override_bit = 1;
96
97 if (!highest_el_is_64) {
98 // AArch32
99 if (!scr_routing_bit) {
100 // SCR IRQ == 0
101 if (!hcr_mask_override_bit)
102 mask = INT_MASK_M;
103 else {
104 if (!is_secure && (el == EL0 || el == EL1))
105 mask = INT_MASK_T;
106 else
107 mask = INT_MASK_M;
108 }
109 } else {
110 // SCR IRQ == 1
111 if ((!is_secure) &&
112 (hcr_mask_override_bit ||
113 (!scr_fwaw_bit && !hcr_mask_override_bit)))
114 mask = INT_MASK_T;
115 else
116 mask = INT_MASK_M;
117 }
118 } else {
119 // AArch64
120 if (!scr_routing_bit) {
121 // SCR IRQ == 0
122 if (!scr.rw) {
123 // SCR RW == 0
124 if (!hcr_mask_override_bit) {
125 if (el == EL3)
126 mask = INT_MASK_P;
127 else
128 mask = INT_MASK_M;
129 } else {
130 if (el == EL3)
131 mask = INT_MASK_T;
132 else if (is_secure || el == EL2)
133 mask = INT_MASK_M;
134 else
135 mask = INT_MASK_T;
136 }
137 } else {
138 // SCR RW == 1
139 if (!hcr_mask_override_bit) {
140 if (el == EL3 || el == EL2)
141 mask = INT_MASK_P;
142 else
143 mask = INT_MASK_M;
144 } else {
145 if (el == EL3)
146 mask = INT_MASK_P;
147 else if (is_secure || el == EL2)
148 mask = INT_MASK_M;
149 else
150 mask = INT_MASK_T;
151 }
152 }
153 } else {
154 // SCR IRQ == 1
155 if (el == EL3)
156 mask = INT_MASK_M;
157 else
158 mask = INT_MASK_T;
159 }
160 }
161
162 return ((mask == INT_MASK_T) ||
163 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
164 (mask != INT_MASK_P);
165}
166
|