vfp.hh (7382:b3c768629a54) | vfp.hh (7384:f12b4f28e5eb) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40#ifndef __ARCH_ARM_INSTS_VFP_HH__ 41#define __ARCH_ARM_INSTS_VFP_HH__ 42 43#include "arch/arm/insts/misc.hh" 44#include "arch/arm/miscregs.hh" 45#include <fenv.h> 46#include <cmath> 47 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40#ifndef __ARCH_ARM_INSTS_VFP_HH__ 41#define __ARCH_ARM_INSTS_VFP_HH__ 42 43#include "arch/arm/insts/misc.hh" 44#include "arch/arm/miscregs.hh" 45#include <fenv.h> 46#include <cmath> 47 |
48namespace ArmISA 49{ 50 |
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48enum VfpMicroMode { 49 VfpNotAMicroop, 50 VfpMicroop, 51 VfpFirstMicroop, 52 VfpLastMicroop 53}; 54 55template<class T> --- 61 unchanged lines hidden (view full) --- 117template <class fpType> 118static inline void 119vfpFlushToZero(uint32_t &fpscr, fpType &op1, fpType &op2) 120{ 121 vfpFlushToZero(fpscr, op1); 122 vfpFlushToZero(fpscr, op2); 123} 124 | 51enum VfpMicroMode { 52 VfpNotAMicroop, 53 VfpMicroop, 54 VfpFirstMicroop, 55 VfpLastMicroop 56}; 57 58template<class T> --- 61 unchanged lines hidden (view full) --- 120template <class fpType> 121static inline void 122vfpFlushToZero(uint32_t &fpscr, fpType &op1, fpType &op2) 123{ 124 vfpFlushToZero(fpscr, op1); 125 vfpFlushToZero(fpscr, op2); 126} 127 |
128static inline uint32_t 129fpToBits(float fp) 130{ 131 union 132 { 133 float fp; 134 uint32_t bits; 135 } val; 136 val.fp = fp; 137 return val.bits; 138} 139 |
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125static inline uint64_t | 140static inline uint64_t |
141fpToBits(double fp) 142{ 143 union 144 { 145 double fp; 146 uint64_t bits; 147 } val; 148 val.fp = fp; 149 return val.bits; 150} 151 152static inline float 153bitsToFp(uint64_t bits, float junk) 154{ 155 union 156 { 157 float fp; 158 uint32_t bits; 159 } val; 160 val.bits = bits; 161 return val.fp; 162} 163 164static inline double 165bitsToFp(uint64_t bits, double junk) 166{ 167 union 168 { 169 double fp; 170 uint64_t bits; 171 } val; 172 val.bits = bits; 173 return val.fp; 174} 175 176template <class fpType> 177static inline fpType 178fixNan(FPSCR fpscr, fpType val, fpType op1, fpType op2) 179{ 180 if (std::isnan(val)) { 181 const bool single = (sizeof(val) == sizeof(float)); 182 const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000); 183 const bool nan1 = std::isnan(op1); 184 const bool nan2 = std::isnan(op2); 185 const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan); 186 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan); 187 fpType junk = 0.0; 188 if ((!nan1 && !nan2) || (fpscr.dn == 1)) { 189 val = bitsToFp(qnan, junk); 190 } else if (signal1) { 191 val = bitsToFp(fpToBits(op1) | qnan, junk); 192 } else if (signal2) { 193 val = bitsToFp(fpToBits(op2) | qnan, junk); 194 } else if (nan1) { 195 val = op1; 196 } else if (nan2) { 197 val = op2; 198 } 199 } 200 return val; 201} 202 203static inline uint64_t |
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126vfpFpSToFixed(float val, bool isSigned, bool half, uint8_t imm) 127{ 128 fesetround(FeRoundZero); 129 val = val * powf(2.0, imm); 130 __asm__ __volatile__("" : "=m" (val) : "m" (val)); 131 feclearexcept(FeAllExceptions); 132 __asm__ __volatile__("" : "=m" (val) : "m" (val)); 133 float origVal = val; --- 342 unchanged lines hidden (view full) --- 476 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 477 VfpMicroMode mode = VfpNotAMicroop) : 478 RegRegRegOp(mnem, _machInst, __opClass, _dest, _op1, _op2) 479 { 480 setVfpMicroFlags(mode, flags); 481 } 482}; 483 | 204vfpFpSToFixed(float val, bool isSigned, bool half, uint8_t imm) 205{ 206 fesetround(FeRoundZero); 207 val = val * powf(2.0, imm); 208 __asm__ __volatile__("" : "=m" (val) : "m" (val)); 209 feclearexcept(FeAllExceptions); 210 __asm__ __volatile__("" : "=m" (val) : "m" (val)); 211 float origVal = val; --- 342 unchanged lines hidden (view full) --- 554 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 555 VfpMicroMode mode = VfpNotAMicroop) : 556 RegRegRegOp(mnem, _machInst, __opClass, _dest, _op1, _op2) 557 { 558 setVfpMicroFlags(mode, flags); 559 } 560}; 561 |
562} 563 |
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484#endif //__ARCH_ARM_INSTS_VFP_HH__ | 564#endif //__ARCH_ARM_INSTS_VFP_HH__ |