vfp.hh (7376:3b781776b2d9) vfp.hh (7378:de704acd042f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_VFP_HH__
41#define __ARCH_ARM_INSTS_VFP_HH__
42
43#include "arch/arm/insts/misc.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_VFP_HH__
41#define __ARCH_ARM_INSTS_VFP_HH__
42
43#include "arch/arm/insts/misc.hh"
44#include "arch/arm/miscregs.hh"
45#include <fenv.h>
44
45enum VfpMicroMode {
46 VfpNotAMicroop,
47 VfpMicroop,
48 VfpFirstMicroop,
49 VfpLastMicroop
50};
51

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68 case VfpNotAMicroop:
69 break;
70 }
71 if (mode == VfpMicroop || mode == VfpFirstMicroop) {
72 flags[StaticInst::IsDelayedCommit] = true;
73 }
74}
75
46
47enum VfpMicroMode {
48 VfpNotAMicroop,
49 VfpMicroop,
50 VfpFirstMicroop,
51 VfpLastMicroop
52};
53

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70 case VfpNotAMicroop:
71 break;
72 }
73 if (mode == VfpMicroop || mode == VfpFirstMicroop) {
74 flags[StaticInst::IsDelayedCommit] = true;
75 }
76}
77
78enum FeExceptionBit
79{
80 FeDivByZero = FE_DIVBYZERO,
81 FeInexact = FE_INEXACT,
82 FeInvalid = FE_INVALID,
83 FeOverflow = FE_OVERFLOW,
84 FeUnderflow = FE_UNDERFLOW,
85 FeAllExceptions = FE_ALL_EXCEPT
86};
87
88enum FeRoundingMode
89{
90 FeRoundDown = FE_DOWNWARD,
91 FeRoundNearest = FE_TONEAREST,
92 FeRoundZero = FE_TOWARDZERO,
93 FeRoundUpward = FE_UPWARD
94};
95
96enum VfpRoundingMode
97{
98 VfpRoundNearest = 0,
99 VfpRoundUpward = 1,
100 VfpRoundDown = 2,
101 VfpRoundZero = 3
102};
103
104typedef int VfpSavedState;
105
106static inline VfpSavedState
107prepVfpFpscr(FPSCR fpscr)
108{
109 int roundingMode = fegetround();
110 feclearexcept(FeAllExceptions);
111 switch (fpscr.rMode) {
112 case VfpRoundNearest:
113 fesetround(FeRoundNearest);
114 break;
115 case VfpRoundUpward:
116 fesetround(FeRoundUpward);
117 break;
118 case VfpRoundDown:
119 fesetround(FeRoundDown);
120 break;
121 case VfpRoundZero:
122 fesetround(FeRoundZero);
123 break;
124 }
125 return roundingMode;
126}
127
128static inline FPSCR
129setVfpFpscr(FPSCR fpscr, VfpSavedState state)
130{
131 int exceptions = fetestexcept(FeAllExceptions);
132 if (exceptions & FeInvalid) {
133 fpscr.ioc = 1;
134 }
135 if (exceptions & FeDivByZero) {
136 fpscr.dzc = 1;
137 }
138 if (exceptions & FeOverflow) {
139 fpscr.ofc = 1;
140 }
141 if (exceptions & FeUnderflow) {
142 fpscr.ufc = 1;
143 }
144 if (exceptions & FeInexact) {
145 fpscr.ixc = 1;
146 }
147 fesetround(state);
148 return fpscr;
149}
150
76class VfpMacroOp : public PredMacroOp
77{
78 public:
79 static bool
80 inScalarBank(IntRegIndex idx)
81 {
82 return (idx % 32) < 8;
83 }

--- 103 unchanged lines hidden --- 		151class VfpMacroOp : public PredMacroOp
152{
153 public:
154 static bool
155 inScalarBank(IntRegIndex idx)
156 {
157 return (idx % 32) < 8;
158 }

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