vfp.cc (11671:520509f3e66c) vfp.cc (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46 */
47
48std::string
49FpCondCompRegOp::generateDisassembly(
50 Addr pc, const SymbolTable *symtab) const
51{
52 std::stringstream ss;
53 printMnemonic(ss, "", false);
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46 */
47
48std::string
49FpCondCompRegOp::generateDisassembly(
50 Addr pc, const SymbolTable *symtab) const
51{
52 std::stringstream ss;
53 printMnemonic(ss, "", false);
54 printReg(ss, op1);
54 printIntReg(ss, op1);
55 ccprintf(ss, ", ");
55 ccprintf(ss, ", ");
56 printReg(ss, op2);
56 printIntReg(ss, op2);
57 ccprintf(ss, ", #%d", defCc);
58 ccprintf(ss, ", ");
59 printCondition(ss, condCode, true);
60 return ss.str();
61}
62
63std::string
64FpCondSelOp::generateDisassembly(
65 Addr pc, const SymbolTable *symtab) const
66{
67 std::stringstream ss;
68 printMnemonic(ss, "", false);
57 ccprintf(ss, ", #%d", defCc);
58 ccprintf(ss, ", ");
59 printCondition(ss, condCode, true);
60 return ss.str();
61}
62
63std::string
64FpCondSelOp::generateDisassembly(
65 Addr pc, const SymbolTable *symtab) const
66{
67 std::stringstream ss;
68 printMnemonic(ss, "", false);
69 printReg(ss, dest);
69 printIntReg(ss, dest);
70 ccprintf(ss, ", ");
70 ccprintf(ss, ", ");
71 printReg(ss, op1);
71 printIntReg(ss, op1);
72 ccprintf(ss, ", ");
72 ccprintf(ss, ", ");
73 printReg(ss, op2);
73 printIntReg(ss, op2);
74 ccprintf(ss, ", ");
75 printCondition(ss, condCode, true);
76 return ss.str();
77}
78
79std::string
80FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
81{
82 std::stringstream ss;
83 printMnemonic(ss);
74 ccprintf(ss, ", ");
75 printCondition(ss, condCode, true);
76 return ss.str();
77}
78
79std::string
80FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
81{
82 std::stringstream ss;
83 printMnemonic(ss);
84 printReg(ss, dest + FP_Reg_Base);
84 printFloatReg(ss, dest);
85 ss << ", ";
85 ss << ", ";
86 printReg(ss, op1 + FP_Reg_Base);
86 printFloatReg(ss, op1);
87 return ss.str();
88}
89
90std::string
91FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
92{
93 std::stringstream ss;
94 printMnemonic(ss);
87 return ss.str();
88}
89
90std::string
91FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
92{
93 std::stringstream ss;
94 printMnemonic(ss);
95 printReg(ss, dest + FP_Reg_Base);
95 printFloatReg(ss, dest);
96 ccprintf(ss, ", #%d", imm);
97 return ss.str();
98}
99
100std::string
101FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
102{
103 std::stringstream ss;
104 printMnemonic(ss);
96 ccprintf(ss, ", #%d", imm);
97 return ss.str();
98}
99
100std::string
101FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
102{
103 std::stringstream ss;
104 printMnemonic(ss);
105 printReg(ss, dest + FP_Reg_Base);
105 printFloatReg(ss, dest);
106 ss << ", ";
106 ss << ", ";
107 printReg(ss, op1 + FP_Reg_Base);
107 printFloatReg(ss, op1);
108 ccprintf(ss, ", #%d", imm);
109 return ss.str();
110}
111
112std::string
113FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
114{
115 std::stringstream ss;
116 printMnemonic(ss);
108 ccprintf(ss, ", #%d", imm);
109 return ss.str();
110}
111
112std::string
113FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
114{
115 std::stringstream ss;
116 printMnemonic(ss);
117 printReg(ss, dest + FP_Reg_Base);
117 printFloatReg(ss, dest);
118 ss << ", ";
118 ss << ", ";
119 printReg(ss, op1 + FP_Reg_Base);
119 printFloatReg(ss, op1);
120 ss << ", ";
120 ss << ", ";
121 printReg(ss, op2 + FP_Reg_Base);
121 printFloatReg(ss, op2);
122 return ss.str();
123}
124
125std::string
126FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
127 const
128{
129 std::stringstream ss;
130 printMnemonic(ss);
131 printCondition(ss, cond);
122 return ss.str();
123}
124
125std::string
126FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
127 const
128{
129 std::stringstream ss;
130 printMnemonic(ss);
131 printCondition(ss, cond);
132 printReg(ss, dest + FP_Reg_Base);
132 printFloatReg(ss, dest);
133 ss << ", ";
133 ss << ", ";
134 printReg(ss, op1 + FP_Reg_Base);
134 printFloatReg(ss, op1);
135 ss << ", ";
135 ss << ", ";
136 printReg(ss, op2 + FP_Reg_Base);
136 printFloatReg(ss, op2);
137 return ss.str();
138}
139
140std::string
141FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
142{
143 std::stringstream ss;
144 printMnemonic(ss);
137 return ss.str();
138}
139
140std::string
141FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
142{
143 std::stringstream ss;
144 printMnemonic(ss);
145 printReg(ss, dest + FP_Reg_Base);
145 printFloatReg(ss, dest);
146 ss << ", ";
146 ss << ", ";
147 printReg(ss, op1 + FP_Reg_Base);
147 printFloatReg(ss, op1);
148 ss << ", ";
148 ss << ", ";
149 printReg(ss, op2 + FP_Reg_Base);
149 printFloatReg(ss, op2);
150 ss << ", ";
150 ss << ", ";
151 printReg(ss, op3 + FP_Reg_Base);
151 printFloatReg(ss, op3);
152 return ss.str();
153}
154
155std::string
156FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157{
158 std::stringstream ss;
159 printMnemonic(ss);
152 return ss.str();
153}
154
155std::string
156FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157{
158 std::stringstream ss;
159 printMnemonic(ss);
160 printReg(ss, dest + FP_Reg_Base);
160 printFloatReg(ss, dest);
161 ss << ", ";
161 ss << ", ";
162 printReg(ss, op1 + FP_Reg_Base);
162 printFloatReg(ss, op1);
163 ss << ", ";
163 ss << ", ";
164 printReg(ss, op2 + FP_Reg_Base);
164 printFloatReg(ss, op2);
165 ccprintf(ss, ", #%d", imm);
166 return ss.str();
167}
168
169namespace ArmISA
170{
171
172VfpSavedState

--- 1017 unchanged lines hidden --- 		165 ccprintf(ss, ", #%d", imm);
166 return ss.str();
167}
168
169namespace ArmISA
170{
171
172VfpSavedState

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