1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46 */ 47 48std::string 49FpCondCompRegOp::generateDisassembly( 50 Addr pc, const SymbolTable *symtab) const 51{ 52 std::stringstream ss; 53 printMnemonic(ss, "", false); |
54 printIntReg(ss, op1); |
55 ccprintf(ss, ", "); |
56 printIntReg(ss, op2); |
57 ccprintf(ss, ", #%d", defCc); 58 ccprintf(ss, ", "); 59 printCondition(ss, condCode, true); 60 return ss.str(); 61} 62 63std::string 64FpCondSelOp::generateDisassembly( 65 Addr pc, const SymbolTable *symtab) const 66{ 67 std::stringstream ss; 68 printMnemonic(ss, "", false); |
69 printIntReg(ss, dest); |
70 ccprintf(ss, ", "); |
71 printIntReg(ss, op1); |
72 ccprintf(ss, ", "); |
73 printIntReg(ss, op2); |
74 ccprintf(ss, ", "); 75 printCondition(ss, condCode, true); 76 return ss.str(); 77} 78 79std::string 80FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 81{ 82 std::stringstream ss; 83 printMnemonic(ss); |
84 printFloatReg(ss, dest); |
85 ss << ", "; |
86 printFloatReg(ss, op1); |
87 return ss.str(); 88} 89 90std::string 91FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92{ 93 std::stringstream ss; 94 printMnemonic(ss); |
95 printFloatReg(ss, dest); |
96 ccprintf(ss, ", #%d", imm); 97 return ss.str(); 98} 99 100std::string 101FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 102{ 103 std::stringstream ss; 104 printMnemonic(ss); |
105 printFloatReg(ss, dest); |
106 ss << ", "; |
107 printFloatReg(ss, op1); |
108 ccprintf(ss, ", #%d", imm); 109 return ss.str(); 110} 111 112std::string 113FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 114{ 115 std::stringstream ss; 116 printMnemonic(ss); |
117 printFloatReg(ss, dest); |
118 ss << ", "; |
119 printFloatReg(ss, op1); |
120 ss << ", "; |
121 printFloatReg(ss, op2); |
122 return ss.str(); 123} 124 125std::string 126FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) 127 const 128{ 129 std::stringstream ss; 130 printMnemonic(ss); 131 printCondition(ss, cond); |
132 printFloatReg(ss, dest); |
133 ss << ", "; |
134 printFloatReg(ss, op1); |
135 ss << ", "; |
136 printFloatReg(ss, op2); |
137 return ss.str(); 138} 139 140std::string 141FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 142{ 143 std::stringstream ss; 144 printMnemonic(ss); |
145 printFloatReg(ss, dest); |
146 ss << ", "; |
147 printFloatReg(ss, op1); |
148 ss << ", "; |
149 printFloatReg(ss, op2); |
150 ss << ", "; |
151 printFloatReg(ss, op3); |
152 return ss.str(); 153} 154 155std::string 156FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 157{ 158 std::stringstream ss; 159 printMnemonic(ss); |
160 printFloatReg(ss, dest); |
161 ss << ", "; |
162 printFloatReg(ss, op1); |
163 ss << ", "; |
164 printFloatReg(ss, op2); |
165 ccprintf(ss, ", #%d", imm); 166 return ss.str(); 167} 168 169namespace ArmISA 170{ 171 172VfpSavedState --- 1017 unchanged lines hidden --- |