sve_macromem.hh (14091:090449e74135) sve_macromem.hh (14106:293e3f4b1321)
1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40#ifndef __ARCH_ARM_SVE_MACROMEM_HH__
41#define __ARCH_ARM_SVE_MACROMEM_HH__
42
43#include "arch/arm/generated/decoder.hh"
44#include "arch/arm/insts/pred_inst.hh"
45
46namespace ArmISA {
47
1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 31 unchanged lines hidden (view full) ---

40#ifndef __ARCH_ARM_SVE_MACROMEM_HH__
41#define __ARCH_ARM_SVE_MACROMEM_HH__
42
43#include "arch/arm/generated/decoder.hh"
44#include "arch/arm/insts/pred_inst.hh"
45
46namespace ArmISA {
47
48template <typename Element,
49 template <typename> class MicroopLdMemType,
50 template <typename> class MicroopDeIntrlvType>
51class SveLdStructSS : public PredMacroOp
52{
53 protected:
54 IntRegIndex dest;
55 IntRegIndex gp;
56 IntRegIndex base;
57 IntRegIndex offset;
58 uint8_t numregs;
59
60 public:
61 SveLdStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
62 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
63 IntRegIndex _offset, uint8_t _numregs)
64 : PredMacroOp(mnem, machInst, __opClass),
65 dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
66 {
67 numMicroops = numregs * 2;
68
69 microOps = new StaticInstPtr[numMicroops];
70
71 for (int i = 0; i < numregs; ++i) {
72 microOps[i] = new MicroopLdMemType<Element>(
73 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
74 _gp, _base, _offset, _numregs, i);
75 }
76 for (int i = 0; i < numregs; ++i) {
77 microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
78 mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
79 _numregs, i, this);
80 }
81
82 microOps[0]->setFirstMicroop();
83 microOps[numMicroops - 1]->setLastMicroop();
84
85 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
86 (*uop)->setDelayedCommit();
87 }
88 }
89
90 Fault
91 execute(ExecContext *, Trace::InstRecord *) const
92 {
93 panic("Execute method called when it shouldn't!");
94 return NoFault;
95 }
96
97 std::string
98 generateDisassembly(Addr pc, const SymbolTable *symtab) const
99 {
100 std::stringstream ss;
101 printMnemonic(ss, "", false);
102 ccprintf(ss, "{");
103 for (int i = 0; i < numregs; ++i) {
104 printVecReg(ss, (dest + i) % 32, true);
105 if (i < numregs - 1)
106 ccprintf(ss, ", ");
107 }
108 ccprintf(ss, "}, ");
109 printVecPredReg(ss, gp);
110 ccprintf(ss, "/z, [");
111 printIntReg(ss, base);
112 ccprintf(ss, ", ");
113 printIntReg(ss, offset);
114 ccprintf(ss, "]");
115 return ss.str();
116 }
117};
118
119template <typename Element,
120 template <typename> class MicroopStMemType,
121 template <typename> class MicroopIntrlvType>
122class SveStStructSS : public PredMacroOp
123{
124 protected:
125 IntRegIndex dest;
126 IntRegIndex gp;
127 IntRegIndex base;
128 IntRegIndex offset;
129 uint8_t numregs;
130
131 public:
132 SveStStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
133 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
134 IntRegIndex _offset, uint8_t _numregs)
135 : PredMacroOp(mnem, machInst, __opClass),
136 dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
137 {
138 numMicroops = numregs * 2;
139
140 microOps = new StaticInstPtr[numMicroops];
141
142 for (int i = 0; i < numregs; ++i) {
143 microOps[i] = new MicroopIntrlvType<Element>(
144 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
145 _dest, _numregs, i, this);
146 }
147
148 for (int i = 0; i < numregs; ++i) {
149 microOps[i + numregs] = new MicroopStMemType<Element>(
150 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
151 _gp, _base, _offset, _numregs, i);
152 }
153
154 microOps[0]->setFirstMicroop();
155 microOps[numMicroops - 1]->setLastMicroop();
156
157 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
158 (*uop)->setDelayedCommit();
159 }
160 }
161
162 Fault
163 execute(ExecContext *, Trace::InstRecord *) const
164 {
165 panic("Execute method called when it shouldn't!");
166 return NoFault;
167 }
168
169 std::string
170 generateDisassembly(Addr pc, const SymbolTable *symtab) const
171 {
172 std::stringstream ss;
173 printMnemonic(ss, "", false);
174 ccprintf(ss, "{");
175 for (int i = 0; i < numregs; ++i) {
176 printVecReg(ss, (dest + i) % 32, true);
177 if (i < numregs - 1)
178 ccprintf(ss, ", ");
179 }
180 ccprintf(ss, "}, ");
181 printVecPredReg(ss, gp);
182 ccprintf(ss, ", [");
183 printIntReg(ss, base);
184 ccprintf(ss, ", ");
185 printIntReg(ss, offset);
186 ccprintf(ss, "]");
187 return ss.str();
188 }
189};
190
191
192template <typename Element,
193 template <typename> class MicroopLdMemType,
194 template <typename> class MicroopDeIntrlvType>
195class SveLdStructSI : public PredMacroOp
196{
197 protected:
198 IntRegIndex dest;
199 IntRegIndex gp;
200 IntRegIndex base;
201 int64_t imm;
202 uint8_t numregs;
203
204 public:
205 SveLdStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
206 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
207 int64_t _imm, uint8_t _numregs)
208 : PredMacroOp(mnem, machInst, __opClass),
209 dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
210 {
211 numMicroops = numregs * 2;
212
213 microOps = new StaticInstPtr[numMicroops];
214
215 for (int i = 0; i < numregs; ++i) {
216 microOps[i] = new MicroopLdMemType<Element>(
217 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
218 _gp, _base, _imm, _numregs, i);
219 }
220 for (int i = 0; i < numregs; ++i) {
221 microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
222 mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
223 _numregs, i, this);
224 }
225
226 microOps[0]->setFirstMicroop();
227 microOps[numMicroops - 1]->setLastMicroop();
228
229 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
230 (*uop)->setDelayedCommit();
231 }
232 }
233
234 Fault
235 execute(ExecContext *, Trace::InstRecord *) const
236 {
237 panic("Execute method called when it shouldn't!");
238 return NoFault;
239 }
240
241 std::string
242 generateDisassembly(Addr pc, const SymbolTable *symtab) const
243 {
244 std::stringstream ss;
245 printMnemonic(ss, "", false);
246 ccprintf(ss, "{");
247 for (int i = 0; i < numregs; ++i) {
248 printVecReg(ss, (dest + i) % 32, true);
249 if (i < numregs - 1)
250 ccprintf(ss, ", ");
251 }
252 ccprintf(ss, "}, ");
253 printVecPredReg(ss, gp);
254 ccprintf(ss, "/z, [");
255 printIntReg(ss, base);
256 if (imm != 0) {
257 ccprintf(ss, ", #%d, MUL VL", imm);
258 }
259 ccprintf(ss, "]");
260 return ss.str();
261 }
262};
263
264template <typename Element,
265 template <typename> class MicroopStMemType,
266 template <typename> class MicroopIntrlvType>
267class SveStStructSI : public PredMacroOp
268{
269 protected:
270 IntRegIndex dest;
271 IntRegIndex gp;
272 IntRegIndex base;
273 int64_t imm;
274 uint8_t numregs;
275
276 public:
277 SveStStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
278 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
279 int64_t _imm, uint8_t _numregs)
280 : PredMacroOp(mnem, machInst, __opClass),
281 dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
282 {
283 numMicroops = numregs * 2;
284
285 microOps = new StaticInstPtr[numMicroops];
286
287 for (int i = 0; i < numregs; ++i) {
288 microOps[i] = new MicroopIntrlvType<Element>(
289 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
290 _dest, _numregs, i, this);
291 }
292
293 for (int i = 0; i < numregs; ++i) {
294 microOps[i + numregs] = new MicroopStMemType<Element>(
295 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
296 _gp, _base, _imm, _numregs, i);
297 }
298
299 microOps[0]->setFirstMicroop();
300 microOps[numMicroops - 1]->setLastMicroop();
301
302 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
303 (*uop)->setDelayedCommit();
304 }
305 }
306
307 Fault
308 execute(ExecContext *, Trace::InstRecord *) const
309 {
310 panic("Execute method called when it shouldn't!");
311 return NoFault;
312 }
313
314 std::string
315 generateDisassembly(Addr pc, const SymbolTable *symtab) const
316 {
317 std::stringstream ss;
318 printMnemonic(ss, "", false);
319 ccprintf(ss, "{");
320 for (int i = 0; i < numregs; ++i) {
321 printVecReg(ss, (dest + i) % 32, true);
322 if (i < numregs - 1)
323 ccprintf(ss, ", ");
324 }
325 ccprintf(ss, "}, ");
326 printVecPredReg(ss, gp);
327 ccprintf(ss, ", [");
328 printIntReg(ss, base);
329 if (imm != 0) {
330 ccprintf(ss, ", #%d, MUL VL", imm);
331 }
332 ccprintf(ss, "]");
333 return ss.str();
334 }
335};
336
48template <typename RegElemType, typename MemElemType,
49 template <typename, typename> class MicroopType,
50 template <typename> class FirstFaultWritebackMicroopType>
51class SveIndexedMemVI : public PredMacroOp
52{
53 protected:
54 IntRegIndex dest;
55 IntRegIndex gp;

--- 194 unchanged lines hidden --- 		337template <typename RegElemType, typename MemElemType,
338 template <typename, typename> class MicroopType,
339 template <typename> class FirstFaultWritebackMicroopType>
340class SveIndexedMemVI : public PredMacroOp
341{
342 protected:
343 IntRegIndex dest;
344 IntRegIndex gp;

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