1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41#define __ARCH_ARM_SVE_MACROMEM_HH__
42
43#include "arch/arm/generated/decoder.hh"
44#include "arch/arm/insts/pred_inst.hh"
45
46namespace ArmISA {
47
48template <typename RegElemType, typename MemElemType,
49 template <typename, typename> class MicroopType>
50class SveIndexedMemVI : public PredMacroOp
51{
52 protected:
53 IntRegIndex dest;
54 IntRegIndex gp;
55 IntRegIndex base;
56 uint64_t imm;
57
58 public:
59 SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass,
60 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
61 uint64_t _imm)
62 : PredMacroOp(mnem, machInst, __opClass),
63 dest(_dest), gp(_gp), base(_base), imm(_imm)
64 {
65 bool isLoad = (__opClass == MemReadOp);
66
67 int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
68
69 numMicroops = num_elems;
70 if (isLoad) {
71 numMicroops++;
72 }
73
74 microOps = new StaticInstPtr[numMicroops];
75
76 StaticInstPtr *uop = microOps;
77
78 if (isLoad) {
79 // The first microop of a gather load copies the source vector

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85 mnem, machInst, _base, this);
86 uop++;
87 }
88
89 for (int i = 0; i < num_elems; i++, uop++) {
90 *uop = new MicroopType<RegElemType, MemElemType>(
91 mnem, machInst, __opClass, _dest, _gp,
92 isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
93 num_elems);
94 }
95
96 --uop;
97 (*uop)->setLastMicroop();
98 microOps[0]->setFirstMicroop();
99
100 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
101 (*uop)->setDelayedCommit();
102 }
103 }
104

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125 ccprintf(ss, ", #%d", imm * sizeof(MemElemType));
126 }
127 ccprintf(ss, "]");
128 return ss.str();
129 }
130};
131
132template <typename RegElemType, typename MemElemType,
133 template <typename, typename> class MicroopType>
134class SveIndexedMemSV : public PredMacroOp
135{
136 protected:
137 IntRegIndex dest;
138 IntRegIndex gp;
139 IntRegIndex base;
140 IntRegIndex offset;
141
142 bool offsetIs32;
143 bool offsetIsSigned;
144 bool offsetIsScaled;
145
146 public:
147 SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass,
148 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
149 IntRegIndex _offset, bool _offsetIs32,
150 bool _offsetIsSigned, bool _offsetIsScaled)
151 : PredMacroOp(mnem, machInst, __opClass),
152 dest(_dest), gp(_gp), base(_base), offset(_offset),
153 offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
154 offsetIsScaled(_offsetIsScaled)
155 {
156 bool isLoad = (__opClass == MemReadOp);
157
158 int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
159
160 numMicroops = num_elems;
161 if (isLoad) {
162 numMicroops++;
163 }
164
165 microOps = new StaticInstPtr[numMicroops];
166
167 StaticInstPtr *uop = microOps;
168
169 if (isLoad) {
170 // The first microop of a gather load copies the source vector

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176 mnem, machInst, _offset, this);
177 uop++;
178 }
179
180 for (int i = 0; i < num_elems; i++, uop++) {
181 *uop = new MicroopType<RegElemType, MemElemType>(
182 mnem, machInst, __opClass, _dest, _gp, _base,
183 isLoad ? (IntRegIndex) VECREG_UREG0 : _offset, _offsetIs32,
184 _offsetIsSigned, _offsetIsScaled, i, num_elems);
185 }
186
187 --uop;
188 (*uop)->setLastMicroop();
189 microOps[0]->setFirstMicroop();
190
191 for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
192 (*uop)->setDelayedCommit();
193 }
194 }
195

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