static_inst.hh (8809:bb10807da889) static_inst.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "arch/arm/utility.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "arch/arm/utility.hh"
47#include "arch/arm/system.hh"
47#include "base/trace.hh"
48#include "cpu/static_inst.hh"
49#include "sim/byteswap.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55class ArmStaticInst : public StaticInst
56{
57 protected:
48#include "base/trace.hh"
49#include "cpu/static_inst.hh"
50#include "sim/byteswap.hh"
51#include "sim/full_system.hh"
52
53namespace ArmISA
54{
55
56class ArmStaticInst : public StaticInst
57{
58 protected:
59 bool aarch64;
60 uint8_t intWidth;
61
58 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool shift_carry_imm(uint32_t base, uint32_t shamt,
64 uint32_t type, uint32_t cfval) const;
65 bool shift_carry_rs(uint32_t base, uint32_t shamt,
66 uint32_t type, uint32_t cfval) const;
67
62 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
63 uint32_t type, uint32_t cfval) const;
64 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
65 uint32_t type, uint32_t cfval) const;
66
67 bool shift_carry_imm(uint32_t base, uint32_t shamt,
68 uint32_t type, uint32_t cfval) const;
69 bool shift_carry_rs(uint32_t base, uint32_t shamt,
70 uint32_t type, uint32_t cfval) const;
71
72 int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
73 ArmShiftType type, uint8_t width) const;
74 int64_t extendReg64(uint64_t base, ArmExtendType type,
75 uint64_t shiftAmt, uint8_t width) const;
76
68 template<int width>
69 static inline bool
70 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
71 {
72 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
73 if (bits(midRes, width) != bits(midRes, width - 1)) {
74 if (midRes > 0)
75 res = (LL(1) << (width - 1)) - 1;

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130 }
131 }
132
133 // Constructor
134 ArmStaticInst(const char *mnem, ExtMachInst _machInst,
135 OpClass __opClass)
136 : StaticInst(mnem, _machInst, __opClass)
137 {
77 template<int width>
78 static inline bool
79 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
80 {
81 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
82 if (bits(midRes, width) != bits(midRes, width - 1)) {
83 if (midRes > 0)
84 res = (LL(1) << (width - 1)) - 1;

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139 }
140 }
141
142 // Constructor
143 ArmStaticInst(const char *mnem, ExtMachInst _machInst,
144 OpClass __opClass)
145 : StaticInst(mnem, _machInst, __opClass)
146 {
147 aarch64 = machInst.aarch64;
148 if (bits(machInst, 28, 24) == 0x10)
149 intWidth = 64; // Force 64-bit width for ADR/ADRP
150 else
151 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
138 }
139
140 /// Print a register name for disassembly given the unique
141 /// dependence tag number (FP or int).
142 void printReg(std::ostream &os, int reg) const;
143 void printMnemonic(std::ostream &os,
144 const std::string &suffix = "",
152 }
153
154 /// Print a register name for disassembly given the unique
155 /// dependence tag number (FP or int).
156 void printReg(std::ostream &os, int reg) const;
157 void printMnemonic(std::ostream &os,
158 const std::string &suffix = "",
145 bool withPred = true) const;
159 bool withPred = true,
160 bool withCond64 = false,
161 ConditionCode cond64 = COND_UC) const;
162 void printTarget(std::ostream &os, Addr target,
163 const SymbolTable *symtab) const;
164 void printCondition(std::ostream &os, unsigned code,
165 bool noImplicit=false) const;
146 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
147 const std::string &prefix, const Addr addr,
148 const std::string &suffix) const;
149 void printShiftOperand(std::ostream &os, IntRegIndex rm,
150 bool immShift, uint32_t shiftAmt,
151 IntRegIndex rs, ArmShiftType type) const;
166 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
167 const std::string &prefix, const Addr addr,
168 const std::string &suffix) const;
169 void printShiftOperand(std::ostream &os, IntRegIndex rm,
170 bool immShift, uint32_t shiftAmt,
171 IntRegIndex rs, ArmShiftType type) const;
172 void printExtendOperand(bool firstOperand, std::ostream &os,
173 IntRegIndex rm, ArmExtendType type,
174 int64_t shiftAmt) const;
152
153
154 void printDataInst(std::ostream &os, bool withImm) const;
155 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
156 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
157 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
158 uint32_t imm) const;
159
160 void
161 advancePC(PCState &pcState) const
162 {
163 pcState.advance();
164 }
165
166 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
167
168 static inline uint32_t
175
176
177 void printDataInst(std::ostream &os, bool withImm) const;
178 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
179 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
180 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
181 uint32_t imm) const;
182
183 void
184 advancePC(PCState &pcState) const
185 {
186 pcState.advance();
187 }
188
189 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
190
191 static inline uint32_t
169 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
170 uint8_t byteMask, bool affectState, bool nmfi)
192 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
193 uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
171 {
194 {
172 bool privileged = (cpsr.mode != MODE_USER);
195 bool privileged = (cpsr.mode != MODE_USER);
196 bool haveVirt = ArmSystem::haveVirtualization(tc);
197 bool haveSecurity = ArmSystem::haveSecurity(tc);
198 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity;
173
174 uint32_t bitMask = 0;
175
176 if (bits(byteMask, 3)) {
177 unsigned lowIdx = affectState ? 24 : 27;
178 bitMask = bitMask | mask(31, lowIdx);
179 }
180 if (bits(byteMask, 2)) {
181 bitMask = bitMask | mask(19, 16);
182 }
183 if (bits(byteMask, 1)) {
184 unsigned highIdx = affectState ? 15 : 9;
199
200 uint32_t bitMask = 0;
201
202 if (bits(byteMask, 3)) {
203 unsigned lowIdx = affectState ? 24 : 27;
204 bitMask = bitMask | mask(31, lowIdx);
205 }
206 if (bits(byteMask, 2)) {
207 bitMask = bitMask | mask(19, 16);
208 }
209 if (bits(byteMask, 1)) {
210 unsigned highIdx = affectState ? 15 : 9;
185 unsigned lowIdx = privileged ? 8 : 9;
211 unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
212 ? 8 : 9;
186 bitMask = bitMask | mask(highIdx, lowIdx);
187 }
188 if (bits(byteMask, 0)) {
189 if (privileged) {
213 bitMask = bitMask | mask(highIdx, lowIdx);
214 }
215 if (bits(byteMask, 0)) {
216 if (privileged) {
190 bitMask = bitMask | mask(7, 6);
191 if (!badMode((OperatingMode)(val & mask(5)))) {
192 bitMask = bitMask | mask(5);
217 bitMask |= 1 << 7;
218 if ( (!nmfi || !((val >> 6) & 0x1)) &&
219 (isSecure || scr.fw || haveVirt) ) {
220 bitMask |= 1 << 6;
221 }
222 // Now check the new mode is allowed
223 OperatingMode newMode = (OperatingMode) (val & mask(5));
224 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
225 if (!badMode(newMode)) {
226 bool validModeChange = true;
227 // Check for attempts to enter modes only permitted in
228 // Secure state from Non-secure state. These are Monitor
229 // mode ('10110'), and FIQ mode ('10001') if the Security
230 // Extensions have reserved it.
231 if (!isSecure && newMode == MODE_MON)
232 validModeChange = false;
233 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
234 validModeChange = false;
235 // There is no Hyp mode ('11010') in Secure state, so that
236 // is UNPREDICTABLE
237 if (scr.ns == '0' && newMode == MODE_HYP)
238 validModeChange = false;
239 // Cannot move into Hyp mode directly from a Non-secure
240 // PL1 mode
241 if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
242 validModeChange = false;
243 // Cannot move out of Hyp mode with this function except
244 // on an exception return
245 if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
246 validModeChange = false;
247 // Must not change to 64 bit when running in 32 bit mode
248 if (!opModeIs64(oldMode) && opModeIs64(newMode))
249 validModeChange = false;
250
251 // If we passed all of the above then set the bit mask to
252 // copy the mode accross
253 if (validModeChange) {
254 bitMask = bitMask | mask(5);
255 } else {
256 warn_once("Illegal change to CPSR mode attempted\n");
257 }
193 } else {
194 warn_once("Ignoring write of bad mode to CPSR.\n");
195 }
196 }
197 if (affectState)
198 bitMask = bitMask | (1 << 5);
199 }
200
258 } else {
259 warn_once("Ignoring write of bad mode to CPSR.\n");
260 }
261 }
262 if (affectState)
263 bitMask = bitMask | (1 << 5);
264 }
265
201 bool cpsr_f = cpsr.f;
202 uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
203 if (nmfi && !cpsr_f)
204 new_cpsr &= ~(1 << 6);
205 return new_cpsr;
266 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
206 }
207
208 static inline uint32_t
209 spsrWriteByInstr(uint32_t spsr, uint32_t val,
210 uint8_t byteMask, bool affectState)
211 {
212 uint32_t bitMask = 0;
213

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291 PCState pc = xc->pcState();
292 pc.instAIWNPC(val);
293 xc->pcState(pc);
294 }
295
296 inline Fault
297 disabledFault() const
298 {
267 }
268
269 static inline uint32_t
270 spsrWriteByInstr(uint32_t spsr, uint32_t val,
271 uint8_t byteMask, bool affectState)
272 {
273 uint32_t bitMask = 0;
274

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352 PCState pc = xc->pcState();
353 pc.instAIWNPC(val);
354 xc->pcState(pc);
355 }
356
357 inline Fault
358 disabledFault() const
359 {
299 if (FullSystem) {
300 return new UndefinedInstruction();
301 } else {
302 return new UndefinedInstruction(machInst, false, mnemonic, true);
303 }
360 return new UndefinedInstruction(machInst, false, mnemonic, true);
304 }
361 }
362
363 public:
364 virtual void
365 annotateFault(ArmFault *fault) {}
305};
306}
307
308#endif //__ARCH_ARM_INSTS_STATICINST_HH__
366};
367}
368
369#endif //__ARCH_ARM_INSTS_STATICINST_HH__